LXR linux/arch/arc/plat-eznps/entry.S

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*******************************************************************************
   3
   4  EZNPS CPU startup Code
   5  Copyright(c) 2012 EZchip Technologies.
   6
   7
   8*******************************************************************************/
   9#include <linux/linkage.h>
  10#include <asm/entry.h>
  11#include <asm/cache.h>
  12#include <plat/ctop.h>
  13
  14        .cpu A7
  15
  16        .section .init.text, "ax",@progbits
  17        .align 1024     ; HW requierment for restart first PC
  18
  19ENTRY(res_service)
  20#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
  21        ; There is no work for HW thread id != 0
  22        lr      r3, [CTOP_AUX_THREAD_ID]
  23        cmp     r3, 0
  24        jne     stext
  25#endif
  26
  27#ifdef CONFIG_ARC_HAS_DCACHE
  28        ; With no cache coherency mechanism D$ need to be used very carefully.
  29        ; Address space:
  30        ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES.
  31        ; 2G-3G: We disable D$ by setting this bit.
  32        ; 3G-4G: D$ is disabled by architecture.
  33        ; FMT are huge pages for user application reside at 0-2G.
  34        ; Only FMT left as one who can use D$ where each such page got
  35        ; disable/enable bit for cachability.
  36        ; Programmer will use FMT pages for private data so cache coherency
  37        ; would not be a problem.
  38        ; First thing we invalidate D$
  39        sr      1, [ARC_REG_DC_IVDC]
  40        sr      HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY]
  41#endif
  42
  43#ifdef CONFIG_SMP
  44        ; We set logical cpuid to be used by GET_CPUID
  45        ; We do not use physical cpuid since we want ids to be continious when
  46        ; it comes to cpus on the same quad cluster.
  47        ; This is useful for applications that used shared resources of a quad
  48        ; cluster such SRAMS.
  49        lr      r3, [CTOP_AUX_CORE_ID]
  50        sr      r3, [CTOP_AUX_LOGIC_CORE_ID]
  51        lr      r3, [CTOP_AUX_CLUSTER_ID]
  52        ; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit)
  53        ; r3 is used since we use short instruction and we need q-class reg
  54        .short  CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST
  55        .word   CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM
  56         sr     r3, [CTOP_AUX_LOGIC_CLUSTER_ID]
  57#endif
  58
  59        j       stext
  60END(res_service)
  61