LXR linux/arch/arm/mach-prima2/rstc.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * reset controller for CSR SiRFprimaII
   4 *
   5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6 */
   7
   8#include <linux/kernel.h>
   9#include <linux/mutex.h>
  10#include <linux/io.h>
  11#include <linux/delay.h>
  12#include <linux/device.h>
  13#include <linux/of.h>
  14#include <linux/of_address.h>
  15#include <linux/platform_device.h>
  16#include <linux/reboot.h>
  17#include <linux/reset-controller.h>
  18
  19#include <asm/system_misc.h>
  20
  21#define SIRFSOC_RSTBIT_NUM      64
  22
  23static void __iomem *sirfsoc_rstc_base;
  24static DEFINE_MUTEX(rstc_lock);
  25
  26static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
  27                                        unsigned long sw_reset_idx)
  28{
  29        u32 reset_bit = sw_reset_idx;
  30
  31        if (reset_bit >= SIRFSOC_RSTBIT_NUM)
  32                return -EINVAL;
  33
  34        mutex_lock(&rstc_lock);
  35
  36        /*
  37         * Writing 1 to this bit resets corresponding block.
  38         * Writing 0 to this bit de-asserts reset signal of the
  39         * corresponding block. datasheet doesn't require explicit
  40         * delay between the set and clear of reset bit. it could
  41         * be shorter if tests pass.
  42         */
  43        writel(readl(sirfsoc_rstc_base +
  44                        (reset_bit / 32) * 4) | (1 << reset_bit),
  45                sirfsoc_rstc_base + (reset_bit / 32) * 4);
  46        msleep(20);
  47        writel(readl(sirfsoc_rstc_base +
  48                        (reset_bit / 32) * 4) & ~(1 << reset_bit),
  49                sirfsoc_rstc_base + (reset_bit / 32) * 4);
  50
  51        mutex_unlock(&rstc_lock);
  52
  53        return 0;
  54}
  55
  56static struct reset_control_ops sirfsoc_rstc_ops = {
  57        .reset = sirfsoc_reset_module,
  58};
  59
  60static struct reset_controller_dev sirfsoc_reset_controller = {
  61        .ops = &sirfsoc_rstc_ops,
  62        .nr_resets = SIRFSOC_RSTBIT_NUM,
  63};
  64
  65#define SIRFSOC_SYS_RST_BIT  BIT(31)
  66
  67static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
  68{
  69        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
  70}
  71
  72static int sirfsoc_rstc_probe(struct platform_device *pdev)
  73{
  74        struct device_node *np = pdev->dev.of_node;
  75        sirfsoc_rstc_base = of_iomap(np, 0);
  76        if (!sirfsoc_rstc_base) {
  77                dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
  78                return -ENOMEM;
  79        }
  80
  81        sirfsoc_reset_controller.of_node = np;
  82        arm_pm_restart = sirfsoc_restart;
  83
  84        if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
  85                reset_controller_register(&sirfsoc_reset_controller);
  86
  87        return 0;
  88}
  89
  90static const struct of_device_id rstc_ids[]  = {
  91        { .compatible = "sirf,prima2-rstc" },
  92        {},
  93};
  94
  95static struct platform_driver sirfsoc_rstc_driver = {
  96        .probe          = sirfsoc_rstc_probe,
  97        .driver         = {
  98                .name   = "sirfsoc_rstc",
  99                .of_match_table = rstc_ids,
 100        },
 101};
 102
 103static int __init sirfsoc_rstc_init(void)
 104{
 105        return platform_driver_register(&sirfsoc_rstc_driver);
 106}
 107subsys_initcall(sirfsoc_rstc_init);
 108