1#ifndef __PARISC_PATPDC_H
2#define __PARISC_PATPDC_H
3
4
5
6
7
8
9
10
11
12
13
14#define PDC_PAT_CELL 64L
15
16#define PDC_PAT_CELL_GET_NUMBER 0L
17#define PDC_PAT_CELL_GET_INFO 1L
18#define PDC_PAT_CELL_MODULE 2L
19#define PDC_PAT_CELL_SET_ATTENTION 9L
20#define PDC_PAT_CELL_NUMBER_TO_LOC 10L
21#define PDC_PAT_CELL_WALK_FABRIC 11L
22#define PDC_PAT_CELL_GET_RDT_SIZE 12L
23#define PDC_PAT_CELL_GET_RDT 13L
24#define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L
25#define PDC_PAT_CELL_SET_LOCAL_PDH 15L
26#define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L
27#define PDC_PAT_CELL_GET_REMOTE_PDH 17L
28#define PDC_PAT_CELL_GET_DBG_INFO 128L
29#define PDC_PAT_CELL_CHANGE_ALIAS 129L
30
31
32
33
34
35
36
37
38#define IO_VIEW 0UL
39#define PA_VIEW 1UL
40
41
42#define PAT_ENTITY_CA 0
43#define PAT_ENTITY_PROC 1
44#define PAT_ENTITY_MEM 2
45#define PAT_ENTITY_SBA 3
46#define PAT_ENTITY_LBA 4
47#define PAT_ENTITY_PBC 5
48#define PAT_ENTITY_XBC 6
49#define PAT_ENTITY_RC 7
50
51
52#define PAT_PBNUM 0
53#define PAT_LMMIO 1
54#define PAT_GMMIO 2
55#define PAT_NPIOP 3
56#define PAT_PIOP 4
57#define PAT_AHPA 5
58#define PAT_UFO 6
59#define PAT_GNIP 7
60
61
62
63
64
65#define PDC_PAT_CHASSIS_LOG 65L
66#define PDC_PAT_CHASSIS_WRITE_LOG 0L
67#define PDC_PAT_CHASSIS_READ_LOG 1L
68
69
70
71
72#define PDC_PAT_COMPLEX 66L
73
74
75
76#define PDC_PAT_CPU 67L
77#define PDC_PAT_CPU_INFO 0L
78#define PDC_PAT_CPU_DELETE 1L
79#define PDC_PAT_CPU_ADD 2L
80#define PDC_PAT_CPU_GET_NUMBER 3L
81#define PDC_PAT_CPU_GET_HPA 4L
82#define PDC_PAT_CPU_STOP 5L
83#define PDC_PAT_CPU_RENDEZVOUS 6L
84#define PDC_PAT_CPU_GET_CLOCK_INFO 7L
85#define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L
86#define PDC_PAT_CPU_PLUNGE_FABRIC 128L
87#define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L
88
89
90
91#define PDC_PAT_EVENT 68L
92#define PDC_PAT_EVENT_GET_CAPS 0L
93#define PDC_PAT_EVENT_SET_MODE 1L
94#define PDC_PAT_EVENT_SCAN 2L
95#define PDC_PAT_EVENT_HANDLE 3L
96#define PDC_PAT_EVENT_GET_NB_CALL 4L
97
98
99
100
101
102#define PDC_PAT_HPMC 70L
103#define PDC_PAT_HPMC_RENDEZ_CPU 0L
104#define PDC_PAT_HPMC_SET_PARAMS 1L
105
106
107
108
109#define HPMC_SET_PARAMS_INTR 1L
110#define HPMC_SET_PARAMS_WAKE 2L
111
112
113
114
115#define PDC_PAT_IO 71L
116#define PDC_PAT_IO_GET_SLOT_STATUS 5L
117#define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L
118
119#define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L
120
121#define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L
122
123#define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L
124
125#define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L
126#define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L
127#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L
128
129#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L
130#define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L
131#define PDC_PAT_IO_GET_HINT_TABLE 18L
132#define PDC_PAT_IO_PCI_CONFIG_READ 19L
133#define PDC_PAT_IO_PCI_CONFIG_WRITE 20L
134#define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L
135
136#define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L
137
138#define PDC_PAT_IO_BAY_STATUS_INFO 28L
139#define PDC_PAT_IO_GET_PROC_VIEW 29L
140#define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L
141
142
143
144
145#define PDC_PAT_MEM 72L
146#define PDC_PAT_MEM_PD_INFO 0L
147#define PDC_PAT_MEM_PD_CLEAR 1L
148#define PDC_PAT_MEM_PD_READ 2L
149#define PDC_PAT_MEM_PD_RESET 3L
150#define PDC_PAT_MEM_CELL_INFO 5L
151#define PDC_PAT_MEM_CELL_CLEAR 6L
152#define PDC_PAT_MEM_CELL_READ 7L
153#define PDC_PAT_MEM_CELL_RESET 8L
154#define PDC_PAT_MEM_SETGM 9L
155#define PDC_PAT_MEM_ADD_PAGE 10L
156#define PDC_PAT_MEM_ADDRESS 11L
157
158#define PDC_PAT_MEM_GET_TXT_SIZE 12L
159#define PDC_PAT_MEM_GET_PD_TXT 13L
160#define PDC_PAT_MEM_GET_CELL_TXT 14L
161#define PDC_PAT_MEM_RD_STATE_INFO 15L
162#define PDC_PAT_MEM_CLR_STATE_INFO 16L
163#define PDC_PAT_MEM_CLEAN_RANGE 128L
164#define PDC_PAT_MEM_GET_TBL_SIZE 131L
165#define PDC_PAT_MEM_GET_TBL 132L
166
167
168
169
170#define PDC_PAT_NVOLATILE 73L
171#define PDC_PAT_NVOLATILE_READ 0L
172#define PDC_PAT_NVOLATILE_WRITE 1L
173#define PDC_PAT_NVOLATILE_GET_SIZE 2L
174#define PDC_PAT_NVOLATILE_VERIFY 3L
175#define PDC_PAT_NVOLATILE_INIT 4L
176
177
178#define PDC_PAT_PD 74L
179#define PDC_PAT_PD_GET_ADDR_MAP 0L
180#define PDC_PAT_PD_GET_PDC_INTERF_REV 1L
181
182#define PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE (1UL << 0)
183#define PDC_PAT_CAPABILITY_BIT_PDC_POLLING (1UL << 1)
184#define PDC_PAT_CAPABILITY_BIT_PDC_NBC (1UL << 2)
185#define PDC_PAT_CAPABILITY_BIT_PDC_UFO (1UL << 3)
186#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32 (1UL << 4)
187#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_64 (1UL << 5)
188#define PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ (1UL << 6)
189#define PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB (1UL << 7)
190
191
192#define PAT_MEMORY_DESCRIPTOR 1
193
194
195#define PAT_MEMTYPE_MEMORY 0
196#define PAT_MEMTYPE_FIRMWARE 4
197
198
199#define PAT_MEMUSE_GENERAL 0
200#define PAT_MEMUSE_GI 128
201#define PAT_MEMUSE_GNI 129
202
203
204#define PDC_PAT_REGISTER_TOC 75L
205#define PDC_PAT_TOC_REGISTER_VECTOR 0L
206#define PDC_PAT_TOC_READ_VECTOR 1L
207
208
209#define PDC_PAT_SYSTEM_INFO 76L
210
211
212#ifndef __ASSEMBLY__
213#include <linux/types.h>
214
215#ifdef CONFIG_64BIT
216#define is_pdc_pat() (PDC_TYPE_PAT == pdc_type)
217extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
218extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
219#else
220
221#define is_pdc_pat() (0)
222#define pdc_pat_get_irt_size(num_entries, cell_numn) PDC_BAD_PROC
223#define pdc_pat_get_irt(r_addr, cell_num) PDC_BAD_PROC
224#endif
225
226
227struct pdc_pat_cell_num {
228 unsigned long cell_num;
229 unsigned long cell_loc;
230};
231
232struct pdc_pat_cpu_num {
233 unsigned long cpu_num;
234 unsigned long cpu_loc;
235};
236
237struct pdc_pat_mem_retinfo {
238 unsigned int ke;
239 unsigned int current_pdt_entries:16;
240 unsigned int max_pdt_entries:16;
241 unsigned long Cs_bitmap;
242 unsigned long Ic_bitmap;
243 unsigned long good_mem;
244 unsigned long first_dbe_loc;
245 unsigned long clear_time;
246};
247
248struct pdc_pat_mem_cell_pdt_retinfo {
249 u64 reserved:32;
250 u64 cs:1;
251 u64 current_pdt_entries:15;
252 u64 ic:1;
253 u64 max_pdt_entries:15;
254 unsigned long good_mem;
255 unsigned long first_dbe_loc;
256 unsigned long clear_time;
257};
258
259
260struct pdc_pat_mem_read_pd_retinfo {
261 unsigned long actual_count_bytes;
262 unsigned long pdt_entries;
263};
264
265struct pdc_pat_mem_phys_mem_location {
266 u64 cabinet:8;
267 u64 ign1:8;
268 u64 ign2:8;
269 u64 cell_slot:8;
270 u64 ign3:8;
271 u64 dimm_slot:8;
272 u64 ign4:8;
273 u64 source:4;
274 u64 source_detail:4;
275};
276
277struct pdc_pat_pd_addr_map_entry {
278 unsigned char entry_type;
279 unsigned char reserve1[5];
280 unsigned char memory_type;
281 unsigned char memory_usage;
282 unsigned long paddr;
283 unsigned int pages;
284 unsigned int reserve2;
285 unsigned long cell_map;
286};
287
288
289
290
291
292
293
294
295#define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312#define PAT_GET_ENTITY(value) (((value) >> 56) & 0xffUL)
313#define PAT_GET_DVI(value) (((value) >> 48) & 0xffUL)
314#define PAT_GET_IOC(value) (((value) >> 40) & 0xffUL)
315#define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
316
317
318
319
320
321typedef struct pdc_pat_cell_info_rtn_block {
322 unsigned long pdc_rev;
323 unsigned long capabilities;
324 unsigned long reserved0[2];
325 unsigned long cell_info;
326 unsigned long cell_phys_location;
327 unsigned long cpu_info;
328 unsigned long cpu_speed;
329 unsigned long io_chassis_phys_location;
330 unsigned long cell_io_information;
331 unsigned long reserved1[2];
332 unsigned long io_slot_info_size;
333 struct {
334 unsigned long header, info0, info1;
335 unsigned long phys_loc, hw_path;
336 } io_slot[16];
337 unsigned long cell_mem_size;
338 unsigned long cell_dimm_info_size;
339 unsigned long dimm_info[16];
340 unsigned long fabric_info_size;
341 struct {
342 unsigned long fabric_info_xbc_port;
343 unsigned long rc_attached_to_xbc;
344 } xbc[8*4];
345} pdc_pat_cell_info_rtn_block_t;
346
347
348
349struct pdc_pat_cell_mod_maddr_block {
350 unsigned long cba;
351 unsigned long mod_info;
352 unsigned long mod_location;
353 struct hardware_path mod_path;
354 unsigned long mod[508];
355} __attribute__((aligned(8))) ;
356
357typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
358
359
360extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
361extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
362extern int pdc_pat_cell_info(struct pdc_pat_cell_info_rtn_block *info,
363 unsigned long *actcnt, unsigned long offset,
364 unsigned long cell_number);
365extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc,
366 unsigned long mod, unsigned long view_type, void *mem_addr);
367extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
368
369extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
370
371extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr,
372 unsigned long count, unsigned long offset);
373extern int pdc_pat_pd_get_pdc_revisions(unsigned long *legacy_rev,
374 unsigned long *pat_rev, unsigned long *pdc_cap);
375
376extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val);
377extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);
378
379extern int pdc_pat_mem_pdt_info(struct pdc_pat_mem_retinfo *rinfo);
380extern int pdc_pat_mem_pdt_cell_info(struct pdc_pat_mem_cell_pdt_retinfo *rinfo,
381 unsigned long cell);
382extern int pdc_pat_mem_read_cell_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
383 unsigned long *pdt_entries_ptr, unsigned long max_entries);
384extern int pdc_pat_mem_read_pd_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
385 unsigned long *pdt_entries_ptr, unsigned long count,
386 unsigned long offset);
387extern int pdc_pat_mem_get_dimm_phys_location(
388 struct pdc_pat_mem_phys_mem_location *pret,
389 unsigned long phys_addr);
390
391#endif
392
393#endif
394