LXR linux/arch/x86/kvm/vmx/nested.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __KVM_X86_VMX_NESTED_H
   3#define __KVM_X86_VMX_NESTED_H
   4
   5#include "kvm_cache_regs.h"
   6#include "vmcs12.h"
   7#include "vmx.h"
   8
   9/*
  10 * Status returned by nested_vmx_enter_non_root_mode():
  11 */
  12enum nvmx_vmentry_status {
  13        NVMX_VMENTRY_SUCCESS,           /* Entered VMX non-root mode */
  14        NVMX_VMENTRY_VMFAIL,            /* Consistency check VMFail */
  15        NVMX_VMENTRY_VMEXIT,            /* Consistency check VMExit */
  16        NVMX_VMENTRY_KVM_INTERNAL_ERROR,/* KVM internal error */
  17};
  18
  19void vmx_leave_nested(struct kvm_vcpu *vcpu);
  20void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
  21                                bool apicv);
  22void nested_vmx_hardware_unsetup(void);
  23__init int nested_vmx_hardware_setup(int (*exit_handlers[])(struct kvm_vcpu *));
  24void nested_vmx_set_vmcs_shadowing_bitmap(void);
  25void nested_vmx_free_vcpu(struct kvm_vcpu *vcpu);
  26enum nvmx_vmentry_status nested_vmx_enter_non_root_mode(struct kvm_vcpu *vcpu,
  27                                                     bool from_vmentry);
  28bool nested_vmx_exit_reflected(struct kvm_vcpu *vcpu, u32 exit_reason);
  29void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
  30                       u32 exit_intr_info, unsigned long exit_qualification);
  31void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu);
  32int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data);
  33int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdata);
  34int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualification,
  35                        u32 vmx_instruction_info, bool wr, int len, gva_t *ret);
  36void nested_vmx_pmu_entry_exit_ctls_update(struct kvm_vcpu *vcpu);
  37
  38static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
  39{
  40        return to_vmx(vcpu)->nested.cached_vmcs12;
  41}
  42
  43static inline struct vmcs12 *get_shadow_vmcs12(struct kvm_vcpu *vcpu)
  44{
  45        return to_vmx(vcpu)->nested.cached_shadow_vmcs12;
  46}
  47
  48static inline int vmx_has_valid_vmcs12(struct kvm_vcpu *vcpu)
  49{
  50        struct vcpu_vmx *vmx = to_vmx(vcpu);
  51
  52        /*
  53         * In case we do two consecutive get/set_nested_state()s while L2 was
  54         * running hv_evmcs may end up not being mapped (we map it from
  55         * nested_vmx_run()/vmx_vcpu_run()). Check is_guest_mode() as we always
  56         * have vmcs12 if it is true.
  57         */
  58        return is_guest_mode(vcpu) || vmx->nested.current_vmptr != -1ull ||
  59                vmx->nested.hv_evmcs;
  60}
  61
  62static inline unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
  63{
  64        /* return the page table to be shadowed - in our case, EPT12 */
  65        return get_vmcs12(vcpu)->ept_pointer;
  66}
  67
  68static inline bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
  69{
  70        return nested_ept_get_cr3(vcpu) & VMX_EPTP_AD_ENABLE_BIT;
  71}
  72
  73/*
  74 * Reflect a VM Exit into L1.
  75 */
  76static inline int nested_vmx_reflect_vmexit(struct kvm_vcpu *vcpu,
  77                                            u32 exit_reason)
  78{
  79        u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
  80
  81        /*
  82         * At this point, the exit interruption info in exit_intr_info
  83         * is only valid for EXCEPTION_NMI exits.  For EXTERNAL_INTERRUPT
  84         * we need to query the in-kernel LAPIC.
  85         */
  86        WARN_ON(exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT);
  87        if ((exit_intr_info &
  88             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
  89            (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) {
  90                struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
  91
  92                vmcs12->vm_exit_intr_error_code =
  93                        vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
  94        }
  95
  96        nested_vmx_vmexit(vcpu, exit_reason, exit_intr_info,
  97                          vmcs_readl(EXIT_QUALIFICATION));
  98        return 1;
  99}
 100
 101/*
 102 * Return the cr0 value that a nested guest would read. This is a combination
 103 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
 104 * its hypervisor (cr0_read_shadow).
 105 */
 106static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
 107{
 108        return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
 109                (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
 110}
 111static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
 112{
 113        return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
 114                (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
 115}
 116
 117static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
 118{
 119        return vmx_misc_cr3_count(to_vmx(vcpu)->nested.msrs.misc_low);
 120}
 121
 122/*
 123 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
 124 * to modify any valid field of the VMCS, or are the VM-exit
 125 * information fields read-only?
 126 */
 127static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu *vcpu)
 128{
 129        return to_vmx(vcpu)->nested.msrs.misc_low &
 130                MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS;
 131}
 132
 133static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu *vcpu)
 134{
 135        return to_vmx(vcpu)->nested.msrs.misc_low & VMX_MISC_ZERO_LEN_INS;
 136}
 137
 138static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu *vcpu)
 139{
 140        return to_vmx(vcpu)->nested.msrs.procbased_ctls_high &
 141                        CPU_BASED_MONITOR_TRAP_FLAG;
 142}
 143
 144static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu *vcpu)
 145{
 146        return to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
 147                SECONDARY_EXEC_SHADOW_VMCS;
 148}
 149
 150static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 151{
 152        return vmcs12->cpu_based_vm_exec_control & bit;
 153}
 154
 155static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 156{
 157        return (vmcs12->cpu_based_vm_exec_control &
 158                        CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 159                (vmcs12->secondary_vm_exec_control & bit);
 160}
 161
 162static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
 163{
 164        return vmcs12->pin_based_vm_exec_control &
 165                PIN_BASED_VMX_PREEMPTION_TIMER;
 166}
 167
 168static inline bool nested_cpu_has_nmi_exiting(struct vmcs12 *vmcs12)
 169{
 170        return vmcs12->pin_based_vm_exec_control & PIN_BASED_NMI_EXITING;
 171}
 172
 173static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
 174{
 175        return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 176}
 177
 178static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
 179{
 180        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
 181}
 182
 183static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
 184{
 185        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
 186}
 187
 188static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
 189{
 190        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
 191}
 192
 193static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
 194{
 195        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
 196}
 197
 198static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
 199{
 200        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
 201}
 202
 203static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
 204{
 205        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
 206}
 207
 208static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
 209{
 210        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
 211}
 212
 213static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
 214{
 215        return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
 216}
 217
 218static inline bool nested_cpu_has_vmfunc(struct vmcs12 *vmcs12)
 219{
 220        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VMFUNC);
 221}
 222
 223static inline bool nested_cpu_has_eptp_switching(struct vmcs12 *vmcs12)
 224{
 225        return nested_cpu_has_vmfunc(vmcs12) &&
 226                (vmcs12->vm_function_control &
 227                 VMX_VMFUNC_EPTP_SWITCHING);
 228}
 229
 230static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12 *vmcs12)
 231{
 232        return nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS);
 233}
 234
 235static inline bool nested_cpu_has_save_preemption_timer(struct vmcs12 *vmcs12)
 236{
 237        return vmcs12->vm_exit_controls &
 238            VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
 239}
 240
 241/*
 242 * In nested virtualization, check if L1 asked to exit on external interrupts.
 243 * For most existing hypervisors, this will always return true.
 244 */
 245static inline bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
 246{
 247        return get_vmcs12(vcpu)->pin_based_vm_exec_control &
 248                PIN_BASED_EXT_INTR_MASK;
 249}
 250
 251/*
 252 * if fixed0[i] == 1: val[i] must be 1
 253 * if fixed1[i] == 0: val[i] must be 0
 254 */
 255static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
 256{
 257        return ((val & fixed1) | fixed0) == val;
 258}
 259
 260static inline bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
 261{
 262        u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
 263        u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
 264        struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
 265
 266        if (to_vmx(vcpu)->nested.msrs.secondary_ctls_high &
 267                SECONDARY_EXEC_UNRESTRICTED_GUEST &&
 268            nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
 269                fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
 270
 271        return fixed_bits_valid(val, fixed0, fixed1);
 272}
 273
 274static inline bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
 275{
 276        u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr0_fixed0;
 277        u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr0_fixed1;
 278
 279        return fixed_bits_valid(val, fixed0, fixed1);
 280}
 281
 282static inline bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
 283{
 284        u64 fixed0 = to_vmx(vcpu)->nested.msrs.cr4_fixed0;
 285        u64 fixed1 = to_vmx(vcpu)->nested.msrs.cr4_fixed1;
 286
 287        return fixed_bits_valid(val, fixed0, fixed1);
 288}
 289
 290/* No difference in the restrictions on guest and host CR4 in VMX operation. */
 291#define nested_guest_cr4_valid  nested_cr4_valid
 292#define nested_host_cr4_valid   nested_cr4_valid
 293
 294#endif /* __KVM_X86_VMX_NESTED_H */
 295