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6#include <linux/platform_device.h>
7#include <linux/mfd/syscon.h>
8#include "meson-aoclk.h"
9#include "gxbb-aoclk.h"
10
11#include "clk-regmap.h"
12#include "clk-dualdiv.h"
13
14
15#define AO_RTI_PWR_CNTL_REG1 0x0c
16#define AO_RTI_PWR_CNTL_REG0 0x10
17#define AO_RTI_GEN_CNTL_REG0 0x40
18#define AO_OSCIN_CNTL 0x58
19#define AO_CRT_CLK_CNTL1 0x68
20#define AO_RTC_ALT_CLK_CNTL0 0x94
21#define AO_RTC_ALT_CLK_CNTL1 0x98
22
23#define GXBB_AO_GATE(_name, _bit) \
24static struct clk_regmap _name##_ao = { \
25 .data = &(struct clk_regmap_gate_data) { \
26 .offset = AO_RTI_GEN_CNTL_REG0, \
27 .bit_idx = (_bit), \
28 }, \
29 .hw.init = &(struct clk_init_data) { \
30 .name = #_name "_ao", \
31 .ops = &clk_regmap_gate_ops, \
32 .parent_data = &(const struct clk_parent_data) { \
33 .fw_name = "mpeg-clk", \
34 }, \
35 .num_parents = 1, \
36 .flags = CLK_IGNORE_UNUSED, \
37 }, \
38}
39
40GXBB_AO_GATE(remote, 0);
41GXBB_AO_GATE(i2c_master, 1);
42GXBB_AO_GATE(i2c_slave, 2);
43GXBB_AO_GATE(uart1, 3);
44GXBB_AO_GATE(uart2, 5);
45GXBB_AO_GATE(ir_blaster, 6);
46
47static struct clk_regmap ao_cts_oscin = {
48 .data = &(struct clk_regmap_gate_data){
49 .offset = AO_RTI_PWR_CNTL_REG0,
50 .bit_idx = 6,
51 },
52 .hw.init = &(struct clk_init_data){
53 .name = "ao_cts_oscin",
54 .ops = &clk_regmap_gate_ro_ops,
55 .parent_data = &(const struct clk_parent_data) {
56 .fw_name = "xtal",
57 },
58 .num_parents = 1,
59 },
60};
61
62static struct clk_regmap ao_32k_pre = {
63 .data = &(struct clk_regmap_gate_data){
64 .offset = AO_RTC_ALT_CLK_CNTL0,
65 .bit_idx = 31,
66 },
67 .hw.init = &(struct clk_init_data){
68 .name = "ao_32k_pre",
69 .ops = &clk_regmap_gate_ops,
70 .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
71 .num_parents = 1,
72 },
73};
74
75static const struct meson_clk_dualdiv_param gxbb_32k_div_table[] = {
76 {
77 .dual = 1,
78 .n1 = 733,
79 .m1 = 8,
80 .n2 = 732,
81 .m2 = 11,
82 }, {}
83};
84
85static struct clk_regmap ao_32k_div = {
86 .data = &(struct meson_clk_dualdiv_data){
87 .n1 = {
88 .reg_off = AO_RTC_ALT_CLK_CNTL0,
89 .shift = 0,
90 .width = 12,
91 },
92 .n2 = {
93 .reg_off = AO_RTC_ALT_CLK_CNTL0,
94 .shift = 12,
95 .width = 12,
96 },
97 .m1 = {
98 .reg_off = AO_RTC_ALT_CLK_CNTL1,
99 .shift = 0,
100 .width = 12,
101 },
102 .m2 = {
103 .reg_off = AO_RTC_ALT_CLK_CNTL1,
104 .shift = 12,
105 .width = 12,
106 },
107 .dual = {
108 .reg_off = AO_RTC_ALT_CLK_CNTL0,
109 .shift = 28,
110 .width = 1,
111 },
112 .table = gxbb_32k_div_table,
113 },
114 .hw.init = &(struct clk_init_data){
115 .name = "ao_32k_div",
116 .ops = &meson_clk_dualdiv_ops,
117 .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
118 .num_parents = 1,
119 },
120};
121
122static struct clk_regmap ao_32k_sel = {
123 .data = &(struct clk_regmap_mux_data) {
124 .offset = AO_RTC_ALT_CLK_CNTL1,
125 .mask = 0x1,
126 .shift = 24,
127 .flags = CLK_MUX_ROUND_CLOSEST,
128 },
129 .hw.init = &(struct clk_init_data){
130 .name = "ao_32k_sel",
131 .ops = &clk_regmap_mux_ops,
132 .parent_hws = (const struct clk_hw *[]) {
133 &ao_32k_div.hw,
134 &ao_32k_pre.hw
135 },
136 .num_parents = 2,
137 .flags = CLK_SET_RATE_PARENT,
138 },
139};
140
141static struct clk_regmap ao_32k = {
142 .data = &(struct clk_regmap_gate_data){
143 .offset = AO_RTC_ALT_CLK_CNTL0,
144 .bit_idx = 30,
145 },
146 .hw.init = &(struct clk_init_data){
147 .name = "ao_32k",
148 .ops = &clk_regmap_gate_ops,
149 .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
150 .num_parents = 1,
151 .flags = CLK_SET_RATE_PARENT,
152 },
153};
154
155static struct clk_regmap ao_cts_rtc_oscin = {
156 .data = &(struct clk_regmap_mux_data) {
157 .offset = AO_RTI_PWR_CNTL_REG0,
158 .mask = 0x7,
159 .shift = 10,
160 .table = (u32[]){ 1, 2, 3, 4 },
161 .flags = CLK_MUX_ROUND_CLOSEST,
162 },
163 .hw.init = &(struct clk_init_data){
164 .name = "ao_cts_rtc_oscin",
165 .ops = &clk_regmap_mux_ops,
166 .parent_data = (const struct clk_parent_data []) {
167 { .fw_name = "ext-32k-0", },
168 { .fw_name = "ext-32k-1", },
169 { .fw_name = "ext-32k-2", },
170 { .hw = &ao_32k.hw },
171 },
172 .num_parents = 4,
173 .flags = CLK_SET_RATE_PARENT,
174 },
175};
176
177static struct clk_regmap ao_clk81 = {
178 .data = &(struct clk_regmap_mux_data) {
179 .offset = AO_RTI_PWR_CNTL_REG0,
180 .mask = 0x1,
181 .shift = 0,
182 .flags = CLK_MUX_ROUND_CLOSEST,
183 },
184 .hw.init = &(struct clk_init_data){
185 .name = "ao_clk81",
186 .ops = &clk_regmap_mux_ro_ops,
187 .parent_data = (const struct clk_parent_data []) {
188 { .fw_name = "mpeg-clk", },
189 { .hw = &ao_cts_rtc_oscin.hw },
190 },
191 .num_parents = 2,
192 .flags = CLK_SET_RATE_PARENT,
193 },
194};
195
196static struct clk_regmap ao_cts_cec = {
197 .data = &(struct clk_regmap_mux_data) {
198 .offset = AO_CRT_CLK_CNTL1,
199 .mask = 0x1,
200 .shift = 27,
201 .flags = CLK_MUX_ROUND_CLOSEST,
202 },
203 .hw.init = &(struct clk_init_data){
204 .name = "ao_cts_cec",
205 .ops = &clk_regmap_mux_ops,
206
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218
219 .parent_data = (const struct clk_parent_data []) {
220 { .name = "fixme", .index = -1, },
221 { .hw = &ao_cts_rtc_oscin.hw },
222 },
223 .num_parents = 2,
224 .flags = CLK_SET_RATE_PARENT,
225 },
226};
227
228static const unsigned int gxbb_aoclk_reset[] = {
229 [RESET_AO_REMOTE] = 16,
230 [RESET_AO_I2C_MASTER] = 18,
231 [RESET_AO_I2C_SLAVE] = 19,
232 [RESET_AO_UART1] = 17,
233 [RESET_AO_UART2] = 22,
234 [RESET_AO_IR_BLASTER] = 23,
235};
236
237static struct clk_regmap *gxbb_aoclk[] = {
238 &remote_ao,
239 &i2c_master_ao,
240 &i2c_slave_ao,
241 &uart1_ao,
242 &uart2_ao,
243 &ir_blaster_ao,
244 &ao_cts_oscin,
245 &ao_32k_pre,
246 &ao_32k_div,
247 &ao_32k_sel,
248 &ao_32k,
249 &ao_cts_rtc_oscin,
250 &ao_clk81,
251 &ao_cts_cec,
252};
253
254static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
255 .hws = {
256 [CLKID_AO_REMOTE] = &remote_ao.hw,
257 [CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
258 [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
259 [CLKID_AO_UART1] = &uart1_ao.hw,
260 [CLKID_AO_UART2] = &uart2_ao.hw,
261 [CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,
262 [CLKID_AO_CEC_32K] = &ao_cts_cec.hw,
263 [CLKID_AO_CTS_OSCIN] = &ao_cts_oscin.hw,
264 [CLKID_AO_32K_PRE] = &ao_32k_pre.hw,
265 [CLKID_AO_32K_DIV] = &ao_32k_div.hw,
266 [CLKID_AO_32K_SEL] = &ao_32k_sel.hw,
267 [CLKID_AO_32K] = &ao_32k.hw,
268 [CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
269 [CLKID_AO_CLK81] = &ao_clk81.hw,
270 },
271 .num = NR_CLKS,
272};
273
274static const struct meson_aoclk_data gxbb_aoclkc_data = {
275 .reset_reg = AO_RTI_GEN_CNTL_REG0,
276 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
277 .reset = gxbb_aoclk_reset,
278 .num_clks = ARRAY_SIZE(gxbb_aoclk),
279 .clks = gxbb_aoclk,
280 .hw_data = &gxbb_aoclk_onecell_data,
281};
282
283static const struct of_device_id gxbb_aoclkc_match_table[] = {
284 {
285 .compatible = "amlogic,meson-gx-aoclkc",
286 .data = &gxbb_aoclkc_data,
287 },
288 { }
289};
290
291static struct platform_driver gxbb_aoclkc_driver = {
292 .probe = meson_aoclkc_probe,
293 .driver = {
294 .name = "gxbb-aoclkc",
295 .of_match_table = gxbb_aoclkc_match_table,
296 },
297};
298builtin_platform_driver(gxbb_aoclkc_driver);
299
