LXR linux/drivers/gpu/drm/amd/display/dc/dml/display_mode

   1/*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25#ifndef __DISPLAY_MODE_ENUMS_H__
  26#define __DISPLAY_MODE_ENUMS_H__
  27
  28enum output_encoder_class {
  29        dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
  30};
  31enum output_format_class {
  32        dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
  33};
  34enum source_format_class {
  35        dm_444_16 = 0,
  36        dm_444_32 = 1,
  37        dm_444_64 = 2,
  38        dm_420_8 = 3,
  39        dm_420_10 = 4,
  40        dm_420_12 = 5,
  41        dm_422_8 = 6,
  42        dm_422_10 = 7,
  43        dm_444_8 = 8,
  44        dm_mono_8 = dm_444_8,
  45        dm_mono_16 = dm_444_16,
  46        dm_rgbe = 9,
  47        dm_rgbe_alpha = 10,
  48};
  49enum output_bpc_class {
  50        dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
  51};
  52enum scan_direction_class {
  53        dm_horz = 0, dm_vert = 1
  54};
  55enum dm_swizzle_mode {
  56        dm_sw_linear = 0,
  57        dm_sw_256b_s = 1,
  58        dm_sw_256b_d = 2,
  59        dm_sw_SPARE_0 = 3,
  60        dm_sw_SPARE_1 = 4,
  61        dm_sw_4kb_s = 5,
  62        dm_sw_4kb_d = 6,
  63        dm_sw_SPARE_2 = 7,
  64        dm_sw_SPARE_3 = 8,
  65        dm_sw_64kb_s = 9,
  66        dm_sw_64kb_d = 10,
  67        dm_sw_SPARE_4 = 11,
  68        dm_sw_SPARE_5 = 12,
  69        dm_sw_var_s = 13,
  70        dm_sw_var_d = 14,
  71        dm_sw_SPARE_6 = 15,
  72        dm_sw_SPARE_7 = 16,
  73        dm_sw_64kb_s_t = 17,
  74        dm_sw_64kb_d_t = 18,
  75        dm_sw_SPARE_10 = 19,
  76        dm_sw_SPARE_11 = 20,
  77        dm_sw_4kb_s_x = 21,
  78        dm_sw_4kb_d_x = 22,
  79        dm_sw_SPARE_12 = 23,
  80        dm_sw_SPARE_13 = 24,
  81        dm_sw_64kb_s_x = 25,
  82        dm_sw_64kb_d_x = 26,
  83        dm_sw_SPARE_14 = 27,
  84        dm_sw_SPARE_15 = 28,
  85        dm_sw_var_s_x = 29,
  86        dm_sw_var_d_x = 30,
  87        dm_sw_64kb_r_x,
  88        dm_sw_gfx7_2d_thin_lvp,
  89        dm_sw_gfx7_2d_thin_gl,
  90};
  91enum lb_depth {
  92        dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
  93        dm_lb_19 = 5
  94};
  95enum voltage_state {
  96        dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
  97};
  98enum source_macro_tile_size {
  99        dm_4k_tile = 0, dm_64k_tile = 1, dm_256k_tile = 2
 100};
 101enum cursor_bpp {
 102        dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
 103};
 104enum clock_change_support {
 105        dm_dram_clock_change_uninitialized = 0,
 106        dm_dram_clock_change_vactive,
 107        dm_dram_clock_change_vblank,
 108        dm_dram_clock_change_unsupported
 109};
 110
 111enum output_standard {
 112        dm_std_uninitialized = 0, dm_std_cvtr2, dm_std_cvt
 113};
 114
 115enum mpc_combine_affinity {
 116        dm_mpc_always_when_possible,
 117        dm_mpc_reduce_voltage,
 118        dm_mpc_reduce_voltage_and_clocks,
 119        dm_mpc_never
 120};
 121
 122enum self_refresh_affinity {
 123        dm_try_to_allow_self_refresh_and_mclk_switch,
 124        dm_allow_self_refresh_and_mclk_switch,
 125        dm_allow_self_refresh,
 126        dm_neither_self_refresh_nor_mclk_switch
 127};
 128
 129enum dm_validation_status {
 130        DML_VALIDATION_OK,
 131        DML_FAIL_SCALE_RATIO_TAP,
 132        DML_FAIL_SOURCE_PIXEL_FORMAT,
 133        DML_FAIL_VIEWPORT_SIZE,
 134        DML_FAIL_TOTAL_V_ACTIVE_BW,
 135        DML_FAIL_DIO_SUPPORT,
 136        DML_FAIL_NOT_ENOUGH_DSC,
 137        DML_FAIL_DSC_CLK_REQUIRED,
 138#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 139        DML_FAIL_DSC_VALIDATION_FAILURE,
 140#endif
 141        DML_FAIL_URGENT_LATENCY,
 142        DML_FAIL_REORDERING_BUFFER,
 143        DML_FAIL_DISPCLK_DPPCLK,
 144        DML_FAIL_TOTAL_AVAILABLE_PIPES,
 145        DML_FAIL_NUM_OTG,
 146        DML_FAIL_WRITEBACK_MODE,
 147        DML_FAIL_WRITEBACK_LATENCY,
 148        DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
 149        DML_FAIL_CURSOR_SUPPORT,
 150        DML_FAIL_PITCH_SUPPORT,
 151        DML_FAIL_PTE_BUFFER_SIZE,
 152        DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
 153        DML_FAIL_DSC_INPUT_BPC,
 154        DML_FAIL_PREFETCH_SUPPORT,
 155        DML_FAIL_V_RATIO_PREFETCH,
 156};
 157
 158enum writeback_config {
 159        dm_normal,
 160        dm_whole_buffer_for_single_stream_no_interleave,
 161        dm_whole_buffer_for_single_stream_interleave,
 162};
 163
 164enum odm_combine_mode {
 165        dm_odm_combine_mode_disabled,
 166        dm_odm_combine_mode_2to1,
 167        dm_odm_combine_mode_4to1,
 168};
 169
 170#endif
 171