1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifdef CONFIG_DRM_AMD_DC_DCN2_0
27
28#ifndef __DML2_DISPLAY_MODE_VBA_H__
29#define __DML2_DISPLAY_MODE_VBA_H__
30
31#include "dml_common_defs.h"
32
33struct display_mode_lib;
34
35void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
36
37#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
38
39dml_get_attr_decl(clk_dcf_deepsleep);
40dml_get_attr_decl(wm_urgent);
41dml_get_attr_decl(wm_memory_trip);
42dml_get_attr_decl(wm_writeback_urgent);
43dml_get_attr_decl(wm_stutter_exit);
44dml_get_attr_decl(wm_stutter_enter_exit);
45dml_get_attr_decl(wm_dram_clock_change);
46dml_get_attr_decl(wm_writeback_dram_clock_change);
47dml_get_attr_decl(wm_xfc_underflow);
48dml_get_attr_decl(stutter_efficiency_no_vblank);
49dml_get_attr_decl(stutter_efficiency);
50dml_get_attr_decl(urgent_latency);
51dml_get_attr_decl(urgent_extra_latency);
52dml_get_attr_decl(nonurgent_latency);
53dml_get_attr_decl(dram_clock_change_latency);
54dml_get_attr_decl(dispclk_calculated);
55dml_get_attr_decl(total_data_read_bw);
56dml_get_attr_decl(return_bw);
57dml_get_attr_decl(tcalc);
58dml_get_attr_decl(fraction_of_urgent_bandwidth);
59dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
60
61#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
62
63dml_get_pipe_attr_decl(dsc_delay);
64dml_get_pipe_attr_decl(dppclk_calculated);
65dml_get_pipe_attr_decl(dscclk_calculated);
66dml_get_pipe_attr_decl(min_ttu_vblank);
67dml_get_pipe_attr_decl(vratio_prefetch_l);
68dml_get_pipe_attr_decl(vratio_prefetch_c);
69dml_get_pipe_attr_decl(dst_x_after_scaler);
70dml_get_pipe_attr_decl(dst_y_after_scaler);
71dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
72dml_get_pipe_attr_decl(dst_y_per_row_vblank);
73dml_get_pipe_attr_decl(dst_y_prefetch);
74dml_get_pipe_attr_decl(dst_y_per_vm_flip);
75dml_get_pipe_attr_decl(dst_y_per_row_flip);
76dml_get_pipe_attr_decl(xfc_transfer_delay);
77dml_get_pipe_attr_decl(xfc_precharge_delay);
78dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
79dml_get_pipe_attr_decl(xfc_prefetch_margin);
80dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
81dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
82dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
83dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
84
85unsigned int get_vstartup_calculated(
86 struct display_mode_lib *mode_lib,
87 const display_e2e_pipe_params_st *pipes,
88 unsigned int num_pipes,
89 unsigned int which_pipe);
90
91double get_total_immediate_flip_bytes(
92 struct display_mode_lib *mode_lib,
93 const display_e2e_pipe_params_st *pipes,
94 unsigned int num_pipes);
95double get_total_immediate_flip_bw(
96 struct display_mode_lib *mode_lib,
97 const display_e2e_pipe_params_st *pipes,
98 unsigned int num_pipes);
99double get_total_prefetch_bw(
100 struct display_mode_lib *mode_lib,
101 const display_e2e_pipe_params_st *pipes,
102 unsigned int num_pipes);
103unsigned int dml_get_voltage_level(
104 struct display_mode_lib *mode_lib,
105 const display_e2e_pipe_params_st *pipes,
106 unsigned int num_pipes);
107
108void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
109
110bool Calculate256BBlockSizes(
111 enum source_format_class SourcePixelFormat,
112 enum dm_swizzle_mode SurfaceTiling,
113 unsigned int BytePerPixelY,
114 unsigned int BytePerPixelC,
115 unsigned int *BlockHeight256BytesY,
116 unsigned int *BlockHeight256BytesC,
117 unsigned int *BlockWidth256BytesY,
118 unsigned int *BlockWidth256BytesC);
119
120struct vba_vars_st {
121 ip_params_st ip;
122 soc_bounding_box_st soc;
123
124 int maxMpcComb;
125 bool UseMaximumVStartup;
126
127 double WritebackDISPCLK;
128 double DPPCLKUsingSingleDPPLuma;
129 double DPPCLKUsingSingleDPPChroma;
130 double DISPCLKWithRamping;
131 double DISPCLKWithoutRamping;
132 double GlobalDPPCLK;
133 double DISPCLKWithRampingRoundedToDFSGranularity;
134 double DISPCLKWithoutRampingRoundedToDFSGranularity;
135 double MaxDispclkRoundedToDFSGranularity;
136 bool DCCEnabledAnyPlane;
137 double ReturnBandwidthToDCN;
138 unsigned int TotalActiveDPP;
139 unsigned int TotalDCCActiveDPP;
140 double UrgentRoundTripAndOutOfOrderLatency;
141 double StutterPeriod;
142 double FrameTimeForMinFullDETBufferingTime;
143 double AverageReadBandwidth;
144 double TotalRowReadBandwidth;
145 double PartOfBurstThatFitsInROB;
146 double StutterBurstTime;
147 unsigned int NextPrefetchMode;
148 double NextMaxVStartup;
149 double VBlankTime;
150 double SmallestVBlank;
151 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
152 double EffectiveDETPlusLBLinesLuma;
153 double EffectiveDETPlusLBLinesChroma;
154 double UrgentLatencySupportUsLuma;
155 double UrgentLatencySupportUsChroma;
156 unsigned int DSCFormatFactor;
157
158 bool PrefetchModeSupported;
159 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank;
160 double XFCRemoteSurfaceFlipDelay;
161 double TInitXFill;
162 double TslvChk;
163 double SrcActiveDrainRate;
164 bool ImmediateFlipSupported;
165 enum mpc_combine_affinity WhenToDoMPCCombine;
166
167 bool PrefetchERROR;
168
169 unsigned int VStartupLines;
170 unsigned int ActiveDPPs;
171 unsigned int LBLatencyHidingSourceLinesY;
172 unsigned int LBLatencyHidingSourceLinesC;
173 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
174 double MinActiveDRAMClockChangeMargin;
175 double InitFillLevel;
176 double FinalFillMargin;
177 double FinalFillLevel;
178 double RemainingFillLevel;
179 double TFinalxFill;
180
181
182
183
184 double SRExitTime;
185 double SREnterPlusExitTime;
186 double UrgentLatencyPixelDataOnly;
187 double UrgentLatencyPixelMixedWithVMData;
188 double UrgentLatencyVMDataOnly;
189 double UrgentLatency;
190 double WritebackLatency;
191 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly;
192 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData;
193 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
194 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation;
195 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation;
196 double NumberOfChannels;
197 double DRAMChannelWidth;
198 double FabricDatapathToDCNDataReturn;
199 double ReturnBusWidth;
200 double Downspreading;
201 double DISPCLKDPPCLKDSCCLKDownSpreading;
202 double DISPCLKDPPCLKVCOSpeed;
203 double RoundTripPingLatencyCycles;
204 double UrgentOutOfOrderReturnPerChannel;
205 double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
206 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
207 double UrgentOutOfOrderReturnPerChannelVMDataOnly;
208 unsigned int VMMPageSize;
209 double DRAMClockChangeLatency;
210 double XFCBusTransportTime;
211 bool UseUrgentBurstBandwidth;
212 double XFCXBUFLatencyTolerance;
213
214
215
216
217 unsigned int ROBBufferSizeInKByte;
218 double DETBufferSizeInKByte;
219 double DETBufferSizeInTime;
220 unsigned int DPPOutputBufferPixels;
221 unsigned int OPPOutputBufferLines;
222 unsigned int PixelChunkSizeInKByte;
223 double ReturnBW;
224 bool GPUVMEnable;
225 bool HostVMEnable;
226 unsigned int GPUVMMaxPageTableLevels;
227 unsigned int HostVMMaxPageTableLevels;
228 unsigned int HostVMCachedPageTableLevels;
229 unsigned int OverrideGPUVMPageTableLevels;
230 unsigned int OverrideHostVMPageTableLevels;
231 unsigned int MetaChunkSize;
232 double MinPixelChunkSizeBytes;
233 double MinMetaChunkSizeBytes;
234 unsigned int WritebackChunkSize;
235 bool ODMCapability;
236 unsigned int NumberOfDSC;
237 unsigned int LineBufferSize;
238 unsigned int MaxLineBufferLines;
239 unsigned int WritebackInterfaceLumaBufferSize;
240 unsigned int WritebackInterfaceChromaBufferSize;
241 unsigned int WritebackChromaLineBufferWidth;
242 enum writeback_config WritebackConfiguration;
243 double MaxDCHUBToPSCLThroughput;
244 double MaxPSCLToLBThroughput;
245 unsigned int PTEBufferSizeInRequestsLuma;
246 unsigned int PTEBufferSizeInRequestsChroma;
247 double DISPCLKRampingMargin;
248 unsigned int MaxInterDCNTileRepeaters;
249 bool XFCSupported;
250 double XFCSlvChunkSize;
251 double XFCFillBWOverhead;
252 double XFCFillConstant;
253 double XFCTSlvVupdateOffset;
254 double XFCTSlvVupdateWidth;
255 double XFCTSlvVreadyOffset;
256 double DPPCLKDelaySubtotal;
257 double DPPCLKDelaySCL;
258 double DPPCLKDelaySCLLBOnly;
259 double DPPCLKDelayCNVCFormater;
260 double DPPCLKDelayCNVCCursor;
261 double DISPCLKDelaySubtotal;
262 bool ProgressiveToInterlaceUnitInOPP;
263
264 int VoltageLevel;
265 double FabricClock;
266 double DRAMSpeed;
267 double DISPCLK;
268 double SOCCLK;
269 double DCFCLK;
270
271 unsigned int NumberOfActivePlanes;
272 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
273 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
274 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
275 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
276 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
277 unsigned int PitchY[DC__NUM_DPP__MAX];
278 unsigned int PitchC[DC__NUM_DPP__MAX];
279 double HRatio[DC__NUM_DPP__MAX];
280 double VRatio[DC__NUM_DPP__MAX];
281 unsigned int htaps[DC__NUM_DPP__MAX];
282 unsigned int vtaps[DC__NUM_DPP__MAX];
283 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
284 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
285 unsigned int HTotal[DC__NUM_DPP__MAX];
286 unsigned int VTotal[DC__NUM_DPP__MAX];
287 unsigned int VTotal_Max[DC__NUM_DPP__MAX];
288 unsigned int VTotal_Min[DC__NUM_DPP__MAX];
289 int DPPPerPlane[DC__NUM_DPP__MAX];
290 double PixelClock[DC__NUM_DPP__MAX];
291 double PixelClockBackEnd[DC__NUM_DPP__MAX];
292 bool DCCEnable[DC__NUM_DPP__MAX];
293 bool FECEnable[DC__NUM_DPP__MAX];
294 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
295 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
296 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
297 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
298 bool WritebackEnable[DC__NUM_DPP__MAX];
299 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
300 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
301 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
302 double WritebackSourceHeight[DC__NUM_DPP__MAX];
303 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
304 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
305 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
306 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
307 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
308 double WritebackHRatio[DC__NUM_DPP__MAX];
309 double WritebackVRatio[DC__NUM_DPP__MAX];
310 unsigned int HActive[DC__NUM_DPP__MAX];
311 unsigned int VActive[DC__NUM_DPP__MAX];
312 bool Interlace[DC__NUM_DPP__MAX];
313 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
314 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
315 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
316 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
317 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
318 double DCCRate[DC__NUM_DPP__MAX];
319 double AverageDCCCompressionRate;
320 bool ODMCombineEnabled[DC__NUM_DPP__MAX];
321 enum odm_combine_mode ODMCombineTypeEnabled[DC__NUM_DPP__MAX];
322 double OutputBpp[DC__NUM_DPP__MAX];
323 bool DSCEnabled[DC__NUM_DPP__MAX];
324 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
325 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
326 enum output_encoder_class Output[DC__NUM_DPP__MAX];
327 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
328 bool SynchronizedVBlank;
329 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
330 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
331 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
332 bool XFCEnabled[DC__NUM_DPP__MAX];
333 bool ScalerEnabled[DC__NUM_DPP__MAX];
334
335
336 bool ImmediateFlipSupport;
337 double DETBufferSizeY[DC__NUM_DPP__MAX];
338 double DETBufferSizeC[DC__NUM_DPP__MAX];
339 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
340 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
341 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
342 double LastPixelOfLineExtraWatermark;
343 double TotalDataReadBandwidth;
344 unsigned int TotalActiveWriteback;
345 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
346 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
347 double BandwidthAvailableForImmediateFlip;
348 unsigned int PrefetchMode[DC__VOLTAGE_STATES + 1][2];
349 unsigned int MinPrefetchMode;
350 unsigned int MaxPrefetchMode;
351 bool AnyLinesForVMOrRowTooLarge;
352 double MaxVStartup;
353 bool IgnoreViewportPositioning;
354 bool ErrorResult[DC__NUM_DPP__MAX];
355
356
357
358 double DCFCLKDeepSleep;
359 double UrgentWatermark;
360 double UrgentExtraLatency;
361 double WritebackUrgentWatermark;
362 double StutterExitWatermark;
363 double StutterEnterPlusExitWatermark;
364 double DRAMClockChangeWatermark;
365 double WritebackDRAMClockChangeWatermark;
366 double StutterEfficiency;
367 double StutterEfficiencyNotIncludingVBlank;
368 double NonUrgentLatencyTolerance;
369 double MinActiveDRAMClockChangeLatencySupported;
370
371
372
373
374 double DISPCLK_calculated;
375 double DPPCLK_calculated[DC__NUM_DPP__MAX];
376
377 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
378 double VUpdateWidthPix[DC__NUM_DPP__MAX];
379 double VReadyOffsetPix[DC__NUM_DPP__MAX];
380
381 unsigned int TotImmediateFlipBytes;
382 double TCalc;
383
384 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
385 unsigned int cache_num_pipes;
386 unsigned int pipe_plane[DC__NUM_DPP__MAX];
387
388
389
390 bool EmbeddedPanel[DC__NUM_DPP__MAX];
391 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
392 double MaxHSCLRatio;
393 double MaxVSCLRatio;
394 unsigned int MaxNumWriteback;
395 bool WritebackLumaAndChromaScalingSupported;
396 bool Cursor64BppSupport;
397 double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
398 double FabricClockPerState[DC__VOLTAGE_STATES + 1];
399 double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
400 double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
401 double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
402 double MaxDppclk[DC__VOLTAGE_STATES + 1];
403 double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
404 double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
405 double MaxDispclk[DC__VOLTAGE_STATES + 1];
406 int VoltageOverrideLevel;
407
408
409 bool ScaleRatioAndTapsSupport;
410 bool SourceFormatPixelAndScanSupport;
411 double TotalBandwidthConsumedGBytePerSecond;
412 bool DCCEnabledInAnyPlane;
413 bool WritebackLatencySupport;
414 bool WritebackModeSupport;
415 bool Writeback10bpc420Supported;
416 bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
417 unsigned int TotalNumberOfActiveWriteback;
418 double CriticalPoint;
419 double ReturnBWToDCNPerState;
420 bool IsErrorResult[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
421 bool prefetch_vm_bw_valid;
422 bool prefetch_row_bw_valid;
423 bool NumberOfOTGSupport;
424 bool NonsupportedDSCInputBPC;
425 bool WritebackScaleRatioAndTapsSupport;
426 bool CursorSupport;
427 bool PitchSupport;
428 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES + 1];
429
430 double WritebackLineBufferLumaBufferSize;
431 double WritebackLineBufferChromaBufferSize;
432 double WritebackMinHSCLRatio;
433 double WritebackMinVSCLRatio;
434 double WritebackMaxHSCLRatio;
435 double WritebackMaxVSCLRatio;
436 double WritebackMaxHSCLTaps;
437 double WritebackMaxVSCLTaps;
438 unsigned int MaxNumDPP;
439 unsigned int MaxNumOTG;
440 double CursorBufferSize;
441 double CursorChunkSize;
442 unsigned int Mode;
443 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
444 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX];
445 double ImmediateFlipBW[DC__NUM_DPP__MAX];
446 double MaxMaxVStartup;
447
448 double WritebackLumaVExtra;
449 double WritebackChromaVExtra;
450 double WritebackRequiredDISPCLK;
451 double MaximumSwathWidthSupport;
452 double MaximumSwathWidthInDETBuffer;
453 double MaximumSwathWidthInLineBuffer;
454 double MaxDispclkRoundedDownToDFSGranularity;
455 double MaxDppclkRoundedDownToDFSGranularity;
456 double PlaneRequiredDISPCLKWithoutODMCombine;
457 double PlaneRequiredDISPCLKWithODMCombine;
458 double PlaneRequiredDISPCLK;
459 double TotalNumberOfActiveOTG;
460 double FECOverhead;
461 double EffectiveFECOverhead;
462 double Outbpp;
463 unsigned int OutbppDSC;
464 double TotalDSCUnitsRequired;
465 double bpp;
466 unsigned int slices;
467 double SwathWidthGranularityY;
468 double RoundedUpMaxSwathSizeBytesY;
469 double SwathWidthGranularityC;
470 double RoundedUpMaxSwathSizeBytesC;
471 double EffectiveDETLBLinesLuma;
472 double EffectiveDETLBLinesChroma;
473 double ProjectedDCFCLKDeepSleep;
474 double PDEAndMetaPTEBytesPerFrameY;
475 double PDEAndMetaPTEBytesPerFrameC;
476 unsigned int MetaRowBytesY;
477 unsigned int MetaRowBytesC;
478 unsigned int DPTEBytesPerRowC;
479 unsigned int DPTEBytesPerRowY;
480 double ExtraLatency;
481 double TimeCalc;
482 double TWait;
483 double MaximumReadBandwidthWithPrefetch;
484 double MaximumReadBandwidthWithoutPrefetch;
485 double total_dcn_read_bw_with_flip;
486 double total_dcn_read_bw_with_flip_no_urgent_burst;
487 double FractionOfUrgentBandwidth;
488 double FractionOfUrgentBandwidthImmediateFlip;
489
490
491 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES + 1];
492 unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
493 int NoOfDPPThisState[DC__NUM_DPP__MAX];
494 bool ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
495 enum odm_combine_mode ODMCombineTypeEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
496 unsigned int SwathWidthYThisState[DC__NUM_DPP__MAX];
497 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
498 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
499 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
500 double VRatioPreY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
501 double VRatioPreC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
502 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
503 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
504 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
505 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
506 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
507 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
508 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES + 1];
509 bool PrefetchSupported[DC__VOLTAGE_STATES + 1][2];
510 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
511 double RequiredDISPCLK[DC__VOLTAGE_STATES + 1][2];
512 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1][2];
513 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1][2];
514 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1][2];
515 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1][2];
516 bool ModeSupport[DC__VOLTAGE_STATES + 1][2];
517 double ReturnBWPerState[DC__VOLTAGE_STATES + 1];
518 bool DIOSupport[DC__VOLTAGE_STATES + 1];
519 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
520 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
521 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
522 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
523 bool ROBSupport[DC__VOLTAGE_STATES + 1];
524 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
525 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES + 1];
526 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES + 1];
527 double PrefetchBW[DC__NUM_DPP__MAX];
528 double PDEAndMetaPTEBytesPerFrame[DC__NUM_DPP__MAX];
529 double MetaRowBytes[DC__NUM_DPP__MAX];
530 double DPTEBytesPerRow[DC__NUM_DPP__MAX];
531 double PrefetchLinesY[DC__NUM_DPP__MAX];
532 double PrefetchLinesC[DC__NUM_DPP__MAX];
533 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
534 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
535 double PrefillY[DC__NUM_DPP__MAX];
536 double PrefillC[DC__NUM_DPP__MAX];
537 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
538 double LinesForMetaPTE[DC__NUM_DPP__MAX];
539 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
540 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
541 unsigned int SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
542 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
543 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
544 bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
545 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
546 double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
547 double OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
548 double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
549 bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1];
550 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
551 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
552 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
553 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
554 double MaxSwathHeightY[DC__NUM_DPP__MAX];
555 double MaxSwathHeightC[DC__NUM_DPP__MAX];
556 double MinSwathHeightY[DC__NUM_DPP__MAX];
557 double MinSwathHeightC[DC__NUM_DPP__MAX];
558 double ReadBandwidthLuma[DC__NUM_DPP__MAX];
559 double ReadBandwidthChroma[DC__NUM_DPP__MAX];
560 double ReadBandwidth[DC__NUM_DPP__MAX];
561 double WriteBandwidth[DC__NUM_DPP__MAX];
562 double PSCL_FACTOR[DC__NUM_DPP__MAX];
563 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
564 double MaximumVStartup[DC__NUM_DPP__MAX];
565 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
566 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
567 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
568 double AlignedYPitch[DC__NUM_DPP__MAX];
569 double AlignedCPitch[DC__NUM_DPP__MAX];
570 double MaximumSwathWidth[DC__NUM_DPP__MAX];
571 double cursor_bw[DC__NUM_DPP__MAX];
572 double cursor_bw_pre[DC__NUM_DPP__MAX];
573 double Tno_bw[DC__NUM_DPP__MAX];
574 double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
575 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
576 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
577 double final_flip_bw[DC__NUM_DPP__MAX];
578 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1][2];
579 double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
580 unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
581 long dpte_group_bytes[DC__NUM_DPP__MAX];
582 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
583 unsigned int meta_req_height[DC__NUM_DPP__MAX];
584 unsigned int meta_req_width[DC__NUM_DPP__MAX];
585 unsigned int meta_row_height[DC__NUM_DPP__MAX];
586 unsigned int meta_row_width[DC__NUM_DPP__MAX];
587 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
588 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
589 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
590 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
591 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
592 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
593 double meta_row_bw[DC__NUM_DPP__MAX];
594 double dpte_row_bw[DC__NUM_DPP__MAX];
595 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];
596 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];
597 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
598 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
599 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2];
600 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
601 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
602 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
603 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
604 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
605 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
606
607 bool MPCCombine[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
608 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
609 double MaximumSwathWidthInLineBufferLuma;
610 double MaximumSwathWidthInLineBufferChroma;
611 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
612 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
613 bool odm_combine_dummy[DC__NUM_DPP__MAX];
614 enum odm_combine_mode odm_combine_mode_dummy[DC__NUM_DPP__MAX];
615 double dummy1[DC__NUM_DPP__MAX];
616 double dummy2[DC__NUM_DPP__MAX];
617 double dummy3[DC__NUM_DPP__MAX];
618 double dummy4[DC__NUM_DPP__MAX];
619 double dummy5;
620 double dummy6;
621 double dummy7[DC__NUM_DPP__MAX];
622 double dummy8[DC__NUM_DPP__MAX];
623 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX];
624 unsigned int dummyinteger2ms[DC__NUM_DPP__MAX];
625 unsigned int dummyinteger3[DC__NUM_DPP__MAX];
626 unsigned int dummyinteger4;
627 unsigned int dummyinteger5;
628 unsigned int dummyinteger6;
629 unsigned int dummyinteger7;
630 unsigned int dummyinteger8;
631 unsigned int dummyinteger9;
632 unsigned int dummyinteger10;
633 unsigned int dummyinteger11;
634 unsigned int dummyinteger12;
635 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX];
636 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX];
637 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX];
638 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX];
639 long dummylongarr1[DC__NUM_DPP__MAX];
640 bool dummysinglestring;
641 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
642 double PlaneRequiredDISPCLKWithODMCombine2To1;
643 double PlaneRequiredDISPCLKWithODMCombine4To1;
644 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES + 1][2];
645 bool LinkDSCEnable;
646 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
647 bool ODMCombineEnableThisState[DC__NUM_DPP__MAX];
648 enum odm_combine_mode ODMCombineEnableTypeThisState[DC__NUM_DPP__MAX];
649 unsigned int SwathWidthCThisState[DC__NUM_DPP__MAX];
650 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
651 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
652 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
653
654 unsigned int NotEnoughUrgentLatencyHiding;
655 unsigned int NotEnoughUrgentLatencyHidingPre;
656 long PTEBufferSizeInRequestsForLuma;
657 long PTEBufferSizeInRequestsForChroma;
658
659
660 long dpte_group_bytes_chroma;
661 unsigned int vm_group_bytes_chroma;
662 double dst_x_after_scaler;
663 double dst_y_after_scaler;
664 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
665
666
667 double PrefetchBandwidth[DC__NUM_DPP__MAX];
668 double VInitPreFillY[DC__NUM_DPP__MAX];
669 double VInitPreFillC[DC__NUM_DPP__MAX];
670 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
671 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
672 unsigned int VStartup[DC__NUM_DPP__MAX];
673 double DSTYAfterScaler[DC__NUM_DPP__MAX];
674 double DSTXAfterScaler[DC__NUM_DPP__MAX];
675 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
676 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
677 double VRatioPrefetchY[DC__NUM_DPP__MAX];
678 double VRatioPrefetchC[DC__NUM_DPP__MAX];
679 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
680 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
681 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
682 double MinTTUVBlank[DC__NUM_DPP__MAX];
683 double BytePerPixelDETY[DC__NUM_DPP__MAX];
684 double BytePerPixelDETC[DC__NUM_DPP__MAX];
685 unsigned int SwathWidthY[DC__NUM_DPP__MAX];
686 unsigned int SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
687 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
688 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
689 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
690 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
691 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
692 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
693 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
694 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
695 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
696 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
697 double MetaRowByte[DC__NUM_DPP__MAX];
698 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
699 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
700 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
701 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
702 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
703 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
704 double DSCCLK_calculated[DC__NUM_DPP__MAX];
705 unsigned int DSCDelay[DC__NUM_DPP__MAX];
706 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
707 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
708 double DPPCLK[DC__NUM_DPP__MAX];
709 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
710 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
711 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
712 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
713 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
714 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
715 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
716 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
717 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
718 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
719 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
720 double XFCTransferDelay[DC__NUM_DPP__MAX];
721 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
722 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
723 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
724 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
725 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
726 double FullDETBufferingTimeY[DC__NUM_DPP__MAX];
727 double FullDETBufferingTimeC[DC__NUM_DPP__MAX];
728 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
729 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
730 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
731 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
732 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
733 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
734 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
735 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
736 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
737 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
738 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
739 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
740 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
741 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
742 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
743 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
744 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
745 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
746 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
747 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
748 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
749 double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
750 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
751 double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
752 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
753 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
754 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
755 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
756 double LinesToFinishSwathTransferStutterCriticalPlane;
757 unsigned int BytePerPixelYCriticalPlane;
758 double SwathWidthYCriticalPlane;
759 double LinesInDETY[DC__NUM_DPP__MAX];
760 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
761
762 unsigned int SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
763 unsigned int SwathWidthC[DC__NUM_DPP__MAX];
764 unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
765 unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
766 long dummyinteger1;
767 long dummyinteger2;
768 double FinalDRAMClockChangeLatency;
769 double Tdmdl_vm[DC__NUM_DPP__MAX];
770 double Tdmdl[DC__NUM_DPP__MAX];
771 unsigned int ThisVStartup;
772 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
773 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
774 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
775 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
776 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
777 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
778 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
779 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
780 double VStartupMargin;
781
782
783 unsigned int MaximumMaxVStartupLines;
784 double FabricAndDRAMBandwidth;
785 double LinesInDETLuma;
786 double LinesInDETChroma;
787 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
788 unsigned int LinesInDETC[DC__NUM_DPP__MAX];
789 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
790 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
791 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
792 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
793 bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1][2];
794 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
795 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
796 double qual_row_bw[DC__NUM_DPP__MAX];
797 double prefetch_row_bw[DC__NUM_DPP__MAX];
798 double prefetch_vm_bw[DC__NUM_DPP__MAX];
799
800 double PTEGroupSize;
801 unsigned int PDEProcessingBufIn64KBReqs;
802
803 double MaxTotalVActiveRDBandwidth;
804 bool DoUrgentLatencyAdjustment;
805 double UrgentLatencyAdjustmentFabricClockComponent;
806 double UrgentLatencyAdjustmentFabricClockReference;
807 double MinUrgentLatencySupportUs;
808 double MinFullDETBufferingTime;
809 double AverageReadBandwidthGBytePerSecond;
810 bool FirstMainPlane;
811
812 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
813 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
814 double HRatioChroma[DC__NUM_DPP__MAX];
815 double VRatioChroma[DC__NUM_DPP__MAX];
816 long WritebackSourceWidth[DC__NUM_DPP__MAX];
817
818 bool ModeIsSupported;
819 bool ODMCombine4To1Supported;
820
821 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
822 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
823 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
824 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
825 unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
826 unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
827 bool DSCEnable[DC__NUM_DPP__MAX];
828
829 double DRAMClockChangeLatencyOverride;
830
831 double GPUVMMinPageSize;
832 double HostVMMinPageSize;
833
834 bool MPCCombineEnable[DC__NUM_DPP__MAX];
835 unsigned int HostVMMaxNonCachedPageTableLevels;
836 bool DynamicMetadataVMEnabled;
837 double WritebackInterfaceBufferSize;
838 double WritebackLineBufferSize;
839
840 double DCCRateLuma[DC__NUM_DPP__MAX];
841 double DCCRateChroma[DC__NUM_DPP__MAX];
842
843 double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
844 int MinVoltageLevel;
845 int MaxVoltageLevel;
846
847 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
848 bool NumberOfHDMIFRLSupport;
849 unsigned int MaxNumHDMIFRLOutputs;
850 int AudioSampleRate[DC__NUM_DPP__MAX];
851 int AudioSampleLayout[DC__NUM_DPP__MAX];
852};
853
854bool CalculateMinAndMaxPrefetchMode(
855 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
856 unsigned int *MinPrefetchMode,
857 unsigned int *MaxPrefetchMode);
858
859double CalculateWriteBackDISPCLK(
860 enum source_format_class WritebackPixelFormat,
861 double PixelClock,
862 double WritebackHRatio,
863 double WritebackVRatio,
864 unsigned int WritebackLumaHTaps,
865 unsigned int WritebackLumaVTaps,
866 unsigned int WritebackChromaHTaps,
867 unsigned int WritebackChromaVTaps,
868 double WritebackDestinationWidth,
869 unsigned int HTotal,
870 unsigned int WritebackChromaLineBufferWidth);
871
872#endif
873#endif
874
