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28#include <drm/drm_dp_helper.h>
29#include <drm/i915_drm.h>
30
31#include "display/intel_display.h"
32#include "display/intel_gmbus.h"
33
34#include "i915_drv.h"
35
36#define _INTEL_BIOS_PRIVATE
37#include "intel_vbt_defs.h"
38
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59
60
61#define SLAVE_ADDR1 0x70
62#define SLAVE_ADDR2 0x72
63
64
65static u32 _get_blocksize(const u8 *block_base)
66{
67
68 if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3)
69 return *((const u32 *)(block_base + 4));
70 else
71 return *((const u16 *)(block_base + 1));
72}
73
74
75static u32 get_blocksize(const void *block_data)
76{
77 return _get_blocksize(block_data - 3);
78}
79
80static const void *
81find_section(const void *_bdb, enum bdb_block_id section_id)
82{
83 const struct bdb_header *bdb = _bdb;
84 const u8 *base = _bdb;
85 int index = 0;
86 u32 total, current_size;
87 enum bdb_block_id current_id;
88
89
90 index += bdb->header_size;
91 total = bdb->bdb_size;
92
93
94 while (index + 3 < total) {
95 current_id = *(base + index);
96 current_size = _get_blocksize(base + index);
97 index += 3;
98
99 if (index + current_size > total)
100 return NULL;
101
102 if (current_id == section_id)
103 return base + index;
104
105 index += current_size;
106 }
107
108 return NULL;
109}
110
111static void
112fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode,
113 const struct lvds_dvo_timing *dvo_timing)
114{
115 panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) |
116 dvo_timing->hactive_lo;
117 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
118 ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo);
119 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
120 ((dvo_timing->hsync_pulse_width_hi << 8) |
121 dvo_timing->hsync_pulse_width_lo);
122 panel_fixed_mode->htotal = panel_fixed_mode->hdisplay +
123 ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo);
124
125 panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) |
126 dvo_timing->vactive_lo;
127 panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay +
128 ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo);
129 panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start +
130 ((dvo_timing->vsync_pulse_width_hi << 4) |
131 dvo_timing->vsync_pulse_width_lo);
132 panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay +
133 ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo);
134 panel_fixed_mode->clock = dvo_timing->clock * 10;
135 panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED;
136
137 if (dvo_timing->hsync_positive)
138 panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC;
139 else
140 panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC;
141
142 if (dvo_timing->vsync_positive)
143 panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC;
144 else
145 panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC;
146
147 panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) |
148 dvo_timing->himage_lo;
149 panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) |
150 dvo_timing->vimage_lo;
151
152
153 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal)
154 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1;
155 if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal)
156 panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1;
157
158 drm_mode_set_name(panel_fixed_mode);
159}
160
161static const struct lvds_dvo_timing *
162get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data,
163 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs,
164 int index)
165{
166
167
168
169
170
171
172 int lfp_data_size =
173 lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset -
174 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset;
175 int dvo_timing_offset =
176 lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset -
177 lvds_lfp_data_ptrs->ptr[0].fp_timing_offset;
178 char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index;
179
180 return (struct lvds_dvo_timing *)(entry + dvo_timing_offset);
181}
182
183
184
185
186static const struct lvds_fp_timing *
187get_lvds_fp_timing(const struct bdb_header *bdb,
188 const struct bdb_lvds_lfp_data *data,
189 const struct bdb_lvds_lfp_data_ptrs *ptrs,
190 int index)
191{
192 size_t data_ofs = (const u8 *)data - (const u8 *)bdb;
193 u16 data_size = ((const u16 *)data)[-1];
194 size_t ofs;
195
196 if (index >= ARRAY_SIZE(ptrs->ptr))
197 return NULL;
198 ofs = ptrs->ptr[index].fp_timing_offset;
199 if (ofs < data_ofs ||
200 ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size)
201 return NULL;
202 return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);
203}
204
205
206static void
207parse_lfp_panel_data(struct drm_i915_private *dev_priv,
208 const struct bdb_header *bdb)
209{
210 const struct bdb_lvds_options *lvds_options;
211 const struct bdb_lvds_lfp_data *lvds_lfp_data;
212 const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs;
213 const struct lvds_dvo_timing *panel_dvo_timing;
214 const struct lvds_fp_timing *fp_timing;
215 struct drm_display_mode *panel_fixed_mode;
216 int panel_type;
217 int drrs_mode;
218 int ret;
219
220 lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
221 if (!lvds_options)
222 return;
223
224 dev_priv->vbt.lvds_dither = lvds_options->pixel_dither;
225
226 ret = intel_opregion_get_panel_type(dev_priv);
227 if (ret >= 0) {
228 WARN_ON(ret > 0xf);
229 panel_type = ret;
230 DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type);
231 } else {
232 if (lvds_options->panel_type > 0xf) {
233 DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n",
234 lvds_options->panel_type);
235 return;
236 }
237 panel_type = lvds_options->panel_type;
238 DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type);
239 }
240
241 dev_priv->vbt.panel_type = panel_type;
242
243 drrs_mode = (lvds_options->dps_panel_type_bits
244 >> (panel_type * 2)) & MODE_MASK;
245
246
247
248
249
250 switch (drrs_mode) {
251 case 0:
252 dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT;
253 DRM_DEBUG_KMS("DRRS supported mode is static\n");
254 break;
255 case 2:
256 dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT;
257 DRM_DEBUG_KMS("DRRS supported mode is seamless\n");
258 break;
259 default:
260 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
261 DRM_DEBUG_KMS("DRRS not supported (VBT input)\n");
262 break;
263 }
264
265 lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA);
266 if (!lvds_lfp_data)
267 return;
268
269 lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS);
270 if (!lvds_lfp_data_ptrs)
271 return;
272
273 panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data,
274 lvds_lfp_data_ptrs,
275 panel_type);
276
277 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
278 if (!panel_fixed_mode)
279 return;
280
281 fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing);
282
283 dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode;
284
285 DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n");
286 drm_mode_debug_printmodeline(panel_fixed_mode);
287
288 fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data,
289 lvds_lfp_data_ptrs,
290 panel_type);
291 if (fp_timing) {
292
293 if (fp_timing->x_res == panel_fixed_mode->hdisplay &&
294 fp_timing->y_res == panel_fixed_mode->vdisplay) {
295 dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val;
296 DRM_DEBUG_KMS("VBT initial LVDS value %x\n",
297 dev_priv->vbt.bios_lvds_val);
298 }
299 }
300}
301
302static void
303parse_lfp_backlight(struct drm_i915_private *dev_priv,
304 const struct bdb_header *bdb)
305{
306 const struct bdb_lfp_backlight_data *backlight_data;
307 const struct lfp_backlight_data_entry *entry;
308 int panel_type = dev_priv->vbt.panel_type;
309
310 backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
311 if (!backlight_data)
312 return;
313
314 if (backlight_data->entry_size != sizeof(backlight_data->data[0])) {
315 DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n",
316 backlight_data->entry_size);
317 return;
318 }
319
320 entry = &backlight_data->data[panel_type];
321
322 dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM;
323 if (!dev_priv->vbt.backlight.present) {
324 DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n",
325 entry->type);
326 return;
327 }
328
329 dev_priv->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
330 if (bdb->version >= 191 &&
331 get_blocksize(backlight_data) >= sizeof(*backlight_data)) {
332 const struct lfp_backlight_control_method *method;
333
334 method = &backlight_data->backlight_control[panel_type];
335 dev_priv->vbt.backlight.type = method->type;
336 dev_priv->vbt.backlight.controller = method->controller;
337 }
338
339 dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
340 dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm;
341 dev_priv->vbt.backlight.min_brightness = entry->min_brightness;
342 DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, "
343 "active %s, min brightness %u, level %u, controller %u\n",
344 dev_priv->vbt.backlight.pwm_freq_hz,
345 dev_priv->vbt.backlight.active_low_pwm ? "low" : "high",
346 dev_priv->vbt.backlight.min_brightness,
347 backlight_data->level[panel_type],
348 dev_priv->vbt.backlight.controller);
349}
350
351
352static void
353parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
354 const struct bdb_header *bdb)
355{
356 const struct bdb_sdvo_panel_dtds *dtds;
357 struct drm_display_mode *panel_fixed_mode;
358 int index;
359
360 index = i915_modparams.vbt_sdvo_panel_type;
361 if (index == -2) {
362 DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n");
363 return;
364 }
365
366 if (index == -1) {
367 const struct bdb_sdvo_lvds_options *sdvo_lvds_options;
368
369 sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
370 if (!sdvo_lvds_options)
371 return;
372
373 index = sdvo_lvds_options->panel_type;
374 }
375
376 dtds = find_section(bdb, BDB_SDVO_PANEL_DTDS);
377 if (!dtds)
378 return;
379
380 panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL);
381 if (!panel_fixed_mode)
382 return;
383
384 fill_detail_timing_data(panel_fixed_mode, &dtds->dtds[index]);
385
386 dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode;
387
388 DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n");
389 drm_mode_debug_printmodeline(panel_fixed_mode);
390}
391
392static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
393 bool alternate)
394{
395 switch (INTEL_GEN(dev_priv)) {
396 case 2:
397 return alternate ? 66667 : 48000;
398 case 3:
399 case 4:
400 return alternate ? 100000 : 96000;
401 default:
402 return alternate ? 100000 : 120000;
403 }
404}
405
406static void
407parse_general_features(struct drm_i915_private *dev_priv,
408 const struct bdb_header *bdb)
409{
410 const struct bdb_general_features *general;
411
412 general = find_section(bdb, BDB_GENERAL_FEATURES);
413 if (!general)
414 return;
415
416 dev_priv->vbt.int_tv_support = general->int_tv_support;
417
418 if (bdb->version >= 155 &&
419 (HAS_DDI(dev_priv) || IS_VALLEYVIEW(dev_priv)))
420 dev_priv->vbt.int_crt_support = general->int_crt_support;
421 dev_priv->vbt.lvds_use_ssc = general->enable_ssc;
422 dev_priv->vbt.lvds_ssc_freq =
423 intel_bios_ssc_frequency(dev_priv, general->ssc_freq);
424 dev_priv->vbt.display_clock_mode = general->display_clock_mode;
425 dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
426 if (bdb->version >= 181) {
427 dev_priv->vbt.orientation = general->rotate_180 ?
428 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
429 DRM_MODE_PANEL_ORIENTATION_NORMAL;
430 } else {
431 dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
432 }
433 DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
434 dev_priv->vbt.int_tv_support,
435 dev_priv->vbt.int_crt_support,
436 dev_priv->vbt.lvds_use_ssc,
437 dev_priv->vbt.lvds_ssc_freq,
438 dev_priv->vbt.display_clock_mode,
439 dev_priv->vbt.fdi_rx_polarity_inverted);
440}
441
442static const struct child_device_config *
443child_device_ptr(const struct bdb_general_definitions *defs, int i)
444{
445 return (const void *) &defs->devices[i * defs->child_dev_size];
446}
447
448static void
449parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)
450{
451 struct sdvo_device_mapping *mapping;
452 const struct child_device_config *child;
453 int i, count = 0;
454
455
456
457
458
459 if (!IS_GEN_RANGE(dev_priv, 3, 7)) {
460 DRM_DEBUG_KMS("Skipping SDVO device mapping\n");
461 return;
462 }
463
464 for (i = 0, count = 0; i < dev_priv->vbt.child_dev_num; i++) {
465 child = dev_priv->vbt.child_dev + i;
466
467 if (child->slave_addr != SLAVE_ADDR1 &&
468 child->slave_addr != SLAVE_ADDR2) {
469
470
471
472
473 continue;
474 }
475 if (child->dvo_port != DEVICE_PORT_DVOB &&
476 child->dvo_port != DEVICE_PORT_DVOC) {
477
478 DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n");
479 continue;
480 }
481 DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on"
482 " %s port\n",
483 child->slave_addr,
484 (child->dvo_port == DEVICE_PORT_DVOB) ?
485 "SDVOB" : "SDVOC");
486 mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1];
487 if (!mapping->initialized) {
488 mapping->dvo_port = child->dvo_port;
489 mapping->slave_addr = child->slave_addr;
490 mapping->dvo_wiring = child->dvo_wiring;
491 mapping->ddc_pin = child->ddc_pin;
492 mapping->i2c_pin = child->i2c_pin;
493 mapping->initialized = 1;
494 DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n",
495 mapping->dvo_port,
496 mapping->slave_addr,
497 mapping->dvo_wiring,
498 mapping->ddc_pin,
499 mapping->i2c_pin);
500 } else {
501 DRM_DEBUG_KMS("Maybe one SDVO port is shared by "
502 "two SDVO device.\n");
503 }
504 if (child->slave2_addr) {
505
506
507 DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this"
508 " is a SDVO device with multiple inputs.\n");
509 }
510 count++;
511 }
512
513 if (!count) {
514
515 DRM_DEBUG_KMS("No SDVO device info is found in VBT\n");
516 }
517}
518
519static void
520parse_driver_features(struct drm_i915_private *dev_priv,
521 const struct bdb_header *bdb)
522{
523 const struct bdb_driver_features *driver;
524
525 driver = find_section(bdb, BDB_DRIVER_FEATURES);
526 if (!driver)
527 return;
528
529 if (INTEL_GEN(dev_priv) >= 5) {
530
531
532
533
534
535 if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
536 dev_priv->vbt.int_lvds_support = 0;
537 } else {
538
539
540
541
542
543
544
545
546
547
548
549 if (bdb->version >= 134 &&
550 driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
551 driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
552 dev_priv->vbt.int_lvds_support = 0;
553 }
554
555 DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled);
556
557
558
559
560
561
562 if (!driver->drrs_enabled)
563 dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED;
564 dev_priv->vbt.psr.enable = driver->psr_enabled;
565}
566
567static void
568parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
569{
570 const struct bdb_edp *edp;
571 const struct edp_power_seq *edp_pps;
572 const struct edp_fast_link_params *edp_link_params;
573 int panel_type = dev_priv->vbt.panel_type;
574
575 edp = find_section(bdb, BDB_EDP);
576 if (!edp)
577 return;
578
579 switch ((edp->color_depth >> (panel_type * 2)) & 3) {
580 case EDP_18BPP:
581 dev_priv->vbt.edp.bpp = 18;
582 break;
583 case EDP_24BPP:
584 dev_priv->vbt.edp.bpp = 24;
585 break;
586 case EDP_30BPP:
587 dev_priv->vbt.edp.bpp = 30;
588 break;
589 }
590
591
592 edp_pps = &edp->power_seqs[panel_type];
593 edp_link_params = &edp->fast_link_params[panel_type];
594
595 dev_priv->vbt.edp.pps = *edp_pps;
596
597 switch (edp_link_params->rate) {
598 case EDP_RATE_1_62:
599 dev_priv->vbt.edp.rate = DP_LINK_BW_1_62;
600 break;
601 case EDP_RATE_2_7:
602 dev_priv->vbt.edp.rate = DP_LINK_BW_2_7;
603 break;
604 default:
605 DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
606 edp_link_params->rate);
607 break;
608 }
609
610 switch (edp_link_params->lanes) {
611 case EDP_LANE_1:
612 dev_priv->vbt.edp.lanes = 1;
613 break;
614 case EDP_LANE_2:
615 dev_priv->vbt.edp.lanes = 2;
616 break;
617 case EDP_LANE_4:
618 dev_priv->vbt.edp.lanes = 4;
619 break;
620 default:
621 DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
622 edp_link_params->lanes);
623 break;
624 }
625
626 switch (edp_link_params->preemphasis) {
627 case EDP_PREEMPHASIS_NONE:
628 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0;
629 break;
630 case EDP_PREEMPHASIS_3_5dB:
631 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1;
632 break;
633 case EDP_PREEMPHASIS_6dB:
634 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2;
635 break;
636 case EDP_PREEMPHASIS_9_5dB:
637 dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3;
638 break;
639 default:
640 DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
641 edp_link_params->preemphasis);
642 break;
643 }
644
645 switch (edp_link_params->vswing) {
646 case EDP_VSWING_0_4V:
647 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
648 break;
649 case EDP_VSWING_0_6V:
650 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
651 break;
652 case EDP_VSWING_0_8V:
653 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
654 break;
655 case EDP_VSWING_1_2V:
656 dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
657 break;
658 default:
659 DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
660 edp_link_params->vswing);
661 break;
662 }
663
664 if (bdb->version >= 173) {
665 u8 vswing;
666
667
668 if (i915_modparams.edp_vswing) {
669 dev_priv->vbt.edp.low_vswing =
670 i915_modparams.edp_vswing == 1;
671 } else {
672 vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF;
673 dev_priv->vbt.edp.low_vswing = vswing == 0;
674 }
675 }
676}
677
678static void
679parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb)
680{
681 const struct bdb_psr *psr;
682 const struct psr_table *psr_table;
683 int panel_type = dev_priv->vbt.panel_type;
684
685 psr = find_section(bdb, BDB_PSR);
686 if (!psr) {
687 DRM_DEBUG_KMS("No PSR BDB found.\n");
688 return;
689 }
690
691 psr_table = &psr->psr_table[panel_type];
692
693 dev_priv->vbt.psr.full_link = psr_table->full_link;
694 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;
695
696
697 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 :
698 psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames;
699
700 switch (psr_table->lines_to_wait) {
701 case 0:
702 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT;
703 break;
704 case 1:
705 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT;
706 break;
707 case 2:
708 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT;
709 break;
710 case 3:
711 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT;
712 break;
713 default:
714 DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n",
715 psr_table->lines_to_wait);
716 break;
717 }
718
719
720
721
722
723 if (bdb->version >= 205 &&
724 (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) ||
725 INTEL_GEN(dev_priv) >= 10)) {
726 switch (psr_table->tp1_wakeup_time) {
727 case 0:
728 dev_priv->vbt.psr.tp1_wakeup_time_us = 500;
729 break;
730 case 1:
731 dev_priv->vbt.psr.tp1_wakeup_time_us = 100;
732 break;
733 case 3:
734 dev_priv->vbt.psr.tp1_wakeup_time_us = 0;
735 break;
736 default:
737 DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
738 psr_table->tp1_wakeup_time);
739
740 case 2:
741 dev_priv->vbt.psr.tp1_wakeup_time_us = 2500;
742 break;
743 }
744
745 switch (psr_table->tp2_tp3_wakeup_time) {
746 case 0:
747 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 500;
748 break;
749 case 1:
750 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 100;
751 break;
752 case 3:
753 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0;
754 break;
755 default:
756 DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n",
757 psr_table->tp2_tp3_wakeup_time);
758
759 case 2:
760 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500;
761 break;
762 }
763 } else {
764 dev_priv->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;
765 dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
766 }
767
768 if (bdb->version >= 226) {
769 u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
770
771 wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
772 switch (wakeup_time) {
773 case 0:
774 wakeup_time = 500;
775 break;
776 case 1:
777 wakeup_time = 100;
778 break;
779 case 3:
780 wakeup_time = 50;
781 break;
782 default:
783 case 2:
784 wakeup_time = 2500;
785 break;
786 }
787 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
788 } else {
789
790 dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
791 }
792}
793
794static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
795 u16 version, enum port port)
796{
797 if (!dev_priv->vbt.dsi.config->dual_link || version < 197) {
798 dev_priv->vbt.dsi.bl_ports = BIT(port);
799 if (dev_priv->vbt.dsi.config->cabc_supported)
800 dev_priv->vbt.dsi.cabc_ports = BIT(port);
801
802 return;
803 }
804
805 switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) {
806 case DL_DCS_PORT_A:
807 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A);
808 break;
809 case DL_DCS_PORT_C:
810 dev_priv->vbt.dsi.bl_ports = BIT(PORT_C);
811 break;
812 default:
813 case DL_DCS_PORT_A_AND_C:
814 dev_priv->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(PORT_C);
815 break;
816 }
817
818 if (!dev_priv->vbt.dsi.config->cabc_supported)
819 return;
820
821 switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) {
822 case DL_DCS_PORT_A:
823 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_A);
824 break;
825 case DL_DCS_PORT_C:
826 dev_priv->vbt.dsi.cabc_ports = BIT(PORT_C);
827 break;
828 default:
829 case DL_DCS_PORT_A_AND_C:
830 dev_priv->vbt.dsi.cabc_ports =
831 BIT(PORT_A) | BIT(PORT_C);
832 break;
833 }
834}
835
836static void
837parse_mipi_config(struct drm_i915_private *dev_priv,
838 const struct bdb_header *bdb)
839{
840 const struct bdb_mipi_config *start;
841 const struct mipi_config *config;
842 const struct mipi_pps_data *pps;
843 int panel_type = dev_priv->vbt.panel_type;
844 enum port port;
845
846
847 if (!intel_bios_is_dsi_present(dev_priv, &port))
848 return;
849
850
851 dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID;
852
853
854
855
856
857
858
859
860
861 start = find_section(bdb, BDB_MIPI_CONFIG);
862 if (!start) {
863 DRM_DEBUG_KMS("No MIPI config BDB found");
864 return;
865 }
866
867 DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n",
868 panel_type);
869
870
871
872
873
874 config = &start->config[panel_type];
875 pps = &start->pps[panel_type];
876
877
878 dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL);
879 if (!dev_priv->vbt.dsi.config)
880 return;
881
882 dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL);
883 if (!dev_priv->vbt.dsi.pps) {
884 kfree(dev_priv->vbt.dsi.config);
885 return;
886 }
887
888 parse_dsi_backlight_ports(dev_priv, bdb->version, port);
889
890
891 switch (config->rotation) {
892 case ENABLE_ROTATION_0:
893
894
895
896
897 dev_priv->vbt.dsi.orientation =
898 DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
899 break;
900 case ENABLE_ROTATION_90:
901 dev_priv->vbt.dsi.orientation =
902 DRM_MODE_PANEL_ORIENTATION_RIGHT_UP;
903 break;
904 case ENABLE_ROTATION_180:
905 dev_priv->vbt.dsi.orientation =
906 DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
907 break;
908 case ENABLE_ROTATION_270:
909 dev_priv->vbt.dsi.orientation =
910 DRM_MODE_PANEL_ORIENTATION_LEFT_UP;
911 break;
912 }
913
914
915 dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID;
916}
917
918
919static const u8 *
920find_panel_sequence_block(const struct bdb_mipi_sequence *sequence,
921 u16 panel_id, u32 *seq_size)
922{
923 u32 total = get_blocksize(sequence);
924 const u8 *data = &sequence->data[0];
925 u8 current_id;
926 u32 current_size;
927 int header_size = sequence->version >= 3 ? 5 : 3;
928 int index = 0;
929 int i;
930
931
932 if (sequence->version >= 3)
933 data += 4;
934
935 for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) {
936 if (index + header_size > total) {
937 DRM_ERROR("Invalid sequence block (header)\n");
938 return NULL;
939 }
940
941 current_id = *(data + index);
942 if (sequence->version >= 3)
943 current_size = *((const u32 *)(data + index + 1));
944 else
945 current_size = *((const u16 *)(data + index + 1));
946
947 index += header_size;
948
949 if (index + current_size > total) {
950 DRM_ERROR("Invalid sequence block\n");
951 return NULL;
952 }
953
954 if (current_id == panel_id) {
955 *seq_size = current_size;
956 return data + index;
957 }
958
959 index += current_size;
960 }
961
962 DRM_ERROR("Sequence block detected but no valid configuration\n");
963
964 return NULL;
965}
966
967static int goto_next_sequence(const u8 *data, int index, int total)
968{
969 u16 len;
970
971
972 for (index = index + 1; index < total; index += len) {
973 u8 operation_byte = *(data + index);
974 index++;
975
976 switch (operation_byte) {
977 case MIPI_SEQ_ELEM_END:
978 return index;
979 case MIPI_SEQ_ELEM_SEND_PKT:
980 if (index + 4 > total)
981 return 0;
982
983 len = *((const u16 *)(data + index + 2)) + 4;
984 break;
985 case MIPI_SEQ_ELEM_DELAY:
986 len = 4;
987 break;
988 case MIPI_SEQ_ELEM_GPIO:
989 len = 2;
990 break;
991 case MIPI_SEQ_ELEM_I2C:
992 if (index + 7 > total)
993 return 0;
994 len = *(data + index + 6) + 7;
995 break;
996 default:
997 DRM_ERROR("Unknown operation byte\n");
998 return 0;
999 }
1000 }
1001
1002 return 0;
1003}
1004
1005static int goto_next_sequence_v3(const u8 *data, int index, int total)
1006{
1007 int seq_end;
1008 u16 len;
1009 u32 size_of_sequence;
1010
1011
1012
1013
1014
1015 if (total < 5) {
1016 DRM_ERROR("Too small sequence size\n");
1017 return 0;
1018 }
1019
1020
1021 index++;
1022
1023
1024
1025
1026
1027
1028 size_of_sequence = *((const u32 *)(data + index));
1029 index += 4;
1030
1031 seq_end = index + size_of_sequence;
1032 if (seq_end > total) {
1033 DRM_ERROR("Invalid sequence size\n");
1034 return 0;
1035 }
1036
1037 for (; index < total; index += len) {
1038 u8 operation_byte = *(data + index);
1039 index++;
1040
1041 if (operation_byte == MIPI_SEQ_ELEM_END) {
1042 if (index != seq_end) {
1043 DRM_ERROR("Invalid element structure\n");
1044 return 0;
1045 }
1046 return index;
1047 }
1048
1049 len = *(data + index);
1050 index++;
1051
1052
1053
1054
1055
1056 switch (operation_byte) {
1057 case MIPI_SEQ_ELEM_SEND_PKT:
1058 case MIPI_SEQ_ELEM_DELAY:
1059 case MIPI_SEQ_ELEM_GPIO:
1060 case MIPI_SEQ_ELEM_I2C:
1061 case MIPI_SEQ_ELEM_SPI:
1062 case MIPI_SEQ_ELEM_PMIC:
1063 break;
1064 default:
1065 DRM_ERROR("Unknown operation byte %u\n",
1066 operation_byte);
1067 break;
1068 }
1069 }
1070
1071 return 0;
1072}
1073
1074
1075
1076
1077
1078static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv)
1079{
1080 const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1081 int index, len;
1082
1083 if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1))
1084 return 0;
1085
1086
1087 for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) {
1088 switch (data[index]) {
1089 case MIPI_SEQ_ELEM_SEND_PKT:
1090 return index == 1 ? 0 : index;
1091 case MIPI_SEQ_ELEM_DELAY:
1092 len = 5;
1093 break;
1094 case MIPI_SEQ_ELEM_GPIO:
1095 len = 3;
1096 break;
1097 default:
1098 return 0;
1099 }
1100 }
1101
1102 return 0;
1103}
1104
1105
1106
1107
1108
1109
1110
1111static void fixup_mipi_sequences(struct drm_i915_private *dev_priv)
1112{
1113 u8 *init_otp;
1114 int len;
1115
1116
1117 if (!IS_VALLEYVIEW(dev_priv))
1118 return;
1119
1120
1121 if (dev_priv->vbt.dsi.config->is_cmd_mode ||
1122 dev_priv->vbt.dsi.seq_version != 1)
1123 return;
1124
1125
1126 if (!dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] ||
1127 !dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] ||
1128 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET])
1129 return;
1130
1131
1132 len = get_init_otp_deassert_fragment_len(dev_priv);
1133 if (!len)
1134 return;
1135
1136 DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n");
1137
1138
1139 init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
1140 dev_priv->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL);
1141 if (!dev_priv->vbt.dsi.deassert_seq)
1142 return;
1143 dev_priv->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET;
1144 dev_priv->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END;
1145
1146 dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] =
1147 dev_priv->vbt.dsi.deassert_seq;
1148
1149 init_otp[len - 1] = MIPI_SEQ_INIT_OTP;
1150
1151 dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1;
1152}
1153
1154static void
1155parse_mipi_sequence(struct drm_i915_private *dev_priv,
1156 const struct bdb_header *bdb)
1157{
1158 int panel_type = dev_priv->vbt.panel_type;
1159 const struct bdb_mipi_sequence *sequence;
1160 const u8 *seq_data;
1161 u32 seq_size;
1162 u8 *data;
1163 int index = 0;
1164
1165
1166 if (dev_priv->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID)
1167 return;
1168
1169 sequence = find_section(bdb, BDB_MIPI_SEQUENCE);
1170 if (!sequence) {
1171 DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n");
1172 return;
1173 }
1174
1175
1176 if (sequence->version >= 4) {
1177 DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n",
1178 sequence->version);
1179 return;
1180 }
1181
1182 DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version);
1183
1184 seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size);
1185 if (!seq_data)
1186 return;
1187
1188 data = kmemdup(seq_data, seq_size, GFP_KERNEL);
1189 if (!data)
1190 return;
1191
1192
1193 for (;;) {
1194 u8 seq_id = *(data + index);
1195 if (seq_id == MIPI_SEQ_END)
1196 break;
1197
1198 if (seq_id >= MIPI_SEQ_MAX) {
1199 DRM_ERROR("Unknown sequence %u\n", seq_id);
1200 goto err;
1201 }
1202
1203
1204 if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF)
1205 DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id);
1206
1207 dev_priv->vbt.dsi.sequence[seq_id] = data + index;
1208
1209 if (sequence->version >= 3)
1210 index = goto_next_sequence_v3(data, index, seq_size);
1211 else
1212 index = goto_next_sequence(data, index, seq_size);
1213 if (!index) {
1214 DRM_ERROR("Invalid sequence %u\n", seq_id);
1215 goto err;
1216 }
1217 }
1218
1219 dev_priv->vbt.dsi.data = data;
1220 dev_priv->vbt.dsi.size = seq_size;
1221 dev_priv->vbt.dsi.seq_version = sequence->version;
1222
1223 fixup_mipi_sequences(dev_priv);
1224
1225 DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n");
1226 return;
1227
1228err:
1229 kfree(data);
1230 memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
1231}
1232
1233static u8 translate_iboost(u8 val)
1234{
1235 static const u8 mapping[] = { 1, 3, 7 };
1236
1237 if (val >= ARRAY_SIZE(mapping)) {
1238 DRM_DEBUG_KMS("Unsupported I_boost value found in VBT (%d), display may not work properly\n", val);
1239 return 0;
1240 }
1241 return mapping[val];
1242}
1243
1244static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
1245{
1246 const struct ddi_vbt_port_info *info;
1247 enum port port;
1248
1249 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1250 info = &i915->vbt.ddi_port_info[port];
1251
1252 if (info->child && ddc_pin == info->alternate_ddc_pin)
1253 return port;
1254 }
1255
1256 return PORT_NONE;
1257}
1258
1259static void sanitize_ddc_pin(struct drm_i915_private *dev_priv,
1260 enum port port)
1261{
1262 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1263 enum port p;
1264
1265 if (!info->alternate_ddc_pin)
1266 return;
1267
1268 p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin);
1269 if (p != PORT_NONE) {
1270 DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, "
1271 "disabling port %c DVI/HDMI support\n",
1272 port_name(port), info->alternate_ddc_pin,
1273 port_name(p), port_name(p));
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287 info = &dev_priv->vbt.ddi_port_info[p];
1288
1289 info->supports_dvi = false;
1290 info->supports_hdmi = false;
1291 info->alternate_ddc_pin = 0;
1292 }
1293}
1294
1295static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
1296{
1297 const struct ddi_vbt_port_info *info;
1298 enum port port;
1299
1300 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1301 info = &i915->vbt.ddi_port_info[port];
1302
1303 if (info->child && aux_ch == info->alternate_aux_channel)
1304 return port;
1305 }
1306
1307 return PORT_NONE;
1308}
1309
1310static void sanitize_aux_ch(struct drm_i915_private *dev_priv,
1311 enum port port)
1312{
1313 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
1314 enum port p;
1315
1316 if (!info->alternate_aux_channel)
1317 return;
1318
1319 p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel);
1320 if (p != PORT_NONE) {
1321 DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, "
1322 "disabling port %c DP support\n",
1323 port_name(port), info->alternate_aux_channel,
1324 port_name(p), port_name(p));
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338 info = &dev_priv->vbt.ddi_port_info[p];
1339
1340 info->supports_dp = false;
1341 info->alternate_aux_channel = 0;
1342 }
1343}
1344
1345static const u8 cnp_ddc_pin_map[] = {
1346 [0] = 0,
1347 [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
1348 [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
1349 [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP,
1350 [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT,
1351};
1352
1353static const u8 icp_ddc_pin_map[] = {
1354 [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
1355 [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
1356 [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
1357 [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
1358 [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
1359 [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
1360 [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
1361 [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
1362 [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
1363};
1364
1365static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
1366{
1367 const u8 *ddc_pin_map;
1368 int n_entries;
1369
1370 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
1371 ddc_pin_map = icp_ddc_pin_map;
1372 n_entries = ARRAY_SIZE(icp_ddc_pin_map);
1373 } else if (HAS_PCH_CNP(dev_priv)) {
1374 ddc_pin_map = cnp_ddc_pin_map;
1375 n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
1376 } else {
1377
1378 return vbt_pin;
1379 }
1380
1381 if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
1382 return ddc_pin_map[vbt_pin];
1383
1384 DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n",
1385 vbt_pin);
1386 return 0;
1387}
1388
1389static enum port dvo_port_to_port(u8 dvo_port)
1390{
1391
1392
1393
1394
1395 static const int dvo_ports[][3] = {
1396 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1},
1397 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1},
1398 [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1},
1399 [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1},
1400 [PORT_E] = { DVO_PORT_CRT, DVO_PORT_HDMIE, DVO_PORT_DPE},
1401 [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1},
1402 [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1},
1403 };
1404 enum port port;
1405 int i;
1406
1407 for (port = PORT_A; port < ARRAY_SIZE(dvo_ports); port++) {
1408 for (i = 0; i < ARRAY_SIZE(dvo_ports[port]); i++) {
1409 if (dvo_ports[port][i] == -1)
1410 break;
1411
1412 if (dvo_port == dvo_ports[port][i])
1413 return port;
1414 }
1415 }
1416
1417 return PORT_NONE;
1418}
1419
1420static void parse_ddi_port(struct drm_i915_private *dev_priv,
1421 const struct child_device_config *child,
1422 u8 bdb_version)
1423{
1424 struct ddi_vbt_port_info *info;
1425 bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
1426 enum port port;
1427
1428 port = dvo_port_to_port(child->dvo_port);
1429 if (port == PORT_NONE)
1430 return;
1431
1432 info = &dev_priv->vbt.ddi_port_info[port];
1433
1434 if (info->child) {
1435 DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n",
1436 port_name(port));
1437 return;
1438 }
1439
1440 is_dvi = child->device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING;
1441 is_dp = child->device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT;
1442 is_crt = child->device_type & DEVICE_TYPE_ANALOG_OUTPUT;
1443 is_hdmi = is_dvi && (child->device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0;
1444 is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR);
1445
1446 if (port == PORT_A && is_dvi) {
1447 DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n",
1448 is_hdmi ? "/HDMI" : "");
1449 is_dvi = false;
1450 is_hdmi = false;
1451 }
1452
1453 info->supports_dvi = is_dvi;
1454 info->supports_hdmi = is_hdmi;
1455 info->supports_dp = is_dp;
1456 info->supports_edp = is_edp;
1457
1458 if (bdb_version >= 195)
1459 info->supports_typec_usb = child->dp_usb_type_c;
1460
1461 if (bdb_version >= 209)
1462 info->supports_tbt = child->tbt;
1463
1464 DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
1465 port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
1466 HAS_LSPCON(dev_priv) && child->lspcon,
1467 info->supports_typec_usb, info->supports_tbt);
1468
1469 if (is_edp && is_dvi)
1470 DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
1471 port_name(port));
1472 if (is_crt && port != PORT_E)
1473 DRM_DEBUG_KMS("Port %c is analog\n", port_name(port));
1474 if (is_crt && (is_dvi || is_dp))
1475 DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n",
1476 port_name(port));
1477 if (is_dvi && (port == PORT_A || port == PORT_E))
1478 DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port));
1479 if (!is_dvi && !is_dp && !is_crt)
1480 DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n",
1481 port_name(port));
1482 if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
1483 DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port));
1484
1485 if (is_dvi) {
1486 u8 ddc_pin;
1487
1488 ddc_pin = map_ddc_pin(dev_priv, child->ddc_pin);
1489 if (intel_gmbus_is_valid_pin(dev_priv, ddc_pin)) {
1490 info->alternate_ddc_pin = ddc_pin;
1491 sanitize_ddc_pin(dev_priv, port);
1492 } else {
1493 DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, "
1494 "sticking to defaults\n",
1495 port_name(port), ddc_pin);
1496 }
1497 }
1498
1499 if (is_dp) {
1500 info->alternate_aux_channel = child->aux_channel;
1501
1502 sanitize_aux_ch(dev_priv, port);
1503 }
1504
1505 if (bdb_version >= 158) {
1506
1507 u8 hdmi_level_shift = child->hdmi_level_shifter_value;
1508 DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n",
1509 port_name(port),
1510 hdmi_level_shift);
1511 info->hdmi_level_shift = hdmi_level_shift;
1512 }
1513
1514 if (bdb_version >= 204) {
1515 int max_tmds_clock;
1516
1517 switch (child->hdmi_max_data_rate) {
1518 default:
1519 MISSING_CASE(child->hdmi_max_data_rate);
1520
1521 case HDMI_MAX_DATA_RATE_PLATFORM:
1522 max_tmds_clock = 0;
1523 break;
1524 case HDMI_MAX_DATA_RATE_297:
1525 max_tmds_clock = 297000;
1526 break;
1527 case HDMI_MAX_DATA_RATE_165:
1528 max_tmds_clock = 165000;
1529 break;
1530 }
1531
1532 if (max_tmds_clock)
1533 DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n",
1534 port_name(port), max_tmds_clock);
1535 info->max_tmds_clock = max_tmds_clock;
1536 }
1537
1538
1539 if (bdb_version >= 196 && child->iboost) {
1540 info->dp_boost_level = translate_iboost(child->dp_iboost_level);
1541 DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n",
1542 port_name(port), info->dp_boost_level);
1543 info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level);
1544 DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n",
1545 port_name(port), info->hdmi_boost_level);
1546 }
1547
1548
1549 if (bdb_version >= 216) {
1550 switch (child->dp_max_link_rate) {
1551 default:
1552 case VBT_DP_MAX_LINK_RATE_HBR3:
1553 info->dp_max_link_rate = 810000;
1554 break;
1555 case VBT_DP_MAX_LINK_RATE_HBR2:
1556 info->dp_max_link_rate = 540000;
1557 break;
1558 case VBT_DP_MAX_LINK_RATE_HBR:
1559 info->dp_max_link_rate = 270000;
1560 break;
1561 case VBT_DP_MAX_LINK_RATE_LBR:
1562 info->dp_max_link_rate = 162000;
1563 break;
1564 }
1565 DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n",
1566 port_name(port), info->dp_max_link_rate);
1567 }
1568
1569 info->child = child;
1570}
1571
1572static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
1573{
1574 const struct child_device_config *child;
1575 int i;
1576
1577 if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1578 return;
1579
1580 if (bdb_version < 155)
1581 return;
1582
1583 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1584 child = dev_priv->vbt.child_dev + i;
1585
1586 parse_ddi_port(dev_priv, child, bdb_version);
1587 }
1588}
1589
1590static void
1591parse_general_definitions(struct drm_i915_private *dev_priv,
1592 const struct bdb_header *bdb)
1593{
1594 const struct bdb_general_definitions *defs;
1595 const struct child_device_config *child;
1596 int i, child_device_num, count;
1597 u8 expected_size;
1598 u16 block_size;
1599 int bus_pin;
1600
1601 defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
1602 if (!defs) {
1603 DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
1604 return;
1605 }
1606
1607 block_size = get_blocksize(defs);
1608 if (block_size < sizeof(*defs)) {
1609 DRM_DEBUG_KMS("General definitions block too small (%u)\n",
1610 block_size);
1611 return;
1612 }
1613
1614 bus_pin = defs->crt_ddc_gmbus_pin;
1615 DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin);
1616 if (intel_gmbus_is_valid_pin(dev_priv, bus_pin))
1617 dev_priv->vbt.crt_ddc_pin = bus_pin;
1618
1619 if (bdb->version < 106) {
1620 expected_size = 22;
1621 } else if (bdb->version < 111) {
1622 expected_size = 27;
1623 } else if (bdb->version < 195) {
1624 expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
1625 } else if (bdb->version == 195) {
1626 expected_size = 37;
1627 } else if (bdb->version <= 215) {
1628 expected_size = 38;
1629 } else if (bdb->version <= 229) {
1630 expected_size = 39;
1631 } else {
1632 expected_size = sizeof(*child);
1633 BUILD_BUG_ON(sizeof(*child) < 39);
1634 DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n",
1635 bdb->version, expected_size);
1636 }
1637
1638
1639 if (defs->child_dev_size != expected_size)
1640 DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n",
1641 defs->child_dev_size, expected_size, bdb->version);
1642
1643
1644 if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
1645 DRM_DEBUG_KMS("Child device config size %u is too small.\n",
1646 defs->child_dev_size);
1647 return;
1648 }
1649
1650
1651 child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size;
1652 count = 0;
1653
1654 for (i = 0; i < child_device_num; i++) {
1655 child = child_device_ptr(defs, i);
1656 if (!child->device_type)
1657 continue;
1658 count++;
1659 }
1660 if (!count) {
1661 DRM_DEBUG_KMS("no child dev is parsed from VBT\n");
1662 return;
1663 }
1664 dev_priv->vbt.child_dev = kcalloc(count, sizeof(*child), GFP_KERNEL);
1665 if (!dev_priv->vbt.child_dev) {
1666 DRM_DEBUG_KMS("No memory space for child device\n");
1667 return;
1668 }
1669
1670 dev_priv->vbt.child_dev_num = count;
1671 count = 0;
1672 for (i = 0; i < child_device_num; i++) {
1673 child = child_device_ptr(defs, i);
1674 if (!child->device_type)
1675 continue;
1676
1677 DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n",
1678 child->device_type);
1679
1680
1681
1682
1683
1684
1685 memcpy(dev_priv->vbt.child_dev + count, child,
1686 min_t(size_t, defs->child_dev_size, sizeof(*child)));
1687 count++;
1688 }
1689}
1690
1691
1692static void
1693init_vbt_defaults(struct drm_i915_private *dev_priv)
1694{
1695 enum port port;
1696
1697 dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
1698
1699
1700 dev_priv->vbt.backlight.present = true;
1701
1702
1703 dev_priv->vbt.lvds_dither = 1;
1704
1705
1706 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1707
1708
1709 dev_priv->vbt.int_tv_support = 1;
1710 dev_priv->vbt.int_crt_support = 1;
1711
1712
1713 dev_priv->vbt.int_lvds_support = 1;
1714
1715
1716 dev_priv->vbt.lvds_use_ssc = 1;
1717
1718
1719
1720
1721 dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv,
1722 !HAS_PCH_SPLIT(dev_priv));
1723 DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
1724
1725 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1726 struct ddi_vbt_port_info *info =
1727 &dev_priv->vbt.ddi_port_info[port];
1728
1729 info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN;
1730 }
1731}
1732
1733
1734static void
1735init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
1736{
1737 enum port port;
1738
1739 for (port = PORT_A; port < I915_MAX_PORTS; port++) {
1740 struct ddi_vbt_port_info *info =
1741 &dev_priv->vbt.ddi_port_info[port];
1742 enum phy phy = intel_port_to_phy(dev_priv, port);
1743
1744
1745
1746
1747
1748 if (intel_phy_is_tc(dev_priv, phy))
1749 continue;
1750
1751 info->supports_dvi = (port != PORT_A && port != PORT_E);
1752 info->supports_hdmi = info->supports_dvi;
1753 info->supports_dp = (port != PORT_E);
1754 info->supports_edp = (port == PORT_A);
1755 }
1756}
1757
1758static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
1759{
1760 const void *_vbt = vbt;
1761
1762 return _vbt + vbt->bdb_offset;
1763}
1764
1765
1766
1767
1768
1769
1770
1771
1772bool intel_bios_is_valid_vbt(const void *buf, size_t size)
1773{
1774 const struct vbt_header *vbt = buf;
1775 const struct bdb_header *bdb;
1776
1777 if (!vbt)
1778 return false;
1779
1780 if (sizeof(struct vbt_header) > size) {
1781 DRM_DEBUG_DRIVER("VBT header incomplete\n");
1782 return false;
1783 }
1784
1785 if (memcmp(vbt->signature, "$VBT", 4)) {
1786 DRM_DEBUG_DRIVER("VBT invalid signature\n");
1787 return false;
1788 }
1789
1790 if (range_overflows_t(size_t,
1791 vbt->bdb_offset,
1792 sizeof(struct bdb_header),
1793 size)) {
1794 DRM_DEBUG_DRIVER("BDB header incomplete\n");
1795 return false;
1796 }
1797
1798 bdb = get_bdb_header(vbt);
1799 if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) {
1800 DRM_DEBUG_DRIVER("BDB incomplete\n");
1801 return false;
1802 }
1803
1804 return vbt;
1805}
1806
1807static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
1808{
1809 size_t i;
1810
1811
1812 for (i = 0; i + 4 < size; i++) {
1813 void *vbt;
1814
1815 if (ioread32(bios + i) != *((const u32 *) "$VBT"))
1816 continue;
1817
1818
1819
1820
1821
1822 vbt = (void __force *) bios + i;
1823 if (intel_bios_is_valid_vbt(vbt, size - i))
1824 return vbt;
1825
1826 break;
1827 }
1828
1829 return NULL;
1830}
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840void intel_bios_init(struct drm_i915_private *dev_priv)
1841{
1842 struct pci_dev *pdev = dev_priv->drm.pdev;
1843 const struct vbt_header *vbt = dev_priv->opregion.vbt;
1844 const struct bdb_header *bdb;
1845 u8 __iomem *bios = NULL;
1846
1847 if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) {
1848 DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n");
1849 return;
1850 }
1851
1852 init_vbt_defaults(dev_priv);
1853
1854
1855 if (!vbt) {
1856 size_t size;
1857
1858 bios = pci_map_rom(pdev, &size);
1859 if (!bios)
1860 goto out;
1861
1862 vbt = find_vbt(bios, size);
1863 if (!vbt)
1864 goto out;
1865
1866 DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n");
1867 }
1868
1869 bdb = get_bdb_header(vbt);
1870
1871 DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n",
1872 (int)sizeof(vbt->signature), vbt->signature, bdb->version);
1873
1874
1875 parse_general_features(dev_priv, bdb);
1876 parse_general_definitions(dev_priv, bdb);
1877 parse_lfp_panel_data(dev_priv, bdb);
1878 parse_lfp_backlight(dev_priv, bdb);
1879 parse_sdvo_panel_data(dev_priv, bdb);
1880 parse_driver_features(dev_priv, bdb);
1881 parse_edp(dev_priv, bdb);
1882 parse_psr(dev_priv, bdb);
1883 parse_mipi_config(dev_priv, bdb);
1884 parse_mipi_sequence(dev_priv, bdb);
1885
1886
1887 parse_sdvo_device_mapping(dev_priv, bdb->version);
1888 parse_ddi_ports(dev_priv, bdb->version);
1889
1890out:
1891 if (!vbt) {
1892 DRM_INFO("Failed to find VBIOS tables (VBT)\n");
1893 init_vbt_missing_defaults(dev_priv);
1894 }
1895
1896 if (bios)
1897 pci_unmap_rom(pdev, bios);
1898}
1899
1900
1901
1902
1903
1904void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
1905{
1906 kfree(dev_priv->vbt.child_dev);
1907 dev_priv->vbt.child_dev = NULL;
1908 dev_priv->vbt.child_dev_num = 0;
1909 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1910 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1911 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1912 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1913 kfree(dev_priv->vbt.dsi.data);
1914 dev_priv->vbt.dsi.data = NULL;
1915 kfree(dev_priv->vbt.dsi.pps);
1916 dev_priv->vbt.dsi.pps = NULL;
1917 kfree(dev_priv->vbt.dsi.config);
1918 dev_priv->vbt.dsi.config = NULL;
1919 kfree(dev_priv->vbt.dsi.deassert_seq);
1920 dev_priv->vbt.dsi.deassert_seq = NULL;
1921}
1922
1923
1924
1925
1926
1927
1928
1929
1930bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv)
1931{
1932 const struct child_device_config *child;
1933 int i;
1934
1935 if (!dev_priv->vbt.int_tv_support)
1936 return false;
1937
1938 if (!dev_priv->vbt.child_dev_num)
1939 return true;
1940
1941 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1942 child = dev_priv->vbt.child_dev + i;
1943
1944
1945
1946 switch (child->device_type) {
1947 case DEVICE_TYPE_INT_TV:
1948 case DEVICE_TYPE_TV:
1949 case DEVICE_TYPE_TV_SVIDEO_COMPOSITE:
1950 break;
1951 default:
1952 continue;
1953 }
1954
1955
1956
1957 if (child->addin_offset)
1958 return true;
1959 }
1960
1961 return false;
1962}
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)
1973{
1974 const struct child_device_config *child;
1975 int i;
1976
1977 if (!dev_priv->vbt.child_dev_num)
1978 return true;
1979
1980 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1981 child = dev_priv->vbt.child_dev + i;
1982
1983
1984
1985
1986
1987 if (child->device_type != DEVICE_TYPE_INT_LFP &&
1988 child->device_type != DEVICE_TYPE_LFP)
1989 continue;
1990
1991 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
1992 *i2c_pin = child->i2c_pin;
1993
1994
1995
1996
1997
1998
1999 if (child->addin_offset)
2000 return true;
2001
2002
2003
2004
2005
2006
2007 if (dev_priv->opregion.vbt)
2008 return true;
2009 }
2010
2011 return false;
2012}
2013
2014
2015
2016
2017
2018
2019
2020
2021bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port)
2022{
2023 const struct child_device_config *child;
2024 static const struct {
2025 u16 dp, hdmi;
2026 } port_mapping[] = {
2027 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2028 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2029 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2030 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
2031 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
2032 };
2033 int i;
2034
2035 if (HAS_DDI(dev_priv)) {
2036 const struct ddi_vbt_port_info *port_info =
2037 &dev_priv->vbt.ddi_port_info[port];
2038
2039 return port_info->supports_dp ||
2040 port_info->supports_dvi ||
2041 port_info->supports_hdmi;
2042 }
2043
2044
2045 if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping))
2046 return false;
2047
2048 if (!dev_priv->vbt.child_dev_num)
2049 return false;
2050
2051 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2052 child = dev_priv->vbt.child_dev + i;
2053
2054 if ((child->dvo_port == port_mapping[port].dp ||
2055 child->dvo_port == port_mapping[port].hdmi) &&
2056 (child->device_type & (DEVICE_TYPE_TMDS_DVI_SIGNALING |
2057 DEVICE_TYPE_DISPLAYPORT_OUTPUT)))
2058 return true;
2059 }
2060
2061 return false;
2062}
2063
2064
2065
2066
2067
2068
2069
2070
2071bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
2072{
2073 const struct child_device_config *child;
2074 static const short port_mapping[] = {
2075 [PORT_B] = DVO_PORT_DPB,
2076 [PORT_C] = DVO_PORT_DPC,
2077 [PORT_D] = DVO_PORT_DPD,
2078 [PORT_E] = DVO_PORT_DPE,
2079 [PORT_F] = DVO_PORT_DPF,
2080 };
2081 int i;
2082
2083 if (HAS_DDI(dev_priv))
2084 return dev_priv->vbt.ddi_port_info[port].supports_edp;
2085
2086 if (!dev_priv->vbt.child_dev_num)
2087 return false;
2088
2089 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2090 child = dev_priv->vbt.child_dev + i;
2091
2092 if (child->dvo_port == port_mapping[port] &&
2093 (child->device_type & DEVICE_TYPE_eDP_BITS) ==
2094 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
2095 return true;
2096 }
2097
2098 return false;
2099}
2100
2101static bool child_dev_is_dp_dual_mode(const struct child_device_config *child,
2102 enum port port)
2103{
2104 static const struct {
2105 u16 dp, hdmi;
2106 } port_mapping[] = {
2107
2108
2109
2110
2111 [PORT_B] = { DVO_PORT_DPB, DVO_PORT_HDMIB, },
2112 [PORT_C] = { DVO_PORT_DPC, DVO_PORT_HDMIC, },
2113 [PORT_D] = { DVO_PORT_DPD, DVO_PORT_HDMID, },
2114 [PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
2115 [PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
2116 };
2117
2118 if (port == PORT_A || port >= ARRAY_SIZE(port_mapping))
2119 return false;
2120
2121 if ((child->device_type & DEVICE_TYPE_DP_DUAL_MODE_BITS) !=
2122 (DEVICE_TYPE_DP_DUAL_MODE & DEVICE_TYPE_DP_DUAL_MODE_BITS))
2123 return false;
2124
2125 if (child->dvo_port == port_mapping[port].dp)
2126 return true;
2127
2128
2129 if (child->dvo_port == port_mapping[port].hdmi &&
2130 child->aux_channel != 0)
2131 return true;
2132
2133 return false;
2134}
2135
2136bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv,
2137 enum port port)
2138{
2139 const struct child_device_config *child;
2140 int i;
2141
2142 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2143 child = dev_priv->vbt.child_dev + i;
2144
2145 if (child_dev_is_dp_dual_mode(child, port))
2146 return true;
2147 }
2148
2149 return false;
2150}
2151
2152
2153
2154
2155
2156
2157
2158
2159bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
2160 enum port *port)
2161{
2162 const struct child_device_config *child;
2163 u8 dvo_port;
2164 int i;
2165
2166 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2167 child = dev_priv->vbt.child_dev + i;
2168
2169 if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
2170 continue;
2171
2172 dvo_port = child->dvo_port;
2173
2174 if (dvo_port == DVO_PORT_MIPIA ||
2175 (dvo_port == DVO_PORT_MIPIB && INTEL_GEN(dev_priv) >= 11) ||
2176 (dvo_port == DVO_PORT_MIPIC && INTEL_GEN(dev_priv) < 11)) {
2177 if (port)
2178 *port = dvo_port - DVO_PORT_MIPIA;
2179 return true;
2180 } else if (dvo_port == DVO_PORT_MIPIB ||
2181 dvo_port == DVO_PORT_MIPIC ||
2182 dvo_port == DVO_PORT_MIPID) {
2183 DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n",
2184 port_name(dvo_port - DVO_PORT_MIPIA));
2185 }
2186 }
2187
2188 return false;
2189}
2190
2191
2192
2193
2194
2195
2196
2197
2198bool
2199intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
2200 enum port port)
2201{
2202 const struct child_device_config *child =
2203 i915->vbt.ddi_port_info[port].child;
2204
2205 if (WARN_ON_ONCE(!IS_GEN9_LP(i915)))
2206 return false;
2207
2208 return child && child->hpd_invert;
2209}
2210
2211
2212
2213
2214
2215
2216
2217
2218bool
2219intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
2220 enum port port)
2221{
2222 const struct child_device_config *child =
2223 i915->vbt.ddi_port_info[port].child;
2224
2225 return HAS_LSPCON(i915) && child && child->lspcon;
2226}
2227
2228enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
2229 enum port port)
2230{
2231 const struct ddi_vbt_port_info *info =
2232 &dev_priv->vbt.ddi_port_info[port];
2233 enum aux_ch aux_ch;
2234
2235 if (!info->alternate_aux_channel) {
2236 aux_ch = (enum aux_ch)port;
2237
2238 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
2239 aux_ch_name(aux_ch), port_name(port));
2240 return aux_ch;
2241 }
2242
2243 switch (info->alternate_aux_channel) {
2244 case DP_AUX_A:
2245 aux_ch = AUX_CH_A;
2246 break;
2247 case DP_AUX_B:
2248 aux_ch = AUX_CH_B;
2249 break;
2250 case DP_AUX_C:
2251 aux_ch = AUX_CH_C;
2252 break;
2253 case DP_AUX_D:
2254 aux_ch = AUX_CH_D;
2255 break;
2256 case DP_AUX_E:
2257 aux_ch = AUX_CH_E;
2258 break;
2259 case DP_AUX_F:
2260 aux_ch = AUX_CH_F;
2261 break;
2262 case DP_AUX_G:
2263 aux_ch = AUX_CH_G;
2264 break;
2265 default:
2266 MISSING_CASE(info->alternate_aux_channel);
2267 aux_ch = AUX_CH_A;
2268 break;
2269 }
2270
2271 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
2272 aux_ch_name(aux_ch), port_name(port));
2273
2274 return aux_ch;
2275}
2276