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26#ifndef __INTEL_DISPLAY_TYPES_H__
27#define __INTEL_DISPLAY_TYPES_H__
28
29#include <linux/async.h>
30#include <linux/i2c.h>
31#include <linux/sched/clock.h>
32
33#include <drm/drm_atomic.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_dp_dual_mode_helper.h>
36#include <drm/drm_dp_mst_helper.h>
37#include <drm/drm_encoder.h>
38#include <drm/drm_fb_helper.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_rect.h>
41#include <drm/drm_vblank.h>
42#include <drm/i915_drm.h>
43#include <drm/i915_mei_hdcp_interface.h>
44#include <media/cec-notifier.h>
45
46#include "i915_drv.h"
47
48struct drm_printer;
49
50
51
52
53
54
55
56enum intel_output_type {
57 INTEL_OUTPUT_UNUSED = 0,
58 INTEL_OUTPUT_ANALOG = 1,
59 INTEL_OUTPUT_DVO = 2,
60 INTEL_OUTPUT_SDVO = 3,
61 INTEL_OUTPUT_LVDS = 4,
62 INTEL_OUTPUT_TVOUT = 5,
63 INTEL_OUTPUT_HDMI = 6,
64 INTEL_OUTPUT_DP = 7,
65 INTEL_OUTPUT_EDP = 8,
66 INTEL_OUTPUT_DSI = 9,
67 INTEL_OUTPUT_DDI = 10,
68 INTEL_OUTPUT_DP_MST = 11,
69};
70
71enum hdmi_force_audio {
72 HDMI_AUDIO_OFF_DVI = -2,
73 HDMI_AUDIO_OFF,
74 HDMI_AUDIO_AUTO,
75 HDMI_AUDIO_ON,
76};
77
78
79enum intel_broadcast_rgb {
80 INTEL_BROADCAST_RGB_AUTO,
81 INTEL_BROADCAST_RGB_FULL,
82 INTEL_BROADCAST_RGB_LIMITED,
83};
84
85struct intel_framebuffer {
86 struct drm_framebuffer base;
87 struct intel_frontbuffer *frontbuffer;
88 struct intel_rotation_info rot_info;
89
90
91 struct {
92 unsigned int x, y;
93 } normal[2];
94
95 struct {
96 unsigned int x, y;
97 unsigned int pitch;
98 } rotated[2];
99};
100
101struct intel_fbdev {
102 struct drm_fb_helper helper;
103 struct intel_framebuffer *fb;
104 struct i915_vma *vma;
105 unsigned long vma_flags;
106 async_cookie_t cookie;
107 int preferred_bpp;
108
109
110 bool hpd_suspended : 1;
111
112
113
114 bool hpd_waiting : 1;
115
116
117 struct mutex hpd_lock;
118};
119
120enum intel_hotplug_state {
121 INTEL_HOTPLUG_UNCHANGED,
122 INTEL_HOTPLUG_CHANGED,
123 INTEL_HOTPLUG_RETRY,
124};
125
126struct intel_encoder {
127 struct drm_encoder base;
128
129 enum intel_output_type type;
130 enum port port;
131 u16 cloneable;
132 u8 pipe_mask;
133 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
134 struct intel_connector *connector,
135 bool irq_received);
136 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
137 struct intel_crtc_state *,
138 struct drm_connector_state *);
139 int (*compute_config)(struct intel_encoder *,
140 struct intel_crtc_state *,
141 struct drm_connector_state *);
142 void (*update_prepare)(struct intel_atomic_state *,
143 struct intel_encoder *,
144 struct intel_crtc *);
145 void (*pre_pll_enable)(struct intel_encoder *,
146 const struct intel_crtc_state *,
147 const struct drm_connector_state *);
148 void (*pre_enable)(struct intel_encoder *,
149 const struct intel_crtc_state *,
150 const struct drm_connector_state *);
151 void (*enable)(struct intel_encoder *,
152 const struct intel_crtc_state *,
153 const struct drm_connector_state *);
154 void (*update_complete)(struct intel_atomic_state *,
155 struct intel_encoder *,
156 struct intel_crtc *);
157 void (*disable)(struct intel_encoder *,
158 const struct intel_crtc_state *,
159 const struct drm_connector_state *);
160 void (*post_disable)(struct intel_encoder *,
161 const struct intel_crtc_state *,
162 const struct drm_connector_state *);
163 void (*post_pll_disable)(struct intel_encoder *,
164 const struct intel_crtc_state *,
165 const struct drm_connector_state *);
166 void (*update_pipe)(struct intel_encoder *,
167 const struct intel_crtc_state *,
168 const struct drm_connector_state *);
169
170
171
172 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
173
174
175
176
177 void (*get_config)(struct intel_encoder *,
178 struct intel_crtc_state *pipe_config);
179
180
181
182
183 void (*get_power_domains)(struct intel_encoder *encoder,
184 struct intel_crtc_state *crtc_state);
185
186
187
188
189
190 void (*suspend)(struct intel_encoder *);
191 enum hpd_pin hpd_pin;
192 enum intel_display_power_domain power_domain;
193
194 const struct drm_connector *audio_connector;
195};
196
197struct intel_panel {
198 struct drm_display_mode *fixed_mode;
199 struct drm_display_mode *downclock_mode;
200
201
202 struct {
203 bool present;
204 u32 level;
205 u32 min;
206 u32 max;
207 bool enabled;
208 bool combination_mode;
209 bool active_low_pwm;
210 bool alternate_pwm_increment;
211
212
213 bool util_pin_active_low;
214 u8 controller;
215 struct pwm_device *pwm;
216
217 struct backlight_device *device;
218
219
220 int (*setup)(struct intel_connector *connector, enum pipe pipe);
221 u32 (*get)(struct intel_connector *connector);
222 void (*set)(const struct drm_connector_state *conn_state, u32 level);
223 void (*disable)(const struct drm_connector_state *conn_state);
224 void (*enable)(const struct intel_crtc_state *crtc_state,
225 const struct drm_connector_state *conn_state);
226 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
227 void (*power)(struct intel_connector *, bool enable);
228 } backlight;
229};
230
231struct intel_digital_port;
232
233enum check_link_response {
234 HDCP_LINK_PROTECTED = 0,
235 HDCP_TOPOLOGY_CHANGE,
236 HDCP_LINK_INTEGRITY_FAILURE,
237 HDCP_REAUTH_REQUEST
238};
239
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265
266
267struct intel_hdcp_shim {
268
269 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
270
271
272 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
273
274
275
276
277
278
279
280 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
281 u8 *bstatus);
282
283
284 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
285 bool *repeater_present);
286
287
288 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
289
290
291 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
292 bool *ksv_ready);
293
294
295 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
296 int num_downstream, u8 *ksv_fifo);
297
298
299 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
300 int i, u32 *part);
301
302
303 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
304 bool enable);
305
306
307 bool (*check_link)(struct intel_digital_port *intel_dig_port);
308
309
310 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
311 bool *hdcp_capable);
312
313
314 enum hdcp_wired_protocol protocol;
315
316
317 int (*hdcp_2_2_capable)(struct intel_digital_port *intel_dig_port,
318 bool *capable);
319
320
321 int (*write_2_2_msg)(struct intel_digital_port *intel_dig_port,
322 void *buf, size_t size);
323
324
325 int (*read_2_2_msg)(struct intel_digital_port *intel_dig_port,
326 u8 msg_id, void *buf, size_t size);
327
328
329
330
331
332
333 int (*config_stream_type)(struct intel_digital_port *intel_dig_port,
334 bool is_repeater, u8 type);
335
336
337 int (*check_2_2_link)(struct intel_digital_port *intel_dig_port);
338};
339
340struct intel_hdcp {
341 const struct intel_hdcp_shim *shim;
342
343 struct mutex mutex;
344 u64 value;
345 struct delayed_work check_work;
346 struct work_struct prop_work;
347
348
349 bool hdcp_encrypted;
350
351
352
353 bool hdcp2_supported;
354
355
356 bool hdcp2_encrypted;
357
358
359
360
361
362
363 u8 content_type;
364 struct hdcp_port_data port_data;
365
366 bool is_paired;
367 bool is_repeater;
368
369
370
371
372
373
374 u32 seq_num_v;
375
376
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378
379
380
381
382 u32 seq_num_m;
383
384
385
386
387
388 wait_queue_head_t cp_irq_queue;
389 atomic_t cp_irq_count;
390 int cp_irq_count_cached;
391
392
393
394
395
396
397 enum transcoder cpu_transcoder;
398};
399
400struct intel_connector {
401 struct drm_connector base;
402
403
404
405 struct intel_encoder *encoder;
406
407
408 u32 acpi_device_id;
409
410
411
412 bool (*get_hw_state)(struct intel_connector *);
413
414
415 struct intel_panel panel;
416
417
418 struct edid *edid;
419 struct edid *detect_edid;
420
421
422
423 u8 polled;
424
425 void *port;
426
427 struct intel_dp *mst_port;
428
429
430 struct work_struct modeset_retry_work;
431
432 struct intel_hdcp hdcp;
433};
434
435struct intel_digital_connector_state {
436 struct drm_connector_state base;
437
438 enum hdmi_force_audio force_audio;
439 int broadcast_rgb;
440};
441
442#define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
443
444struct dpll {
445
446 int n;
447 int m1, m2;
448 int p1, p2;
449
450 int dot;
451 int vco;
452 int m;
453 int p;
454};
455
456struct intel_atomic_state {
457 struct drm_atomic_state base;
458
459 intel_wakeref_t wakeref;
460
461 struct {
462
463
464
465
466
467 struct intel_cdclk_state logical;
468
469
470
471
472
473 struct intel_cdclk_state actual;
474
475 int force_min_cdclk;
476 bool force_min_cdclk_changed;
477
478 enum pipe pipe;
479 } cdclk;
480
481 bool dpll_set, modeset;
482
483
484
485
486
487
488
489
490
491 u8 active_pipe_changes;
492
493 u8 active_pipes;
494
495 int min_cdclk[I915_MAX_PIPES];
496
497 u8 min_voltage_level[I915_MAX_PIPES];
498
499 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
500
501
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503
504
505 bool skip_intermediate_wm;
506
507 bool rps_interactive;
508
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514
515 bool global_state_changed;
516
517
518 struct skl_ddb_values wm_results;
519
520 struct i915_sw_fence commit_ready;
521
522 struct llist_node freed;
523};
524
525struct intel_plane_state {
526 struct drm_plane_state base;
527 struct i915_ggtt_view view;
528 struct i915_vma *vma;
529 unsigned long flags;
530#define PLANE_HAS_FENCE BIT(0)
531
532 struct {
533 u32 offset;
534
535
536
537
538
539 u32 stride;
540 int x, y;
541 } color_plane[2];
542
543
544 u32 ctl;
545
546
547 u32 color_ctl;
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566
567 int scaler_id;
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576
577 struct intel_plane *planar_linked_plane;
578
579
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581
582
583
584
585
586
587 u32 planar_slave;
588
589 struct drm_intel_sprite_colorkey ckey;
590};
591
592struct intel_initial_plane_config {
593 struct intel_framebuffer *fb;
594 unsigned int tiling;
595 int size;
596 u32 base;
597 u8 rotation;
598};
599
600struct intel_scaler {
601 int in_use;
602 u32 mode;
603};
604
605struct intel_crtc_scaler_state {
606#define SKL_NUM_SCALERS 2
607 struct intel_scaler scalers[SKL_NUM_SCALERS];
608
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624
625
626#define SKL_CRTC_INDEX 31
627 unsigned scaler_users;
628
629
630 int scaler_id;
631};
632
633
634#define I915_MODE_FLAG_INHERITED (1<<0)
635
636#define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
637
638#define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
639
640struct intel_pipe_wm {
641 struct intel_wm_level wm[5];
642 u32 linetime;
643 bool fbc_wm_enabled;
644 bool pipe_enabled;
645 bool sprites_enabled;
646 bool sprites_scaled;
647};
648
649struct skl_plane_wm {
650 struct skl_wm_level wm[8];
651 struct skl_wm_level uv_wm[8];
652 struct skl_wm_level trans_wm;
653 bool is_planar;
654};
655
656struct skl_pipe_wm {
657 struct skl_plane_wm planes[I915_MAX_PLANES];
658 u32 linetime;
659};
660
661enum vlv_wm_level {
662 VLV_WM_LEVEL_PM2,
663 VLV_WM_LEVEL_PM5,
664 VLV_WM_LEVEL_DDR_DVFS,
665 NUM_VLV_WM_LEVELS,
666};
667
668struct vlv_wm_state {
669 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
670 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
671 u8 num_levels;
672 bool cxsr;
673};
674
675struct vlv_fifo_state {
676 u16 plane[I915_MAX_PLANES];
677};
678
679enum g4x_wm_level {
680 G4X_WM_LEVEL_NORMAL,
681 G4X_WM_LEVEL_SR,
682 G4X_WM_LEVEL_HPLL,
683 NUM_G4X_WM_LEVELS,
684};
685
686struct g4x_wm_state {
687 struct g4x_pipe_wm wm;
688 struct g4x_sr_wm sr;
689 struct g4x_sr_wm hpll;
690 bool cxsr;
691 bool hpll_en;
692 bool fbc_en;
693};
694
695struct intel_crtc_wm_state {
696 union {
697 struct {
698
699
700
701
702
703
704
705 struct intel_pipe_wm intermediate;
706
707
708
709
710
711 struct intel_pipe_wm optimal;
712 } ilk;
713
714 struct {
715
716 struct skl_pipe_wm optimal;
717 struct skl_ddb_entry ddb;
718 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
719 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
720 } skl;
721
722 struct {
723
724 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
725
726 struct vlv_wm_state intermediate;
727
728 struct vlv_wm_state optimal;
729
730 struct vlv_fifo_state fifo_state;
731 } vlv;
732
733 struct {
734
735 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
736
737 struct g4x_wm_state intermediate;
738
739 struct g4x_wm_state optimal;
740 } g4x;
741 };
742
743
744
745
746
747
748
749 bool need_postvbl_update;
750};
751
752enum intel_output_format {
753 INTEL_OUTPUT_FORMAT_INVALID,
754 INTEL_OUTPUT_FORMAT_RGB,
755 INTEL_OUTPUT_FORMAT_YCBCR420,
756 INTEL_OUTPUT_FORMAT_YCBCR444,
757};
758
759struct intel_crtc_state {
760 struct drm_crtc_state base;
761
762
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764
765
766
767
768
769
770#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0)
771 unsigned long quirks;
772
773 unsigned fb_bits;
774 bool update_pipe;
775 bool disable_cxsr;
776 bool update_wm_pre, update_wm_post;
777 bool fifo_changed;
778 bool preload_luts;
779
780
781
782
783 int pipe_src_w, pipe_src_h;
784
785
786
787
788
789 unsigned int pixel_rate;
790
791
792
793 bool has_pch_encoder;
794
795
796 bool has_infoframe;
797
798
799
800
801 enum transcoder cpu_transcoder;
802
803
804
805
806
807 bool limited_color_range;
808
809
810
811
812 unsigned int output_types;
813
814
815 bool has_hdmi_sink;
816
817
818
819 bool has_audio;
820
821
822
823
824
825 bool dither;
826
827
828
829
830
831
832
833 bool dither_force_disable;
834
835
836 bool clock_set;
837
838
839
840 bool sdvo_tv_clock;
841
842
843
844
845
846
847 bool bw_constrained;
848
849
850
851 struct dpll dpll;
852
853
854 struct intel_shared_dpll *shared_dpll;
855
856
857 struct intel_dpll_hw_state dpll_hw_state;
858
859
860
861
862
863 struct icl_port_dpll {
864 struct intel_shared_dpll *pll;
865 struct intel_dpll_hw_state hw_state;
866 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
867
868
869 struct {
870 u32 ctrl, div;
871 } dsi_pll;
872
873 int pipe_bpp;
874 struct intel_link_m_n dp_m_n;
875
876
877 struct intel_link_m_n dp_m2_n2;
878 bool has_drrs;
879
880 bool has_psr;
881 bool has_psr2;
882 u32 dc3co_exitline;
883
884
885
886
887
888
889 int port_clock;
890
891
892 unsigned pixel_multiplier;
893
894 u8 lane_count;
895
896
897
898
899
900 u8 lane_lat_optim_mask;
901
902
903 u8 min_voltage_level;
904
905
906 struct {
907 u32 control;
908 u32 pgm_ratios;
909 u32 lvds_border_bits;
910 } gmch_pfit;
911
912
913 struct {
914 u32 pos;
915 u32 size;
916 bool enabled;
917 bool force_thru;
918 } pch_pfit;
919
920
921 int fdi_lanes;
922 struct intel_link_m_n fdi_m_n;
923
924 bool ips_enabled;
925
926 bool crc_enabled;
927
928 bool enable_fbc;
929
930 bool double_wide;
931
932 int pbn;
933
934 struct intel_crtc_scaler_state scaler_state;
935
936
937 enum pipe hsw_workaround_pipe;
938
939
940 bool disable_lp_wm;
941
942 struct intel_crtc_wm_state wm;
943
944 int min_cdclk[I915_MAX_PLANES];
945
946 u32 data_rate[I915_MAX_PLANES];
947
948
949 u32 gamma_mode;
950
951 union {
952
953 u32 csc_mode;
954
955
956 u32 cgm_mode;
957 };
958
959
960 u8 active_planes;
961 u8 nv12_planes;
962 u8 c8_planes;
963
964
965 u8 update_planes;
966
967 struct {
968 u32 enable;
969 u32 gcp;
970 union hdmi_infoframe avi;
971 union hdmi_infoframe spd;
972 union hdmi_infoframe hdmi;
973 union hdmi_infoframe drm;
974 } infoframes;
975
976
977 bool hdmi_scrambling;
978
979
980 bool hdmi_high_tmds_clock_ratio;
981
982
983 enum intel_output_format output_format;
984
985
986 bool lspcon_downsampling;
987
988
989 bool gamma_enable;
990
991
992 bool csc_enable;
993
994
995 struct {
996 bool compression_enable;
997 bool dsc_split;
998 u16 compressed_bpp;
999 u8 slice_count;
1000 struct drm_dsc_config config;
1001 } dsc;
1002
1003
1004 bool fec_enable;
1005
1006
1007 enum transcoder master_transcoder;
1008
1009
1010 u8 sync_mode_slaves_mask;
1011};
1012
1013struct intel_crtc {
1014 struct drm_crtc base;
1015 enum pipe pipe;
1016
1017
1018
1019
1020
1021 bool active;
1022 u8 plane_ids_mask;
1023 unsigned long long enabled_power_domains;
1024 struct intel_overlay *overlay;
1025
1026 struct intel_crtc_state *config;
1027
1028
1029 bool cpu_fifo_underrun_disabled;
1030 bool pch_fifo_underrun_disabled;
1031
1032
1033 struct {
1034
1035 union {
1036 struct intel_pipe_wm ilk;
1037 struct vlv_wm_state vlv;
1038 struct g4x_wm_state g4x;
1039 } active;
1040 } wm;
1041
1042 int scanline_offset;
1043
1044 struct {
1045 unsigned start_vbl_count;
1046 ktime_t start_vbl_time;
1047 int min_vbl, max_vbl;
1048 int scanline_start;
1049 } debug;
1050
1051
1052 int num_scalers;
1053
1054
1055 struct intel_dsb dsb;
1056};
1057
1058struct intel_plane {
1059 struct drm_plane base;
1060 enum i9xx_plane_id i9xx_plane;
1061 enum plane_id id;
1062 enum pipe pipe;
1063 bool has_fbc;
1064 bool has_ccs;
1065 u32 frontbuffer_bit;
1066
1067 struct {
1068 u32 base, cntl, size;
1069 } cursor;
1070
1071
1072
1073
1074
1075
1076
1077 unsigned int (*max_stride)(struct intel_plane *plane,
1078 u32 pixel_format, u64 modifier,
1079 unsigned int rotation);
1080 void (*update_plane)(struct intel_plane *plane,
1081 const struct intel_crtc_state *crtc_state,
1082 const struct intel_plane_state *plane_state);
1083 void (*update_slave)(struct intel_plane *plane,
1084 const struct intel_crtc_state *crtc_state,
1085 const struct intel_plane_state *plane_state);
1086 void (*disable_plane)(struct intel_plane *plane,
1087 const struct intel_crtc_state *crtc_state);
1088 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1089 int (*check_plane)(struct intel_crtc_state *crtc_state,
1090 struct intel_plane_state *plane_state);
1091 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1092 const struct intel_plane_state *plane_state);
1093};
1094
1095struct intel_watermark_params {
1096 u16 fifo_size;
1097 u16 max_wm;
1098 u8 default_wm;
1099 u8 guard_size;
1100 u8 cacheline_size;
1101};
1102
1103struct cxsr_latency {
1104 bool is_desktop : 1;
1105 bool is_ddr3 : 1;
1106 u16 fsb_freq;
1107 u16 mem_freq;
1108 u16 display_sr;
1109 u16 display_hpll_disable;
1110 u16 cursor_sr;
1111 u16 cursor_hpll_disable;
1112};
1113
1114#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1115#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1116#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1117#define to_intel_connector(x) container_of(x, struct intel_connector, base)
1118#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1119#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1120#define to_intel_plane(x) container_of(x, struct intel_plane, base)
1121#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1122#define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1123
1124struct intel_hdmi {
1125 i915_reg_t hdmi_reg;
1126 int ddc_bus;
1127 struct {
1128 enum drm_dp_dual_mode_type type;
1129 int max_tmds_clock;
1130 } dp_dual_mode;
1131 bool has_hdmi_sink;
1132 bool has_audio;
1133 struct intel_connector *attached_connector;
1134 struct cec_notifier *cec_notifier;
1135};
1136
1137struct intel_dp_mst_encoder;
1138#define DP_MAX_DOWNSTREAM_PORTS 0x10
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154enum link_m_n_set {
1155
1156 M1_N1 = 0,
1157 M2_N2
1158};
1159
1160struct intel_dp_compliance_data {
1161 unsigned long edid;
1162 u8 video_pattern;
1163 u16 hdisplay, vdisplay;
1164 u8 bpc;
1165};
1166
1167struct intel_dp_compliance {
1168 unsigned long test_type;
1169 struct intel_dp_compliance_data test_data;
1170 bool test_active;
1171 int test_link_rate;
1172 u8 test_lane_count;
1173};
1174
1175struct intel_dp {
1176 i915_reg_t output_reg;
1177 u32 DP;
1178 int link_rate;
1179 u8 lane_count;
1180 u8 sink_count;
1181 bool link_mst;
1182 bool link_trained;
1183 bool has_audio;
1184 bool reset_link_params;
1185 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1186 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1187 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1188 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1189 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1190 u8 fec_capable;
1191
1192 int num_source_rates;
1193 const int *source_rates;
1194
1195 int num_sink_rates;
1196 int sink_rates[DP_MAX_SUPPORTED_RATES];
1197 bool use_rate_select;
1198
1199 int num_common_rates;
1200 int common_rates[DP_MAX_SUPPORTED_RATES];
1201
1202 int max_link_lane_count;
1203
1204 int max_link_rate;
1205
1206 struct drm_dp_desc desc;
1207 struct drm_dp_aux aux;
1208 u32 aux_busy_last_status;
1209 u8 train_set[4];
1210 int panel_power_up_delay;
1211 int panel_power_down_delay;
1212 int panel_power_cycle_delay;
1213 int backlight_on_delay;
1214 int backlight_off_delay;
1215 struct delayed_work panel_vdd_work;
1216 bool want_panel_vdd;
1217 unsigned long last_power_on;
1218 unsigned long last_backlight_off;
1219 ktime_t panel_power_off_time;
1220
1221 struct notifier_block edp_notifier;
1222
1223
1224
1225
1226
1227 enum pipe pps_pipe;
1228
1229
1230
1231
1232
1233 enum pipe active_pipe;
1234
1235
1236
1237
1238 bool pps_reset;
1239 struct edp_power_seq pps_delays;
1240
1241 bool can_mst;
1242 bool is_mst;
1243 int active_mst_links;
1244
1245
1246
1247
1248 struct {
1249 i915_reg_t dp_tp_ctl;
1250 i915_reg_t dp_tp_status;
1251 } regs;
1252
1253
1254 struct intel_connector *attached_connector;
1255
1256
1257 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1258 struct drm_dp_mst_topology_mgr mst_mgr;
1259
1260 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1261
1262
1263
1264
1265 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1266 u32 aux_clock_divider);
1267
1268 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1269 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1270
1271
1272 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1273
1274
1275 struct intel_dp_compliance compliance;
1276
1277
1278 bool force_dsc_en;
1279};
1280
1281enum lspcon_vendor {
1282 LSPCON_VENDOR_MCA,
1283 LSPCON_VENDOR_PARADE
1284};
1285
1286struct intel_lspcon {
1287 bool active;
1288 enum drm_lspcon_mode mode;
1289 enum lspcon_vendor vendor;
1290};
1291
1292struct intel_digital_port {
1293 struct intel_encoder base;
1294 u32 saved_port_bits;
1295 struct intel_dp dp;
1296 struct intel_hdmi hdmi;
1297 struct intel_lspcon lspcon;
1298 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1299 bool release_cl2_override;
1300 u8 max_lanes;
1301
1302 enum aux_ch aux_ch;
1303 enum intel_display_power_domain ddi_io_power_domain;
1304 struct mutex tc_lock;
1305 intel_wakeref_t tc_lock_wakeref;
1306 int tc_link_refcount;
1307 bool tc_legacy_port:1;
1308 char tc_port_name[8];
1309 enum tc_port_mode tc_mode;
1310 enum phy_fia tc_phy_fia;
1311 u8 tc_phy_fia_idx;
1312
1313 void (*write_infoframe)(struct intel_encoder *encoder,
1314 const struct intel_crtc_state *crtc_state,
1315 unsigned int type,
1316 const void *frame, ssize_t len);
1317 void (*read_infoframe)(struct intel_encoder *encoder,
1318 const struct intel_crtc_state *crtc_state,
1319 unsigned int type,
1320 void *frame, ssize_t len);
1321 void (*set_infoframes)(struct intel_encoder *encoder,
1322 bool enable,
1323 const struct intel_crtc_state *crtc_state,
1324 const struct drm_connector_state *conn_state);
1325 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1326 const struct intel_crtc_state *pipe_config);
1327};
1328
1329struct intel_dp_mst_encoder {
1330 struct intel_encoder base;
1331 enum pipe pipe;
1332 struct intel_digital_port *primary;
1333 struct intel_connector *connector;
1334};
1335
1336static inline enum dpio_channel
1337vlv_dport_to_channel(struct intel_digital_port *dport)
1338{
1339 switch (dport->base.port) {
1340 case PORT_B:
1341 case PORT_D:
1342 return DPIO_CH0;
1343 case PORT_C:
1344 return DPIO_CH1;
1345 default:
1346 BUG();
1347 }
1348}
1349
1350static inline enum dpio_phy
1351vlv_dport_to_phy(struct intel_digital_port *dport)
1352{
1353 switch (dport->base.port) {
1354 case PORT_B:
1355 case PORT_C:
1356 return DPIO_PHY0;
1357 case PORT_D:
1358 return DPIO_PHY1;
1359 default:
1360 BUG();
1361 }
1362}
1363
1364static inline enum dpio_channel
1365vlv_pipe_to_channel(enum pipe pipe)
1366{
1367 switch (pipe) {
1368 case PIPE_A:
1369 case PIPE_C:
1370 return DPIO_CH0;
1371 case PIPE_B:
1372 return DPIO_CH1;
1373 default:
1374 BUG();
1375 }
1376}
1377
1378static inline struct intel_crtc *
1379intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1380{
1381 return dev_priv->pipe_to_crtc_mapping[pipe];
1382}
1383
1384static inline struct intel_crtc *
1385intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1386{
1387 return dev_priv->plane_to_crtc_mapping[plane];
1388}
1389
1390struct intel_load_detect_pipe {
1391 struct drm_atomic_state *restore_state;
1392};
1393
1394static inline struct intel_encoder *
1395intel_attached_encoder(struct drm_connector *connector)
1396{
1397 return to_intel_connector(connector)->encoder;
1398}
1399
1400static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1401{
1402 switch (encoder->type) {
1403 case INTEL_OUTPUT_DDI:
1404 case INTEL_OUTPUT_DP:
1405 case INTEL_OUTPUT_EDP:
1406 case INTEL_OUTPUT_HDMI:
1407 return true;
1408 default:
1409 return false;
1410 }
1411}
1412
1413static inline struct intel_digital_port *
1414enc_to_dig_port(struct drm_encoder *encoder)
1415{
1416 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1417
1418 if (intel_encoder_is_dig_port(intel_encoder))
1419 return container_of(encoder, struct intel_digital_port,
1420 base.base);
1421 else
1422 return NULL;
1423}
1424
1425static inline struct intel_digital_port *
1426conn_to_dig_port(struct intel_connector *connector)
1427{
1428 return enc_to_dig_port(&intel_attached_encoder(&connector->base)->base);
1429}
1430
1431static inline struct intel_dp_mst_encoder *
1432enc_to_mst(struct drm_encoder *encoder)
1433{
1434 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1435}
1436
1437static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1438{
1439 return &enc_to_dig_port(encoder)->dp;
1440}
1441
1442static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1443{
1444 switch (encoder->type) {
1445 case INTEL_OUTPUT_DP:
1446 case INTEL_OUTPUT_EDP:
1447 return true;
1448 case INTEL_OUTPUT_DDI:
1449
1450 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1451 default:
1452 return false;
1453 }
1454}
1455
1456static inline struct intel_lspcon *
1457enc_to_intel_lspcon(struct drm_encoder *encoder)
1458{
1459 return &enc_to_dig_port(encoder)->lspcon;
1460}
1461
1462static inline struct intel_digital_port *
1463dp_to_dig_port(struct intel_dp *intel_dp)
1464{
1465 return container_of(intel_dp, struct intel_digital_port, dp);
1466}
1467
1468static inline struct intel_lspcon *
1469dp_to_lspcon(struct intel_dp *intel_dp)
1470{
1471 return &dp_to_dig_port(intel_dp)->lspcon;
1472}
1473
1474static inline struct drm_i915_private *
1475dp_to_i915(struct intel_dp *intel_dp)
1476{
1477 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1478}
1479
1480static inline struct intel_digital_port *
1481hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1482{
1483 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1484}
1485
1486static inline struct intel_plane_state *
1487intel_atomic_get_plane_state(struct intel_atomic_state *state,
1488 struct intel_plane *plane)
1489{
1490 struct drm_plane_state *ret =
1491 drm_atomic_get_plane_state(&state->base, &plane->base);
1492
1493 if (IS_ERR(ret))
1494 return ERR_CAST(ret);
1495
1496 return to_intel_plane_state(ret);
1497}
1498
1499static inline struct intel_plane_state *
1500intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1501 struct intel_plane *plane)
1502{
1503 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1504 &plane->base));
1505}
1506
1507static inline struct intel_plane_state *
1508intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1509 struct intel_plane *plane)
1510{
1511 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1512 &plane->base));
1513}
1514
1515static inline struct intel_crtc_state *
1516intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1517 struct intel_crtc *crtc)
1518{
1519 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1520 &crtc->base));
1521}
1522
1523static inline struct intel_crtc_state *
1524intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1525 struct intel_crtc *crtc)
1526{
1527 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1528 &crtc->base));
1529}
1530
1531
1532static inline bool
1533intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1534 enum intel_output_type type)
1535{
1536 return crtc_state->output_types & (1 << type);
1537}
1538static inline bool
1539intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1540{
1541 return crtc_state->output_types &
1542 ((1 << INTEL_OUTPUT_DP) |
1543 (1 << INTEL_OUTPUT_DP_MST) |
1544 (1 << INTEL_OUTPUT_EDP));
1545}
1546static inline void
1547intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1548{
1549 drm_wait_one_vblank(&dev_priv->drm, pipe);
1550}
1551static inline void
1552intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
1553{
1554 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1555
1556 if (crtc->active)
1557 intel_wait_for_vblank(dev_priv, pipe);
1558}
1559
1560static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1561{
1562 return i915_ggtt_offset(state->vma);
1563}
1564
1565#endif
1566