linux/drivers/gpu/drm/i915/i915_gem_fence_reg.h
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   1/*
   2 * Copyright © 2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#ifndef __I915_FENCE_REG_H__
  26#define __I915_FENCE_REG_H__
  27
  28#include <linux/list.h>
  29#include <linux/types.h>
  30
  31struct drm_i915_gem_object;
  32struct i915_ggtt;
  33struct i915_vma;
  34struct intel_gt;
  35struct sg_table;
  36
  37#define I965_FENCE_PAGE 4096UL
  38
  39struct i915_fence_reg {
  40        struct list_head link;
  41        struct i915_ggtt *ggtt;
  42        struct i915_vma *vma;
  43        atomic_t pin_count;
  44        int id;
  45        /**
  46         * Whether the tiling parameters for the currently
  47         * associated fence register have changed. Note that
  48         * for the purposes of tracking tiling changes we also
  49         * treat the unfenced register, the register slot that
  50         * the object occupies whilst it executes a fenced
  51         * command (such as BLT on gen2/3), as a "fence".
  52         */
  53        bool dirty;
  54};
  55
  56/* i915_gem_fence_reg.c */
  57struct i915_fence_reg *i915_reserve_fence(struct i915_ggtt *ggtt);
  58void i915_unreserve_fence(struct i915_fence_reg *fence);
  59
  60void i915_gem_restore_fences(struct i915_ggtt *ggtt);
  61
  62void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
  63                                       struct sg_table *pages);
  64void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
  65                                         struct sg_table *pages);
  66
  67void i915_ggtt_init_fences(struct i915_ggtt *ggtt);
  68
  69void intel_gt_init_swizzling(struct intel_gt *gt);
  70
  71#endif
  72