linux/drivers/i2c/busses/i2c-mxs.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Freescale MXS I2C bus driver
   4 *
   5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
   7 *
   8 * based on a (non-working) driver which was:
   9 *
  10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  11 */
  12
  13#include <linux/slab.h>
  14#include <linux/device.h>
  15#include <linux/module.h>
  16#include <linux/i2c.h>
  17#include <linux/err.h>
  18#include <linux/interrupt.h>
  19#include <linux/completion.h>
  20#include <linux/platform_device.h>
  21#include <linux/jiffies.h>
  22#include <linux/io.h>
  23#include <linux/stmp_device.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/dmaengine.h>
  28
  29#define DRIVER_NAME "mxs-i2c"
  30
  31#define MXS_I2C_CTRL0           (0x00)
  32#define MXS_I2C_CTRL0_SET       (0x04)
  33#define MXS_I2C_CTRL0_CLR       (0x08)
  34
  35#define MXS_I2C_CTRL0_SFTRST                    0x80000000
  36#define MXS_I2C_CTRL0_RUN                       0x20000000
  37#define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  38#define MXS_I2C_CTRL0_PIO_MODE                  0x01000000
  39#define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  40#define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  41#define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  42#define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  43#define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  44#define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  45
  46#define MXS_I2C_TIMING0         (0x10)
  47#define MXS_I2C_TIMING1         (0x20)
  48#define MXS_I2C_TIMING2         (0x30)
  49
  50#define MXS_I2C_CTRL1           (0x40)
  51#define MXS_I2C_CTRL1_SET       (0x44)
  52#define MXS_I2C_CTRL1_CLR       (0x48)
  53
  54#define MXS_I2C_CTRL1_CLR_GOT_A_NAK             0x10000000
  55#define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  56#define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  57#define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  58#define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  59#define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  60#define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  61#define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  62#define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  63
  64#define MXS_I2C_STAT            (0x50)
  65#define MXS_I2C_STAT_GOT_A_NAK                  0x10000000
  66#define MXS_I2C_STAT_BUS_BUSY                   0x00000800
  67#define MXS_I2C_STAT_CLK_GEN_BUSY               0x00000400
  68
  69#define MXS_I2C_DATA(i2c)       ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
  70
  71#define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
  72
  73#define MXS_I2C_DEBUG0_DMAREQ   0x80000000
  74
  75#define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  76                                 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  77                                 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  78                                 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  79                                 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  80                                 MXS_I2C_CTRL1_SLAVE_IRQ)
  81
  82
  83#define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  84                                 MXS_I2C_CTRL0_PRE_SEND_START | \
  85                                 MXS_I2C_CTRL0_MASTER_MODE |    \
  86                                 MXS_I2C_CTRL0_DIRECTION |      \
  87                                 MXS_I2C_CTRL0_XFER_COUNT(1))
  88
  89#define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  90                                 MXS_I2C_CTRL0_MASTER_MODE |    \
  91                                 MXS_I2C_CTRL0_DIRECTION)
  92
  93#define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  94                                 MXS_I2C_CTRL0_MASTER_MODE)
  95
  96enum mxs_i2c_devtype {
  97        MXS_I2C_UNKNOWN = 0,
  98        MXS_I2C_V1,
  99        MXS_I2C_V2,
 100};
 101
 102/**
 103 * struct mxs_i2c_dev - per device, private MXS-I2C data
 104 *
 105 * @dev: driver model device node
 106 * @dev_type: distinguish i.MX23/i.MX28 features
 107 * @regs: IO registers pointer
 108 * @cmd_complete: completion object for transaction wait
 109 * @cmd_err: error code for last transaction
 110 * @adapter: i2c subsystem adapter node
 111 */
 112struct mxs_i2c_dev {
 113        struct device *dev;
 114        enum mxs_i2c_devtype dev_type;
 115        void __iomem *regs;
 116        struct completion cmd_complete;
 117        int cmd_err;
 118        struct i2c_adapter adapter;
 119
 120        uint32_t timing0;
 121        uint32_t timing1;
 122        uint32_t timing2;
 123
 124        /* DMA support components */
 125        struct dma_chan                 *dmach;
 126        uint32_t                        pio_data[2];
 127        uint32_t                        addr_data;
 128        struct scatterlist              sg_io[2];
 129        bool                            dma_read;
 130};
 131
 132static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 133{
 134        int ret = stmp_reset_block(i2c->regs);
 135        if (ret)
 136                return ret;
 137
 138        /*
 139         * Configure timing for the I2C block. The I2C TIMING2 register has to
 140         * be programmed with this particular magic number. The rest is derived
 141         * from the XTAL speed and requested I2C speed.
 142         *
 143         * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
 144         */
 145        writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
 146        writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
 147        writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
 148
 149        writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 150
 151        return 0;
 152}
 153
 154static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
 155{
 156        if (i2c->dma_read) {
 157                dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 158                dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 159        } else {
 160                dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 161        }
 162}
 163
 164static void mxs_i2c_dma_irq_callback(void *param)
 165{
 166        struct mxs_i2c_dev *i2c = param;
 167
 168        complete(&i2c->cmd_complete);
 169        mxs_i2c_dma_finish(i2c);
 170}
 171
 172static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
 173                        struct i2c_msg *msg, uint32_t flags)
 174{
 175        struct dma_async_tx_descriptor *desc;
 176        struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 177
 178        i2c->addr_data = i2c_8bit_addr_from_msg(msg);
 179
 180        if (msg->flags & I2C_M_RD) {
 181                i2c->dma_read = true;
 182
 183                /*
 184                 * SELECT command.
 185                 */
 186
 187                /* Queue the PIO register write transfer. */
 188                i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
 189                desc = dmaengine_prep_slave_sg(i2c->dmach,
 190                                        (struct scatterlist *)&i2c->pio_data[0],
 191                                        1, DMA_TRANS_NONE, 0);
 192                if (!desc) {
 193                        dev_err(i2c->dev,
 194                                "Failed to get PIO reg. write descriptor.\n");
 195                        goto select_init_pio_fail;
 196                }
 197
 198                /* Queue the DMA data transfer. */
 199                sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
 200                dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 201                desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
 202                                        DMA_MEM_TO_DEV,
 203                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 204                if (!desc) {
 205                        dev_err(i2c->dev,
 206                                "Failed to get DMA data write descriptor.\n");
 207                        goto select_init_dma_fail;
 208                }
 209
 210                /*
 211                 * READ command.
 212                 */
 213
 214                /* Queue the PIO register write transfer. */
 215                i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
 216                                MXS_I2C_CTRL0_XFER_COUNT(msg->len);
 217                desc = dmaengine_prep_slave_sg(i2c->dmach,
 218                                        (struct scatterlist *)&i2c->pio_data[1],
 219                                        1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
 220                if (!desc) {
 221                        dev_err(i2c->dev,
 222                                "Failed to get PIO reg. write descriptor.\n");
 223                        goto select_init_dma_fail;
 224                }
 225
 226                /* Queue the DMA data transfer. */
 227                sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
 228                dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 229                desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
 230                                        DMA_DEV_TO_MEM,
 231                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 232                if (!desc) {
 233                        dev_err(i2c->dev,
 234                                "Failed to get DMA data write descriptor.\n");
 235                        goto read_init_dma_fail;
 236                }
 237        } else {
 238                i2c->dma_read = false;
 239
 240                /*
 241                 * WRITE command.
 242                 */
 243
 244                /* Queue the PIO register write transfer. */
 245                i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
 246                                MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
 247                desc = dmaengine_prep_slave_sg(i2c->dmach,
 248                                        (struct scatterlist *)&i2c->pio_data[0],
 249                                        1, DMA_TRANS_NONE, 0);
 250                if (!desc) {
 251                        dev_err(i2c->dev,
 252                                "Failed to get PIO reg. write descriptor.\n");
 253                        goto write_init_pio_fail;
 254                }
 255
 256                /* Queue the DMA data transfer. */
 257                sg_init_table(i2c->sg_io, 2);
 258                sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
 259                sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
 260                dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 261                desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
 262                                        DMA_MEM_TO_DEV,
 263                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 264                if (!desc) {
 265                        dev_err(i2c->dev,
 266                                "Failed to get DMA data write descriptor.\n");
 267                        goto write_init_dma_fail;
 268                }
 269        }
 270
 271        /*
 272         * The last descriptor must have this callback,
 273         * to finish the DMA transaction.
 274         */
 275        desc->callback = mxs_i2c_dma_irq_callback;
 276        desc->callback_param = i2c;
 277
 278        /* Start the transfer. */
 279        dmaengine_submit(desc);
 280        dma_async_issue_pending(i2c->dmach);
 281        return 0;
 282
 283/* Read failpath. */
 284read_init_dma_fail:
 285        dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
 286select_init_dma_fail:
 287        dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
 288select_init_pio_fail:
 289        dmaengine_terminate_all(i2c->dmach);
 290        return -EINVAL;
 291
 292/* Write failpath. */
 293write_init_dma_fail:
 294        dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
 295write_init_pio_fail:
 296        dmaengine_terminate_all(i2c->dmach);
 297        return -EINVAL;
 298}
 299
 300static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
 301{
 302        unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 303
 304        while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
 305                if (readl(i2c->regs + MXS_I2C_CTRL1) &
 306                                MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 307                        return -ENXIO;
 308                if (time_after(jiffies, timeout))
 309                        return -ETIMEDOUT;
 310                cond_resched();
 311        }
 312
 313        return 0;
 314}
 315
 316static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
 317{
 318        u32 state;
 319
 320        state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
 321
 322        if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 323                i2c->cmd_err = -ENXIO;
 324        else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 325                          MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 326                          MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
 327                          MXS_I2C_CTRL1_SLAVE_IRQ))
 328                i2c->cmd_err = -EIO;
 329
 330        return i2c->cmd_err;
 331}
 332
 333static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
 334{
 335        u32 reg;
 336
 337        writel(cmd, i2c->regs + MXS_I2C_CTRL0);
 338
 339        /* readback makes sure the write is latched into hardware */
 340        reg = readl(i2c->regs + MXS_I2C_CTRL0);
 341        reg |= MXS_I2C_CTRL0_RUN;
 342        writel(reg, i2c->regs + MXS_I2C_CTRL0);
 343}
 344
 345/*
 346 * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
 347 * CTRL0::PIO_MODE bit description clarifies the order in which the registers
 348 * must be written during PIO mode operation. First, the CTRL0 register has
 349 * to be programmed with all the necessary bits but the RUN bit. Then the
 350 * payload has to be written into the DATA register. Finally, the transmission
 351 * is executed by setting the RUN bit in CTRL0.
 352 */
 353static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
 354                                          u32 data)
 355{
 356        writel(cmd, i2c->regs + MXS_I2C_CTRL0);
 357
 358        if (i2c->dev_type == MXS_I2C_V1)
 359                writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
 360
 361        writel(data, i2c->regs + MXS_I2C_DATA(i2c));
 362        writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
 363}
 364
 365static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
 366                        struct i2c_msg *msg, uint32_t flags)
 367{
 368        struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 369        uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
 370        uint32_t data = 0;
 371        int i, ret, xlen = 0, xmit = 0;
 372        uint32_t start;
 373
 374        /* Mute IRQs coming from this block. */
 375        writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
 376
 377        /*
 378         * MX23 idea:
 379         * - Enable CTRL0::PIO_MODE (1 << 24)
 380         * - Enable CTRL1::ACK_MODE (1 << 27)
 381         *
 382         * WARNING! The MX23 is broken in some way, even if it claims
 383         * to support PIO, when we try to transfer any amount of data
 384         * that is not aligned to 4 bytes, the DMA engine will have
 385         * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
 386         * transfer. This in turn will mess up the next transfer as
 387         * the block it emit one byte write onto the bus terminated
 388         * with a NAK+STOP. A possible workaround is to reset the IP
 389         * block after every PIO transmission, which might just work.
 390         *
 391         * NOTE: The CTRL0::PIO_MODE description is important, since
 392         * it outlines how the PIO mode is really supposed to work.
 393         */
 394        if (msg->flags & I2C_M_RD) {
 395                /*
 396                 * PIO READ transfer:
 397                 *
 398                 * This transfer MUST be limited to 4 bytes maximum. It is not
 399                 * possible to transfer more than four bytes via PIO, since we
 400                 * can not in any way make sure we can read the data from the
 401                 * DATA register fast enough. Besides, the RX FIFO is only four
 402                 * bytes deep, thus we can only really read up to four bytes at
 403                 * time. Finally, there is no bit indicating us that new data
 404                 * arrived at the FIFO and can thus be fetched from the DATA
 405                 * register.
 406                 */
 407                BUG_ON(msg->len > 4);
 408
 409                /* SELECT command. */
 410                mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
 411                                              addr_data);
 412
 413                ret = mxs_i2c_pio_wait_xfer_end(i2c);
 414                if (ret) {
 415                        dev_dbg(i2c->dev,
 416                                "PIO: Failed to send SELECT command!\n");
 417                        goto cleanup;
 418                }
 419
 420                /* READ command. */
 421                mxs_i2c_pio_trigger_cmd(i2c,
 422                                        MXS_CMD_I2C_READ | flags |
 423                                        MXS_I2C_CTRL0_XFER_COUNT(msg->len));
 424
 425                ret = mxs_i2c_pio_wait_xfer_end(i2c);
 426                if (ret) {
 427                        dev_dbg(i2c->dev,
 428                                "PIO: Failed to send READ command!\n");
 429                        goto cleanup;
 430                }
 431
 432                data = readl(i2c->regs + MXS_I2C_DATA(i2c));
 433                for (i = 0; i < msg->len; i++) {
 434                        msg->buf[i] = data & 0xff;
 435                        data >>= 8;
 436                }
 437        } else {
 438                /*
 439                 * PIO WRITE transfer:
 440                 *
 441                 * The code below implements clock stretching to circumvent
 442                 * the possibility of kernel not being able to supply data
 443                 * fast enough. It is possible to transfer arbitrary amount
 444                 * of data using PIO write.
 445                 */
 446
 447                /*
 448                 * The LSB of data buffer is the first byte blasted across
 449                 * the bus. Higher order bytes follow. Thus the following
 450                 * filling schematic.
 451                 */
 452
 453                data = addr_data << 24;
 454
 455                /* Start the transfer with START condition. */
 456                start = MXS_I2C_CTRL0_PRE_SEND_START;
 457
 458                /* If the transfer is long, use clock stretching. */
 459                if (msg->len > 3)
 460                        start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
 461
 462                for (i = 0; i < msg->len; i++) {
 463                        data >>= 8;
 464                        data |= (msg->buf[i] << 24);
 465
 466                        xmit = 0;
 467
 468                        /* This is the last transfer of the message. */
 469                        if (i + 1 == msg->len) {
 470                                /* Add optional STOP flag. */
 471                                start |= flags;
 472                                /* Remove RETAIN_CLOCK bit. */
 473                                start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
 474                                xmit = 1;
 475                        }
 476
 477                        /* Four bytes are ready in the "data" variable. */
 478                        if ((i & 3) == 2)
 479                                xmit = 1;
 480
 481                        /* Nothing interesting happened, continue stuffing. */
 482                        if (!xmit)
 483                                continue;
 484
 485                        /*
 486                         * Compute the size of the transfer and shift the
 487                         * data accordingly.
 488                         *
 489                         * i = (4k + 0) .... xlen = 2
 490                         * i = (4k + 1) .... xlen = 3
 491                         * i = (4k + 2) .... xlen = 4
 492                         * i = (4k + 3) .... xlen = 1
 493                         */
 494
 495                        if ((i % 4) == 3)
 496                                xlen = 1;
 497                        else
 498                                xlen = (i % 4) + 2;
 499
 500                        data >>= (4 - xlen) * 8;
 501
 502                        dev_dbg(i2c->dev,
 503                                "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
 504                                xlen, i, msg->len,
 505                                start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
 506                                start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
 507                                start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
 508
 509                        writel(MXS_I2C_DEBUG0_DMAREQ,
 510                               i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
 511
 512                        mxs_i2c_pio_trigger_write_cmd(i2c,
 513                                start | MXS_I2C_CTRL0_MASTER_MODE |
 514                                MXS_I2C_CTRL0_DIRECTION |
 515                                MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
 516
 517                        /* The START condition is sent only once. */
 518                        start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
 519
 520                        /* Wait for the end of the transfer. */
 521                        ret = mxs_i2c_pio_wait_xfer_end(i2c);
 522                        if (ret) {
 523                                dev_dbg(i2c->dev,
 524                                        "PIO: Failed to finish WRITE cmd!\n");
 525                                break;
 526                        }
 527
 528                        /* Check NAK here. */
 529                        ret = readl(i2c->regs + MXS_I2C_STAT) &
 530                                    MXS_I2C_STAT_GOT_A_NAK;
 531                        if (ret) {
 532                                ret = -ENXIO;
 533                                goto cleanup;
 534                        }
 535                }
 536        }
 537
 538        /* make sure we capture any occurred error into cmd_err */
 539        ret = mxs_i2c_pio_check_error_state(i2c);
 540
 541cleanup:
 542        /* Clear any dangling IRQs and re-enable interrupts. */
 543        writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
 544        writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 545
 546        /* Clear the PIO_MODE on i.MX23 */
 547        if (i2c->dev_type == MXS_I2C_V1)
 548                writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
 549
 550        return ret;
 551}
 552
 553/*
 554 * Low level master read/write transaction.
 555 */
 556static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 557                                int stop)
 558{
 559        struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 560        int ret;
 561        int flags;
 562        int use_pio = 0;
 563        unsigned long time_left;
 564
 565        flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 566
 567        dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 568                msg->addr, msg->len, msg->flags, stop);
 569
 570        /*
 571         * The MX28 I2C IP block can only do PIO READ for transfer of to up
 572         * 4 bytes of length. The write transfer is not limited as it can use
 573         * clock stretching to avoid FIFO underruns.
 574         */
 575        if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
 576                use_pio = 1;
 577        if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
 578                use_pio = 1;
 579
 580        i2c->cmd_err = 0;
 581        if (use_pio) {
 582                ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
 583                /* No need to reset the block if NAK was received. */
 584                if (ret && (ret != -ENXIO))
 585                        mxs_i2c_reset(i2c);
 586        } else {
 587                reinit_completion(&i2c->cmd_complete);
 588                ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
 589                if (ret)
 590                        return ret;
 591
 592                time_left = wait_for_completion_timeout(&i2c->cmd_complete,
 593                                                msecs_to_jiffies(1000));
 594                if (!time_left)
 595                        goto timeout;
 596
 597                ret = i2c->cmd_err;
 598        }
 599
 600        if (ret == -ENXIO) {
 601                /*
 602                 * If the transfer fails with a NAK from the slave the
 603                 * controller halts until it gets told to return to idle state.
 604                 */
 605                writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
 606                       i2c->regs + MXS_I2C_CTRL1_SET);
 607        }
 608
 609        /*
 610         * WARNING!
 611         * The i.MX23 is strange. After each and every operation, it's I2C IP
 612         * block must be reset, otherwise the IP block will misbehave. This can
 613         * be observed on the bus by the block sending out one single byte onto
 614         * the bus. In case such an error happens, bit 27 will be set in the
 615         * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
 616         * and is marked as "TBD" instead. To reset this bit to a correct state,
 617         * reset the whole block. Since the block reset does not take long, do
 618         * reset the block after every transfer to play safe.
 619         */
 620        if (i2c->dev_type == MXS_I2C_V1)
 621                mxs_i2c_reset(i2c);
 622
 623        dev_dbg(i2c->dev, "Done with err=%d\n", ret);
 624
 625        return ret;
 626
 627timeout:
 628        dev_dbg(i2c->dev, "Timeout!\n");
 629        mxs_i2c_dma_finish(i2c);
 630        ret = mxs_i2c_reset(i2c);
 631        if (ret)
 632                return ret;
 633
 634        return -ETIMEDOUT;
 635}
 636
 637static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 638                        int num)
 639{
 640        int i;
 641        int err;
 642
 643        for (i = 0; i < num; i++) {
 644                err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 645                if (err)
 646                        return err;
 647        }
 648
 649        return num;
 650}
 651
 652static u32 mxs_i2c_func(struct i2c_adapter *adap)
 653{
 654        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 655}
 656
 657static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 658{
 659        struct mxs_i2c_dev *i2c = dev_id;
 660        u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 661
 662        if (!stat)
 663                return IRQ_NONE;
 664
 665        if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 666                i2c->cmd_err = -ENXIO;
 667        else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 668                    MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 669                    MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 670                /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 671                i2c->cmd_err = -EIO;
 672
 673        writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 674
 675        return IRQ_HANDLED;
 676}
 677
 678static const struct i2c_algorithm mxs_i2c_algo = {
 679        .master_xfer = mxs_i2c_xfer,
 680        .functionality = mxs_i2c_func,
 681};
 682
 683static const struct i2c_adapter_quirks mxs_i2c_quirks = {
 684        .flags = I2C_AQ_NO_ZERO_LEN,
 685};
 686
 687static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
 688{
 689        /* The I2C block clock runs at 24MHz */
 690        const uint32_t clk = 24000000;
 691        uint32_t divider;
 692        uint16_t high_count, low_count, rcv_count, xmit_count;
 693        uint32_t bus_free, leadin;
 694        struct device *dev = i2c->dev;
 695
 696        divider = DIV_ROUND_UP(clk, speed);
 697
 698        if (divider < 25) {
 699                /*
 700                 * limit the divider, so that min(low_count, high_count)
 701                 * is >= 1
 702                 */
 703                divider = 25;
 704                dev_warn(dev,
 705                        "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
 706                        speed / 1000, speed % 1000,
 707                        clk / divider / 1000, clk / divider % 1000);
 708        } else if (divider > 1897) {
 709                /*
 710                 * limit the divider, so that max(low_count, high_count)
 711                 * cannot exceed 1023
 712                 */
 713                divider = 1897;
 714                dev_warn(dev,
 715                        "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
 716                        speed / 1000, speed % 1000,
 717                        clk / divider / 1000, clk / divider % 1000);
 718        }
 719
 720        /*
 721         * The I2C spec specifies the following timing data:
 722         *                          standard mode  fast mode Bitfield name
 723         * tLOW (SCL LOW period)     4700 ns        1300 ns
 724         * tHIGH (SCL HIGH period)   4000 ns         600 ns
 725         * tSU;DAT (data setup time)  250 ns         100 ns
 726         * tHD;STA (START hold time) 4000 ns         600 ns
 727         * tBUF (bus free time)      4700 ns        1300 ns
 728         *
 729         * The hardware (of the i.MX28 at least) seems to add 2 additional
 730         * clock cycles to the low_count and 7 cycles to the high_count.
 731         * This is compensated for by subtracting the respective constants
 732         * from the values written to the timing registers.
 733         */
 734        if (speed > 100000) {
 735                /* fast mode */
 736                low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
 737                high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
 738                leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
 739                bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
 740        } else {
 741                /* normal mode */
 742                low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
 743                high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
 744                leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
 745                bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
 746        }
 747        rcv_count = high_count * 3 / 8;
 748        xmit_count = low_count * 3 / 8;
 749
 750        dev_dbg(dev,
 751                "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
 752                speed, clk / divider, divider, low_count, high_count,
 753                xmit_count, rcv_count, leadin, bus_free);
 754
 755        low_count -= 2;
 756        high_count -= 7;
 757        i2c->timing0 = (high_count << 16) | rcv_count;
 758        i2c->timing1 = (low_count << 16) | xmit_count;
 759        i2c->timing2 = (bus_free << 16 | leadin);
 760}
 761
 762static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
 763{
 764        uint32_t speed;
 765        struct device *dev = i2c->dev;
 766        struct device_node *node = dev->of_node;
 767        int ret;
 768
 769        ret = of_property_read_u32(node, "clock-frequency", &speed);
 770        if (ret) {
 771                dev_warn(dev, "No I2C speed selected, using 100kHz\n");
 772                speed = 100000;
 773        }
 774
 775        mxs_i2c_derive_timing(i2c, speed);
 776
 777        return 0;
 778}
 779
 780static const struct platform_device_id mxs_i2c_devtype[] = {
 781        {
 782                .name = "imx23-i2c",
 783                .driver_data = MXS_I2C_V1,
 784        }, {
 785                .name = "imx28-i2c",
 786                .driver_data = MXS_I2C_V2,
 787        }, { /* sentinel */ }
 788};
 789MODULE_DEVICE_TABLE(platform, mxs_i2c_devtype);
 790
 791static const struct of_device_id mxs_i2c_dt_ids[] = {
 792        { .compatible = "fsl,imx23-i2c", .data = &mxs_i2c_devtype[0], },
 793        { .compatible = "fsl,imx28-i2c", .data = &mxs_i2c_devtype[1], },
 794        { /* sentinel */ }
 795};
 796MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
 797
 798static int mxs_i2c_probe(struct platform_device *pdev)
 799{
 800        const struct of_device_id *of_id =
 801                                of_match_device(mxs_i2c_dt_ids, &pdev->dev);
 802        struct device *dev = &pdev->dev;
 803        struct mxs_i2c_dev *i2c;
 804        struct i2c_adapter *adap;
 805        int err, irq;
 806
 807        i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
 808        if (!i2c)
 809                return -ENOMEM;
 810
 811        if (of_id) {
 812                const struct platform_device_id *device_id = of_id->data;
 813                i2c->dev_type = device_id->driver_data;
 814        }
 815
 816        i2c->regs = devm_platform_ioremap_resource(pdev, 0);
 817        if (IS_ERR(i2c->regs))
 818                return PTR_ERR(i2c->regs);
 819
 820        irq = platform_get_irq(pdev, 0);
 821        if (irq < 0)
 822                return irq;
 823
 824        err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 825        if (err)
 826                return err;
 827
 828        i2c->dev = dev;
 829
 830        init_completion(&i2c->cmd_complete);
 831
 832        if (dev->of_node) {
 833                err = mxs_i2c_get_ofdata(i2c);
 834                if (err)
 835                        return err;
 836        }
 837
 838        /* Setup the DMA */
 839        i2c->dmach = dma_request_slave_channel(dev, "rx-tx");
 840        if (!i2c->dmach) {
 841                dev_err(dev, "Failed to request dma\n");
 842                return -ENODEV;
 843        }
 844
 845        platform_set_drvdata(pdev, i2c);
 846
 847        /* Do reset to enforce correct startup after pinmuxing */
 848        err = mxs_i2c_reset(i2c);
 849        if (err)
 850                return err;
 851
 852        adap = &i2c->adapter;
 853        strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 854        adap->owner = THIS_MODULE;
 855        adap->algo = &mxs_i2c_algo;
 856        adap->quirks = &mxs_i2c_quirks;
 857        adap->dev.parent = dev;
 858        adap->nr = pdev->id;
 859        adap->dev.of_node = pdev->dev.of_node;
 860        i2c_set_adapdata(adap, i2c);
 861        err = i2c_add_numbered_adapter(adap);
 862        if (err) {
 863                writel(MXS_I2C_CTRL0_SFTRST,
 864                                i2c->regs + MXS_I2C_CTRL0_SET);
 865                return err;
 866        }
 867
 868        return 0;
 869}
 870
 871static int mxs_i2c_remove(struct platform_device *pdev)
 872{
 873        struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 874
 875        i2c_del_adapter(&i2c->adapter);
 876
 877        if (i2c->dmach)
 878                dma_release_channel(i2c->dmach);
 879
 880        writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 881
 882        return 0;
 883}
 884
 885static struct platform_driver mxs_i2c_driver = {
 886        .driver = {
 887                   .name = DRIVER_NAME,
 888                   .of_match_table = mxs_i2c_dt_ids,
 889                   },
 890        .probe = mxs_i2c_probe,
 891        .remove = mxs_i2c_remove,
 892};
 893
 894static int __init mxs_i2c_init(void)
 895{
 896        return platform_driver_register(&mxs_i2c_driver);
 897}
 898subsys_initcall(mxs_i2c_init);
 899
 900static void __exit mxs_i2c_exit(void)
 901{
 902        platform_driver_unregister(&mxs_i2c_driver);
 903}
 904module_exit(mxs_i2c_exit);
 905
 906MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 907MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
 908MODULE_DESCRIPTION("MXS I2C Bus Driver");
 909MODULE_LICENSE("GPL");
 910MODULE_ALIAS("platform:" DRIVER_NAME);
 911