LXR linux/drivers/i2c/busses/i2c-uniphier-f.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/i2c.h>
   8#include <linux/iopoll.h>
   9#include <linux/interrupt.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/platform_device.h>
  13
  14#define UNIPHIER_FI2C_CR        0x00    /* control register */
  15#define     UNIPHIER_FI2C_CR_MST        BIT(3)  /* master mode */
  16#define     UNIPHIER_FI2C_CR_STA        BIT(2)  /* start condition */
  17#define     UNIPHIER_FI2C_CR_STO        BIT(1)  /* stop condition */
  18#define     UNIPHIER_FI2C_CR_NACK       BIT(0)  /* do not return ACK */
  19#define UNIPHIER_FI2C_DTTX      0x04    /* TX FIFO */
  20#define     UNIPHIER_FI2C_DTTX_CMD      BIT(8)  /* send command (slave addr) */
  21#define     UNIPHIER_FI2C_DTTX_RD       BIT(0)  /* read transaction */
  22#define UNIPHIER_FI2C_DTRX      0x04    /* RX FIFO */
  23#define UNIPHIER_FI2C_SLAD      0x0c    /* slave address */
  24#define UNIPHIER_FI2C_CYC       0x10    /* clock cycle control */
  25#define UNIPHIER_FI2C_LCTL      0x14    /* clock low period control */
  26#define UNIPHIER_FI2C_SSUT      0x18    /* restart/stop setup time control */
  27#define UNIPHIER_FI2C_DSUT      0x1c    /* data setup time control */
  28#define UNIPHIER_FI2C_INT       0x20    /* interrupt status */
  29#define UNIPHIER_FI2C_IE        0x24    /* interrupt enable */
  30#define UNIPHIER_FI2C_IC        0x28    /* interrupt clear */
  31#define     UNIPHIER_FI2C_INT_TE        BIT(9)  /* TX FIFO empty */
  32#define     UNIPHIER_FI2C_INT_RF        BIT(8)  /* RX FIFO full */
  33#define     UNIPHIER_FI2C_INT_TC        BIT(7)  /* send complete (STOP) */
  34#define     UNIPHIER_FI2C_INT_RC        BIT(6)  /* receive complete (STOP) */
  35#define     UNIPHIER_FI2C_INT_TB        BIT(5)  /* sent specified bytes */
  36#define     UNIPHIER_FI2C_INT_RB        BIT(4)  /* received specified bytes */
  37#define     UNIPHIER_FI2C_INT_NA        BIT(2)  /* no ACK */
  38#define     UNIPHIER_FI2C_INT_AL        BIT(1)  /* arbitration lost */
  39#define UNIPHIER_FI2C_SR        0x2c    /* status register */
  40#define     UNIPHIER_FI2C_SR_DB         BIT(12) /* device busy */
  41#define     UNIPHIER_FI2C_SR_STS        BIT(11) /* stop condition detected */
  42#define     UNIPHIER_FI2C_SR_BB         BIT(8)  /* bus busy */
  43#define     UNIPHIER_FI2C_SR_RFF        BIT(3)  /* RX FIFO full */
  44#define     UNIPHIER_FI2C_SR_RNE        BIT(2)  /* RX FIFO not empty */
  45#define     UNIPHIER_FI2C_SR_TNF        BIT(1)  /* TX FIFO not full */
  46#define     UNIPHIER_FI2C_SR_TFE        BIT(0)  /* TX FIFO empty */
  47#define UNIPHIER_FI2C_RST       0x34    /* reset control */
  48#define     UNIPHIER_FI2C_RST_TBRST     BIT(2)  /* clear TX FIFO */
  49#define     UNIPHIER_FI2C_RST_RBRST     BIT(1)  /* clear RX FIFO */
  50#define     UNIPHIER_FI2C_RST_RST       BIT(0)  /* forcible bus reset */
  51#define UNIPHIER_FI2C_BM        0x38    /* bus monitor */
  52#define     UNIPHIER_FI2C_BM_SDAO       BIT(3)  /* output for SDA line */
  53#define     UNIPHIER_FI2C_BM_SDAS       BIT(2)  /* readback of SDA line */
  54#define     UNIPHIER_FI2C_BM_SCLO       BIT(1)  /* output for SCL line */
  55#define     UNIPHIER_FI2C_BM_SCLS       BIT(0)  /* readback of SCL line */
  56#define UNIPHIER_FI2C_NOISE     0x3c    /* noise filter control */
  57#define UNIPHIER_FI2C_TBC       0x40    /* TX byte count setting */
  58#define UNIPHIER_FI2C_RBC       0x44    /* RX byte count setting */
  59#define UNIPHIER_FI2C_TBCM      0x48    /* TX byte count monitor */
  60#define UNIPHIER_FI2C_RBCM      0x4c    /* RX byte count monitor */
  61#define UNIPHIER_FI2C_BRST      0x50    /* bus reset */
  62#define     UNIPHIER_FI2C_BRST_FOEN     BIT(1)  /* normal operation */
  63#define     UNIPHIER_FI2C_BRST_RSCL     BIT(0)  /* release SCL */
  64
  65#define UNIPHIER_FI2C_INT_FAULTS        \
  66                                (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
  67#define UNIPHIER_FI2C_INT_STOP          \
  68                                (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
  69
  70#define UNIPHIER_FI2C_RD                BIT(0)
  71#define UNIPHIER_FI2C_STOP              BIT(1)
  72#define UNIPHIER_FI2C_MANUAL_NACK       BIT(2)
  73#define UNIPHIER_FI2C_BYTE_WISE         BIT(3)
  74#define UNIPHIER_FI2C_DEFER_STOP_COMP   BIT(4)
  75
  76#define UNIPHIER_FI2C_DEFAULT_SPEED     100000
  77#define UNIPHIER_FI2C_MAX_SPEED         400000
  78#define UNIPHIER_FI2C_FIFO_SIZE         8
  79
  80struct uniphier_fi2c_priv {
  81        struct completion comp;
  82        struct i2c_adapter adap;
  83        void __iomem *membase;
  84        struct clk *clk;
  85        unsigned int len;
  86        u8 *buf;
  87        u32 enabled_irqs;
  88        int error;
  89        unsigned int flags;
  90        unsigned int busy_cnt;
  91        unsigned int clk_cycle;
  92        spinlock_t lock;        /* IRQ synchronization */
  93};
  94
  95static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
  96                                      bool first)
  97{
  98        int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
  99
 100        /*
 101         * TX-FIFO stores slave address in it for the first access.
 102         * Decrement the counter.
 103         */
 104        if (first)
 105                fifo_space--;
 106
 107        while (priv->len) {
 108                if (fifo_space-- <= 0)
 109                        break;
 110
 111                writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
 112                priv->len--;
 113        }
 114}
 115
 116static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
 117{
 118        int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
 119                                                1 : UNIPHIER_FI2C_FIFO_SIZE;
 120
 121        while (priv->len) {
 122                if (fifo_left-- <= 0)
 123                        break;
 124
 125                *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
 126                priv->len--;
 127        }
 128}
 129
 130static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
 131{
 132        writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
 133}
 134
 135static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
 136                                     u32 mask)
 137{
 138        writel(mask, priv->membase + UNIPHIER_FI2C_IC);
 139}
 140
 141static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
 142{
 143        priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
 144        uniphier_fi2c_set_irqs(priv);
 145        writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
 146               priv->membase + UNIPHIER_FI2C_CR);
 147}
 148
 149static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
 150{
 151        struct uniphier_fi2c_priv *priv = dev_id;
 152        u32 irq_status;
 153
 154        spin_lock(&priv->lock);
 155
 156        irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
 157        irq_status &= priv->enabled_irqs;
 158
 159        if (irq_status & UNIPHIER_FI2C_INT_STOP)
 160                goto complete;
 161
 162        if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
 163                priv->error = -EAGAIN;
 164                goto complete;
 165        }
 166
 167        if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
 168                priv->error = -ENXIO;
 169                if (priv->flags & UNIPHIER_FI2C_RD) {
 170                        /*
 171                         * work around a hardware bug:
 172                         * The receive-completed interrupt is never set even if
 173                         * STOP condition is detected after the address phase
 174                         * of read transaction fails to get ACK.
 175                         * To avoid time-out error, we issue STOP here,
 176                         * but do not wait for its completion.
 177                         * It should be checked after exiting this handler.
 178                         */
 179                        uniphier_fi2c_stop(priv);
 180                        priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
 181                        goto complete;
 182                }
 183                goto stop;
 184        }
 185
 186        if (irq_status & UNIPHIER_FI2C_INT_TE) {
 187                if (!priv->len)
 188                        goto data_done;
 189
 190                uniphier_fi2c_fill_txfifo(priv, false);
 191                goto handled;
 192        }
 193
 194        if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
 195                uniphier_fi2c_drain_rxfifo(priv);
 196                /*
 197                 * If the number of bytes to read is multiple of the FIFO size
 198                 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
 199                 * earlier than INT_RB. We wait for INT_RB to confirm the
 200                 * completion of the current message.
 201                 */
 202                if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
 203                        goto data_done;
 204
 205                if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
 206                        if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
 207                            !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
 208                                priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
 209                                uniphier_fi2c_set_irqs(priv);
 210                                priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
 211                        }
 212                        if (priv->len <= 1)
 213                                writel(UNIPHIER_FI2C_CR_MST |
 214                                       UNIPHIER_FI2C_CR_NACK,
 215                                       priv->membase + UNIPHIER_FI2C_CR);
 216                }
 217
 218                goto handled;
 219        }
 220
 221        spin_unlock(&priv->lock);
 222
 223        return IRQ_NONE;
 224
 225data_done:
 226        if (priv->flags & UNIPHIER_FI2C_STOP) {
 227stop:
 228                uniphier_fi2c_stop(priv);
 229        } else {
 230complete:
 231                priv->enabled_irqs = 0;
 232                uniphier_fi2c_set_irqs(priv);
 233                complete(&priv->comp);
 234        }
 235
 236handled:
 237        /*
 238         * This controller makes a pause while any bit of the IRQ status is
 239         * asserted. Clear the asserted bit to kick the controller just before
 240         * exiting the handler.
 241         */
 242        uniphier_fi2c_clear_irqs(priv, irq_status);
 243
 244        spin_unlock(&priv->lock);
 245
 246        return IRQ_HANDLED;
 247}
 248
 249static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
 250                                  bool repeat)
 251{
 252        priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
 253        uniphier_fi2c_set_irqs(priv);
 254
 255        /* do not use TX byte counter */
 256        writel(0, priv->membase + UNIPHIER_FI2C_TBC);
 257        /* set slave address */
 258        writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
 259               priv->membase + UNIPHIER_FI2C_DTTX);
 260        /*
 261         * First chunk of data. For a repeated START condition, do not write
 262         * data to the TX fifo here to avoid the timing issue.
 263         */
 264        if (!repeat)
 265                uniphier_fi2c_fill_txfifo(priv, true);
 266}
 267
 268static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
 269{
 270        priv->flags |= UNIPHIER_FI2C_RD;
 271
 272        if (likely(priv->len < 256)) {
 273                /*
 274                 * If possible, use RX byte counter.
 275                 * It can automatically handle NACK for the last byte.
 276                 */
 277                writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
 278                priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
 279                                      UNIPHIER_FI2C_INT_RB;
 280        } else {
 281                /*
 282                 * The byte counter can not count over 256.  In this case,
 283                 * do not use it at all.  Drain data when FIFO gets full,
 284                 * but treat the last portion as a special case.
 285                 */
 286                writel(0, priv->membase + UNIPHIER_FI2C_RBC);
 287                priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
 288                priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
 289        }
 290
 291        uniphier_fi2c_set_irqs(priv);
 292
 293        /* set slave address with RD bit */
 294        writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
 295               priv->membase + UNIPHIER_FI2C_DTTX);
 296}
 297
 298static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
 299{
 300        writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
 301}
 302
 303static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
 304{
 305        writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
 306               priv->membase + UNIPHIER_FI2C_BRST);
 307}
 308
 309static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
 310{
 311        uniphier_fi2c_reset(priv);
 312        i2c_recover_bus(&priv->adap);
 313}
 314
 315static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
 316                                         struct i2c_msg *msg, bool repeat,
 317                                         bool stop)
 318{
 319        struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 320        bool is_read = msg->flags & I2C_M_RD;
 321        unsigned long time_left, flags;
 322
 323        priv->len = msg->len;
 324        priv->buf = msg->buf;
 325        priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
 326        priv->error = 0;
 327        priv->flags = 0;
 328
 329        if (stop)
 330                priv->flags |= UNIPHIER_FI2C_STOP;
 331
 332        reinit_completion(&priv->comp);
 333        uniphier_fi2c_clear_irqs(priv, U32_MAX);
 334        writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
 335               priv->membase + UNIPHIER_FI2C_RST);      /* reset TX/RX FIFO */
 336
 337        spin_lock_irqsave(&priv->lock, flags);
 338
 339        if (is_read)
 340                uniphier_fi2c_rx_init(priv, msg->addr);
 341        else
 342                uniphier_fi2c_tx_init(priv, msg->addr, repeat);
 343
 344        /*
 345         * For a repeated START condition, writing a slave address to the FIFO
 346         * kicks the controller. So, the UNIPHIER_FI2C_CR register should be
 347         * written only for a non-repeated START condition.
 348         */
 349        if (!repeat)
 350                writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
 351                       priv->membase + UNIPHIER_FI2C_CR);
 352
 353        spin_unlock_irqrestore(&priv->lock, flags);
 354
 355        time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
 356
 357        spin_lock_irqsave(&priv->lock, flags);
 358        priv->enabled_irqs = 0;
 359        uniphier_fi2c_set_irqs(priv);
 360        spin_unlock_irqrestore(&priv->lock, flags);
 361
 362        if (!time_left) {
 363                dev_err(&adap->dev, "transaction timeout.\n");
 364                uniphier_fi2c_recover(priv);
 365                return -ETIMEDOUT;
 366        }
 367
 368        if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
 369                u32 status;
 370                int ret;
 371
 372                ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
 373                                         status,
 374                                         (status & UNIPHIER_FI2C_SR_STS) &&
 375                                         !(status & UNIPHIER_FI2C_SR_BB),
 376                                         1, 20);
 377                if (ret) {
 378                        dev_err(&adap->dev,
 379                                "stop condition was not completed.\n");
 380                        uniphier_fi2c_recover(priv);
 381                        return ret;
 382                }
 383        }
 384
 385        return priv->error;
 386}
 387
 388static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
 389{
 390        struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 391
 392        if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
 393                if (priv->busy_cnt++ > 3) {
 394                        /*
 395                         * If bus busy continues too long, it is probably
 396                         * in a wrong state.  Try bus recovery.
 397                         */
 398                        uniphier_fi2c_recover(priv);
 399                        priv->busy_cnt = 0;
 400                }
 401
 402                return -EAGAIN;
 403        }
 404
 405        priv->busy_cnt = 0;
 406        return 0;
 407}
 408
 409static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
 410                                     struct i2c_msg *msgs, int num)
 411{
 412        struct i2c_msg *msg, *emsg = msgs + num;
 413        bool repeat = false;
 414        int ret;
 415
 416        ret = uniphier_fi2c_check_bus_busy(adap);
 417        if (ret)
 418                return ret;
 419
 420        for (msg = msgs; msg < emsg; msg++) {
 421                /* Emit STOP if it is the last message or I2C_M_STOP is set. */
 422                bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
 423
 424                ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
 425                if (ret)
 426                        return ret;
 427
 428                repeat = !stop;
 429        }
 430
 431        return num;
 432}
 433
 434static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
 435{
 436        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 437}
 438
 439static const struct i2c_algorithm uniphier_fi2c_algo = {
 440        .master_xfer = uniphier_fi2c_master_xfer,
 441        .functionality = uniphier_fi2c_functionality,
 442};
 443
 444static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
 445{
 446        struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 447
 448        return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 449                                                        UNIPHIER_FI2C_BM_SCLS);
 450}
 451
 452static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
 453{
 454        struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 455
 456        writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
 457               priv->membase + UNIPHIER_FI2C_BRST);
 458}
 459
 460static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
 461{
 462        struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
 463
 464        return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
 465                                                        UNIPHIER_FI2C_BM_SDAS);
 466}
 467
 468static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
 469{
 470        uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
 471}
 472
 473static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
 474        .recover_bus = i2c_generic_scl_recovery,
 475        .get_scl = uniphier_fi2c_get_scl,
 476        .set_scl = uniphier_fi2c_set_scl,
 477        .get_sda = uniphier_fi2c_get_sda,
 478        .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
 479};
 480
 481static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
 482{
 483        unsigned int cyc = priv->clk_cycle;
 484        u32 tmp;
 485
 486        tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
 487        tmp |= UNIPHIER_FI2C_CR_MST;
 488        writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
 489
 490        uniphier_fi2c_reset(priv);
 491
 492        /*
 493         *  Standard-mode: tLOW + tHIGH = 10 us
 494         *  Fast-mode:     tLOW + tHIGH = 2.5 us
 495         */
 496        writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
 497        /*
 498         *  Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us
 499         *  Fast-mode:     tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us
 500         * "tLow/tHIGH = 5/4" meets both.
 501         */
 502        writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
 503        /*
 504         *  Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us
 505         *  Fast-mode:     tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us
 506         */
 507        writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
 508        /*
 509         *  Standard-mode: tSU;DAT = 250 ns
 510         *  Fast-mode:     tSU;DAT = 100 ns
 511         */
 512        writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
 513
 514        uniphier_fi2c_prepare_operation(priv);
 515}
 516
 517static int uniphier_fi2c_probe(struct platform_device *pdev)
 518{
 519        struct device *dev = &pdev->dev;
 520        struct uniphier_fi2c_priv *priv;
 521        u32 bus_speed;
 522        unsigned long clk_rate;
 523        int irq, ret;
 524
 525        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 526        if (!priv)
 527                return -ENOMEM;
 528
 529        priv->membase = devm_platform_ioremap_resource(pdev, 0);
 530        if (IS_ERR(priv->membase))
 531                return PTR_ERR(priv->membase);
 532
 533        irq = platform_get_irq(pdev, 0);
 534        if (irq < 0) {
 535                dev_err(dev, "failed to get IRQ number\n");
 536                return irq;
 537        }
 538
 539        if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
 540                bus_speed = UNIPHIER_FI2C_DEFAULT_SPEED;
 541
 542        if (!bus_speed || bus_speed > UNIPHIER_FI2C_MAX_SPEED) {
 543                dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
 544                return -EINVAL;
 545        }
 546
 547        priv->clk = devm_clk_get(dev, NULL);
 548        if (IS_ERR(priv->clk)) {
 549                dev_err(dev, "failed to get clock\n");
 550                return PTR_ERR(priv->clk);
 551        }
 552
 553        ret = clk_prepare_enable(priv->clk);
 554        if (ret)
 555                return ret;
 556
 557        clk_rate = clk_get_rate(priv->clk);
 558        if (!clk_rate) {
 559                dev_err(dev, "input clock rate should not be zero\n");
 560                ret = -EINVAL;
 561                goto disable_clk;
 562        }
 563
 564        priv->clk_cycle = clk_rate / bus_speed;
 565        init_completion(&priv->comp);
 566        spin_lock_init(&priv->lock);
 567        priv->adap.owner = THIS_MODULE;
 568        priv->adap.algo = &uniphier_fi2c_algo;
 569        priv->adap.dev.parent = dev;
 570        priv->adap.dev.of_node = dev->of_node;
 571        strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
 572        priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
 573        i2c_set_adapdata(&priv->adap, priv);
 574        platform_set_drvdata(pdev, priv);
 575
 576        uniphier_fi2c_hw_init(priv);
 577
 578        ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
 579                               pdev->name, priv);
 580        if (ret) {
 581                dev_err(dev, "failed to request irq %d\n", irq);
 582                goto disable_clk;
 583        }
 584
 585        ret = i2c_add_adapter(&priv->adap);
 586disable_clk:
 587        if (ret)
 588                clk_disable_unprepare(priv->clk);
 589
 590        return ret;
 591}
 592
 593static int uniphier_fi2c_remove(struct platform_device *pdev)
 594{
 595        struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
 596
 597        i2c_del_adapter(&priv->adap);
 598        clk_disable_unprepare(priv->clk);
 599
 600        return 0;
 601}
 602
 603static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
 604{
 605        struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
 606
 607        clk_disable_unprepare(priv->clk);
 608
 609        return 0;
 610}
 611
 612static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
 613{
 614        struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
 615        int ret;
 616
 617        ret = clk_prepare_enable(priv->clk);
 618        if (ret)
 619                return ret;
 620
 621        uniphier_fi2c_hw_init(priv);
 622
 623        return 0;
 624}
 625
 626static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
 627        SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
 628};
 629
 630static const struct of_device_id uniphier_fi2c_match[] = {
 631        { .compatible = "socionext,uniphier-fi2c" },
 632        { /* sentinel */ }
 633};
 634MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
 635
 636static struct platform_driver uniphier_fi2c_drv = {
 637        .probe  = uniphier_fi2c_probe,
 638        .remove = uniphier_fi2c_remove,
 639        .driver = {
 640                .name  = "uniphier-fi2c",
 641                .of_match_table = uniphier_fi2c_match,
 642                .pm = &uniphier_fi2c_pm_ops,
 643        },
 644};
 645module_platform_driver(uniphier_fi2c_drv);
 646
 647MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 648MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
 649MODULE_LICENSE("GPL");
 650