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7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/interrupt.h>
11#include <linux/delay.h>
12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/clk.h>
16#include <linux/completion.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/regulator/consumer.h>
20#include <linux/of_platform.h>
21#include <linux/err.h>
22
23#include <linux/iio/iio.h>
24#include <linux/iio/buffer.h>
25#include <linux/iio/sysfs.h>
26#include <linux/iio/trigger.h>
27#include <linux/iio/trigger_consumer.h>
28#include <linux/iio/triggered_buffer.h>
29
30
31#define DRIVER_NAME "vf610-adc"
32
33
34#define VF610_REG_ADC_HC0 0x00
35#define VF610_REG_ADC_HC1 0x04
36#define VF610_REG_ADC_HS 0x08
37#define VF610_REG_ADC_R0 0x0c
38#define VF610_REG_ADC_R1 0x10
39#define VF610_REG_ADC_CFG 0x14
40#define VF610_REG_ADC_GC 0x18
41#define VF610_REG_ADC_GS 0x1c
42#define VF610_REG_ADC_CV 0x20
43#define VF610_REG_ADC_OFS 0x24
44#define VF610_REG_ADC_CAL 0x28
45#define VF610_REG_ADC_PCTL 0x30
46
47
48#define VF610_ADC_MODE_BIT8 0x00
49#define VF610_ADC_MODE_BIT10 0x04
50#define VF610_ADC_MODE_BIT12 0x08
51#define VF610_ADC_MODE_MASK 0x0c
52#define VF610_ADC_BUSCLK2_SEL 0x01
53#define VF610_ADC_ALTCLK_SEL 0x02
54#define VF610_ADC_ADACK_SEL 0x03
55#define VF610_ADC_ADCCLK_MASK 0x03
56#define VF610_ADC_CLK_DIV2 0x20
57#define VF610_ADC_CLK_DIV4 0x40
58#define VF610_ADC_CLK_DIV8 0x60
59#define VF610_ADC_CLK_MASK 0x60
60#define VF610_ADC_ADLSMP_LONG 0x10
61#define VF610_ADC_ADSTS_SHORT 0x100
62#define VF610_ADC_ADSTS_NORMAL 0x200
63#define VF610_ADC_ADSTS_LONG 0x300
64#define VF610_ADC_ADSTS_MASK 0x300
65#define VF610_ADC_ADLPC_EN 0x80
66#define VF610_ADC_ADHSC_EN 0x400
67#define VF610_ADC_REFSEL_VALT 0x800
68#define VF610_ADC_REFSEL_VBG 0x1000
69#define VF610_ADC_ADTRG_HARD 0x2000
70#define VF610_ADC_AVGS_8 0x4000
71#define VF610_ADC_AVGS_16 0x8000
72#define VF610_ADC_AVGS_32 0xC000
73#define VF610_ADC_AVGS_MASK 0xC000
74#define VF610_ADC_OVWREN 0x10000
75
76
77#define VF610_ADC_ADACKEN 0x1
78#define VF610_ADC_DMAEN 0x2
79#define VF610_ADC_ACREN 0x4
80#define VF610_ADC_ACFGT 0x8
81#define VF610_ADC_ACFE 0x10
82#define VF610_ADC_AVGEN 0x20
83#define VF610_ADC_ADCON 0x40
84#define VF610_ADC_CAL 0x80
85
86
87#define VF610_ADC_ADCHC(x) ((x) & 0x1F)
88#define VF610_ADC_AIEN (0x1 << 7)
89#define VF610_ADC_CONV_DISABLE 0x1F
90#define VF610_ADC_HS_COCO0 0x1
91#define VF610_ADC_CALF 0x2
92#define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
93
94#define DEFAULT_SAMPLE_TIME 1000
95
96
97#define VF610_VTEMP25_3V0 950
98
99#define VF610_VTEMP25_3V3 867
100
101#define VF610_TEMP_SLOPE_COEFF 1840
102
103enum clk_sel {
104 VF610_ADCIOC_BUSCLK_SET,
105 VF610_ADCIOC_ALTCLK_SET,
106 VF610_ADCIOC_ADACK_SET,
107};
108
109enum vol_ref {
110 VF610_ADCIOC_VR_VREF_SET,
111 VF610_ADCIOC_VR_VALT_SET,
112 VF610_ADCIOC_VR_VBG_SET,
113};
114
115enum average_sel {
116 VF610_ADC_SAMPLE_1,
117 VF610_ADC_SAMPLE_4,
118 VF610_ADC_SAMPLE_8,
119 VF610_ADC_SAMPLE_16,
120 VF610_ADC_SAMPLE_32,
121};
122
123enum conversion_mode_sel {
124 VF610_ADC_CONV_NORMAL,
125 VF610_ADC_CONV_HIGH_SPEED,
126 VF610_ADC_CONV_LOW_POWER,
127};
128
129enum lst_adder_sel {
130 VF610_ADCK_CYCLES_3,
131 VF610_ADCK_CYCLES_5,
132 VF610_ADCK_CYCLES_7,
133 VF610_ADCK_CYCLES_9,
134 VF610_ADCK_CYCLES_13,
135 VF610_ADCK_CYCLES_17,
136 VF610_ADCK_CYCLES_21,
137 VF610_ADCK_CYCLES_25,
138};
139
140struct vf610_adc_feature {
141 enum clk_sel clk_sel;
142 enum vol_ref vol_ref;
143 enum conversion_mode_sel conv_mode;
144
145 int clk_div;
146 int sample_rate;
147 int res_mode;
148 u32 lst_adder_index;
149 u32 default_sample_time;
150
151 bool calibration;
152 bool ovwren;
153};
154
155struct vf610_adc {
156 struct device *dev;
157 void __iomem *regs;
158 struct clk *clk;
159
160 u32 vref_uv;
161 u32 value;
162 struct regulator *vref;
163
164 u32 max_adck_rate[3];
165 struct vf610_adc_feature adc_feature;
166
167 u32 sample_freq_avail[5];
168
169 struct completion completion;
170 u16 buffer[8];
171};
172
173static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
174static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
175
176static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
177{
178 struct vf610_adc_feature *adc_feature = &info->adc_feature;
179 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
180 u32 adck_period, lst_addr_min;
181 int divisor, i;
182
183 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
184
185 if (adck_rate) {
186
187 divisor = ipg_rate / adck_rate;
188 adc_feature->clk_div = 1 << fls(divisor + 1);
189 } else {
190
191 adc_feature->clk_div = 8;
192 }
193
194 adck_rate = ipg_rate / adc_feature->clk_div;
195
196
197
198
199
200 adck_period = NSEC_PER_SEC / adck_rate;
201 lst_addr_min = adc_feature->default_sample_time / adck_period;
202 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
203 if (vf610_lst_adder[i] > lst_addr_min) {
204 adc_feature->lst_adder_index = i;
205 break;
206 }
207 }
208
209
210
211
212
213
214
215
216
217
218
219
220 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
221 info->sample_freq_avail[i] =
222 adck_rate / (6 + vf610_hw_avgs[i] *
223 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
224}
225
226static inline void vf610_adc_cfg_init(struct vf610_adc *info)
227{
228 struct vf610_adc_feature *adc_feature = &info->adc_feature;
229
230
231 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
232 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
233
234 adc_feature->calibration = true;
235 adc_feature->ovwren = true;
236
237 adc_feature->res_mode = 12;
238 adc_feature->sample_rate = 1;
239
240 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
241
242 vf610_adc_calculate_rates(info);
243}
244
245static void vf610_adc_cfg_post_set(struct vf610_adc *info)
246{
247 struct vf610_adc_feature *adc_feature = &info->adc_feature;
248 int cfg_data = 0;
249 int gc_data = 0;
250
251 switch (adc_feature->clk_sel) {
252 case VF610_ADCIOC_ALTCLK_SET:
253 cfg_data |= VF610_ADC_ALTCLK_SEL;
254 break;
255 case VF610_ADCIOC_ADACK_SET:
256 cfg_data |= VF610_ADC_ADACK_SEL;
257 break;
258 default:
259 break;
260 }
261
262
263 cfg_data |= VF610_ADC_ADLPC_EN;
264
265
266 cfg_data |= VF610_ADC_ADHSC_EN;
267
268
269 switch (adc_feature->vol_ref) {
270 case VF610_ADCIOC_VR_VREF_SET:
271 break;
272 case VF610_ADCIOC_VR_VALT_SET:
273 cfg_data |= VF610_ADC_REFSEL_VALT;
274 break;
275 case VF610_ADCIOC_VR_VBG_SET:
276 cfg_data |= VF610_ADC_REFSEL_VBG;
277 break;
278 default:
279 dev_err(info->dev, "error voltage reference\n");
280 }
281
282
283 if (adc_feature->ovwren)
284 cfg_data |= VF610_ADC_OVWREN;
285
286 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
287 writel(gc_data, info->regs + VF610_REG_ADC_GC);
288}
289
290static void vf610_adc_calibration(struct vf610_adc *info)
291{
292 int adc_gc, hc_cfg;
293
294 if (!info->adc_feature.calibration)
295 return;
296
297
298 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
299 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
300
301 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
302 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
303
304 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
305 dev_err(info->dev, "Timeout for adc calibration\n");
306
307 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
308 if (adc_gc & VF610_ADC_CALF)
309 dev_err(info->dev, "ADC calibration failed\n");
310
311 info->adc_feature.calibration = false;
312}
313
314static void vf610_adc_cfg_set(struct vf610_adc *info)
315{
316 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
317 int cfg_data;
318
319 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
320
321 cfg_data &= ~VF610_ADC_ADLPC_EN;
322 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
323 cfg_data |= VF610_ADC_ADLPC_EN;
324
325 cfg_data &= ~VF610_ADC_ADHSC_EN;
326 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
327 cfg_data |= VF610_ADC_ADHSC_EN;
328
329 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
330}
331
332static void vf610_adc_sample_set(struct vf610_adc *info)
333{
334 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
335 int cfg_data, gc_data;
336
337 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
338 gc_data = readl(info->regs + VF610_REG_ADC_GC);
339
340
341 cfg_data &= ~VF610_ADC_MODE_MASK;
342 switch (adc_feature->res_mode) {
343 case 8:
344 cfg_data |= VF610_ADC_MODE_BIT8;
345 break;
346 case 10:
347 cfg_data |= VF610_ADC_MODE_BIT10;
348 break;
349 case 12:
350 cfg_data |= VF610_ADC_MODE_BIT12;
351 break;
352 default:
353 dev_err(info->dev, "error resolution mode\n");
354 break;
355 }
356
357
358 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
359 switch (adc_feature->clk_div) {
360 case 1:
361 break;
362 case 2:
363 cfg_data |= VF610_ADC_CLK_DIV2;
364 break;
365 case 4:
366 cfg_data |= VF610_ADC_CLK_DIV4;
367 break;
368 case 8:
369 cfg_data |= VF610_ADC_CLK_DIV8;
370 break;
371 case 16:
372 switch (adc_feature->clk_sel) {
373 case VF610_ADCIOC_BUSCLK_SET:
374 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
375 break;
376 default:
377 dev_err(info->dev, "error clk divider\n");
378 break;
379 }
380 break;
381 }
382
383
384
385
386
387 switch (adc_feature->lst_adder_index) {
388 case VF610_ADCK_CYCLES_3:
389 break;
390 case VF610_ADCK_CYCLES_5:
391 cfg_data |= VF610_ADC_ADSTS_SHORT;
392 break;
393 case VF610_ADCK_CYCLES_7:
394 cfg_data |= VF610_ADC_ADSTS_NORMAL;
395 break;
396 case VF610_ADCK_CYCLES_9:
397 cfg_data |= VF610_ADC_ADSTS_LONG;
398 break;
399 case VF610_ADCK_CYCLES_13:
400 cfg_data |= VF610_ADC_ADLSMP_LONG;
401 break;
402 case VF610_ADCK_CYCLES_17:
403 cfg_data |= VF610_ADC_ADLSMP_LONG;
404 cfg_data |= VF610_ADC_ADSTS_SHORT;
405 break;
406 case VF610_ADCK_CYCLES_21:
407 cfg_data |= VF610_ADC_ADLSMP_LONG;
408 cfg_data |= VF610_ADC_ADSTS_NORMAL;
409 break;
410 case VF610_ADCK_CYCLES_25:
411 cfg_data |= VF610_ADC_ADLSMP_LONG;
412 cfg_data |= VF610_ADC_ADSTS_NORMAL;
413 break;
414 default:
415 dev_err(info->dev, "error in sample time select\n");
416 }
417
418
419 cfg_data &= ~VF610_ADC_AVGS_MASK;
420 gc_data &= ~VF610_ADC_AVGEN;
421 switch (adc_feature->sample_rate) {
422 case VF610_ADC_SAMPLE_1:
423 break;
424 case VF610_ADC_SAMPLE_4:
425 gc_data |= VF610_ADC_AVGEN;
426 break;
427 case VF610_ADC_SAMPLE_8:
428 gc_data |= VF610_ADC_AVGEN;
429 cfg_data |= VF610_ADC_AVGS_8;
430 break;
431 case VF610_ADC_SAMPLE_16:
432 gc_data |= VF610_ADC_AVGEN;
433 cfg_data |= VF610_ADC_AVGS_16;
434 break;
435 case VF610_ADC_SAMPLE_32:
436 gc_data |= VF610_ADC_AVGEN;
437 cfg_data |= VF610_ADC_AVGS_32;
438 break;
439 default:
440 dev_err(info->dev,
441 "error hardware sample average select\n");
442 }
443
444 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
445 writel(gc_data, info->regs + VF610_REG_ADC_GC);
446}
447
448static void vf610_adc_hw_init(struct vf610_adc *info)
449{
450
451 vf610_adc_cfg_post_set(info);
452 vf610_adc_sample_set(info);
453
454
455 vf610_adc_calibration(info);
456
457
458 vf610_adc_cfg_set(info);
459}
460
461static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
462 const struct iio_chan_spec *chan,
463 unsigned int mode)
464{
465 struct vf610_adc *info = iio_priv(indio_dev);
466
467 mutex_lock(&indio_dev->mlock);
468 info->adc_feature.conv_mode = mode;
469 vf610_adc_calculate_rates(info);
470 vf610_adc_hw_init(info);
471 mutex_unlock(&indio_dev->mlock);
472
473 return 0;
474}
475
476static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
477 const struct iio_chan_spec *chan)
478{
479 struct vf610_adc *info = iio_priv(indio_dev);
480
481 return info->adc_feature.conv_mode;
482}
483
484static const char * const vf610_conv_modes[] = { "normal", "high-speed",
485 "low-power" };
486
487static const struct iio_enum vf610_conversion_mode = {
488 .items = vf610_conv_modes,
489 .num_items = ARRAY_SIZE(vf610_conv_modes),
490 .get = vf610_get_conversion_mode,
491 .set = vf610_set_conversion_mode,
492};
493
494static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
495 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
496 {},
497};
498
499#define VF610_ADC_CHAN(_idx, _chan_type) { \
500 .type = (_chan_type), \
501 .indexed = 1, \
502 .channel = (_idx), \
503 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
504 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
505 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
506 .ext_info = vf610_ext_info, \
507 .scan_index = (_idx), \
508 .scan_type = { \
509 .sign = 'u', \
510 .realbits = 12, \
511 .storagebits = 16, \
512 }, \
513}
514
515#define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
516 .type = (_chan_type), \
517 .channel = (_idx), \
518 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
519 .scan_index = (_idx), \
520 .scan_type = { \
521 .sign = 'u', \
522 .realbits = 12, \
523 .storagebits = 16, \
524 }, \
525}
526
527static const struct iio_chan_spec vf610_adc_iio_channels[] = {
528 VF610_ADC_CHAN(0, IIO_VOLTAGE),
529 VF610_ADC_CHAN(1, IIO_VOLTAGE),
530 VF610_ADC_CHAN(2, IIO_VOLTAGE),
531 VF610_ADC_CHAN(3, IIO_VOLTAGE),
532 VF610_ADC_CHAN(4, IIO_VOLTAGE),
533 VF610_ADC_CHAN(5, IIO_VOLTAGE),
534 VF610_ADC_CHAN(6, IIO_VOLTAGE),
535 VF610_ADC_CHAN(7, IIO_VOLTAGE),
536 VF610_ADC_CHAN(8, IIO_VOLTAGE),
537 VF610_ADC_CHAN(9, IIO_VOLTAGE),
538 VF610_ADC_CHAN(10, IIO_VOLTAGE),
539 VF610_ADC_CHAN(11, IIO_VOLTAGE),
540 VF610_ADC_CHAN(12, IIO_VOLTAGE),
541 VF610_ADC_CHAN(13, IIO_VOLTAGE),
542 VF610_ADC_CHAN(14, IIO_VOLTAGE),
543 VF610_ADC_CHAN(15, IIO_VOLTAGE),
544 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
545 IIO_CHAN_SOFT_TIMESTAMP(32),
546
547};
548
549static int vf610_adc_read_data(struct vf610_adc *info)
550{
551 int result;
552
553 result = readl(info->regs + VF610_REG_ADC_R0);
554
555 switch (info->adc_feature.res_mode) {
556 case 8:
557 result &= 0xFF;
558 break;
559 case 10:
560 result &= 0x3FF;
561 break;
562 case 12:
563 result &= 0xFFF;
564 break;
565 default:
566 break;
567 }
568
569 return result;
570}
571
572static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
573{
574 struct iio_dev *indio_dev = dev_id;
575 struct vf610_adc *info = iio_priv(indio_dev);
576 int coco;
577
578 coco = readl(info->regs + VF610_REG_ADC_HS);
579 if (coco & VF610_ADC_HS_COCO0) {
580 info->value = vf610_adc_read_data(info);
581 if (iio_buffer_enabled(indio_dev)) {
582 info->buffer[0] = info->value;
583 iio_push_to_buffers_with_timestamp(indio_dev,
584 info->buffer,
585 iio_get_time_ns(indio_dev));
586 iio_trigger_notify_done(indio_dev->trig);
587 } else
588 complete(&info->completion);
589 }
590
591 return IRQ_HANDLED;
592}
593
594static ssize_t vf610_show_samp_freq_avail(struct device *dev,
595 struct device_attribute *attr, char *buf)
596{
597 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
598 size_t len = 0;
599 int i;
600
601 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
602 len += scnprintf(buf + len, PAGE_SIZE - len,
603 "%u ", info->sample_freq_avail[i]);
604
605
606 buf[len - 1] = '\n';
607
608 return len;
609}
610
611static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
612
613static struct attribute *vf610_attributes[] = {
614 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
615 NULL
616};
617
618static const struct attribute_group vf610_attribute_group = {
619 .attrs = vf610_attributes,
620};
621
622static int vf610_read_raw(struct iio_dev *indio_dev,
623 struct iio_chan_spec const *chan,
624 int *val,
625 int *val2,
626 long mask)
627{
628 struct vf610_adc *info = iio_priv(indio_dev);
629 unsigned int hc_cfg;
630 long ret;
631
632 switch (mask) {
633 case IIO_CHAN_INFO_RAW:
634 case IIO_CHAN_INFO_PROCESSED:
635 mutex_lock(&indio_dev->mlock);
636 if (iio_buffer_enabled(indio_dev)) {
637 mutex_unlock(&indio_dev->mlock);
638 return -EBUSY;
639 }
640
641 reinit_completion(&info->completion);
642 hc_cfg = VF610_ADC_ADCHC(chan->channel);
643 hc_cfg |= VF610_ADC_AIEN;
644 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
645 ret = wait_for_completion_interruptible_timeout
646 (&info->completion, VF610_ADC_TIMEOUT);
647 if (ret == 0) {
648 mutex_unlock(&indio_dev->mlock);
649 return -ETIMEDOUT;
650 }
651 if (ret < 0) {
652 mutex_unlock(&indio_dev->mlock);
653 return ret;
654 }
655
656 switch (chan->type) {
657 case IIO_VOLTAGE:
658 *val = info->value;
659 break;
660 case IIO_TEMP:
661
662
663
664
665
666 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
667 1000000 / VF610_TEMP_SLOPE_COEFF;
668
669 break;
670 default:
671 mutex_unlock(&indio_dev->mlock);
672 return -EINVAL;
673 }
674
675 mutex_unlock(&indio_dev->mlock);
676 return IIO_VAL_INT;
677
678 case IIO_CHAN_INFO_SCALE:
679 *val = info->vref_uv / 1000;
680 *val2 = info->adc_feature.res_mode;
681 return IIO_VAL_FRACTIONAL_LOG2;
682
683 case IIO_CHAN_INFO_SAMP_FREQ:
684 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
685 *val2 = 0;
686 return IIO_VAL_INT;
687
688 default:
689 break;
690 }
691
692 return -EINVAL;
693}
694
695static int vf610_write_raw(struct iio_dev *indio_dev,
696 struct iio_chan_spec const *chan,
697 int val,
698 int val2,
699 long mask)
700{
701 struct vf610_adc *info = iio_priv(indio_dev);
702 int i;
703
704 switch (mask) {
705 case IIO_CHAN_INFO_SAMP_FREQ:
706 for (i = 0;
707 i < ARRAY_SIZE(info->sample_freq_avail);
708 i++)
709 if (val == info->sample_freq_avail[i]) {
710 info->adc_feature.sample_rate = i;
711 vf610_adc_sample_set(info);
712 return 0;
713 }
714 break;
715
716 default:
717 break;
718 }
719
720 return -EINVAL;
721}
722
723static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
724{
725 struct vf610_adc *info = iio_priv(indio_dev);
726 unsigned int channel;
727 int ret;
728 int val;
729
730 ret = iio_triggered_buffer_postenable(indio_dev);
731 if (ret)
732 return ret;
733
734 val = readl(info->regs + VF610_REG_ADC_GC);
735 val |= VF610_ADC_ADCON;
736 writel(val, info->regs + VF610_REG_ADC_GC);
737
738 channel = find_first_bit(indio_dev->active_scan_mask,
739 indio_dev->masklength);
740
741 val = VF610_ADC_ADCHC(channel);
742 val |= VF610_ADC_AIEN;
743
744 writel(val, info->regs + VF610_REG_ADC_HC0);
745
746 return 0;
747}
748
749static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
750{
751 struct vf610_adc *info = iio_priv(indio_dev);
752 unsigned int hc_cfg = 0;
753 int val;
754
755 val = readl(info->regs + VF610_REG_ADC_GC);
756 val &= ~VF610_ADC_ADCON;
757 writel(val, info->regs + VF610_REG_ADC_GC);
758
759 hc_cfg |= VF610_ADC_CONV_DISABLE;
760 hc_cfg &= ~VF610_ADC_AIEN;
761
762 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
763
764 return iio_triggered_buffer_predisable(indio_dev);
765}
766
767static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
768 .postenable = &vf610_adc_buffer_postenable,
769 .predisable = &vf610_adc_buffer_predisable,
770 .validate_scan_mask = &iio_validate_scan_mask_onehot,
771};
772
773static int vf610_adc_reg_access(struct iio_dev *indio_dev,
774 unsigned reg, unsigned writeval,
775 unsigned *readval)
776{
777 struct vf610_adc *info = iio_priv(indio_dev);
778
779 if ((readval == NULL) ||
780 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
781 return -EINVAL;
782
783 *readval = readl(info->regs + reg);
784
785 return 0;
786}
787
788static const struct iio_info vf610_adc_iio_info = {
789 .read_raw = &vf610_read_raw,
790 .write_raw = &vf610_write_raw,
791 .debugfs_reg_access = &vf610_adc_reg_access,
792 .attrs = &vf610_attribute_group,
793};
794
795static const struct of_device_id vf610_adc_match[] = {
796 { .compatible = "fsl,vf610-adc", },
797 { }
798};
799MODULE_DEVICE_TABLE(of, vf610_adc_match);
800
801static int vf610_adc_probe(struct platform_device *pdev)
802{
803 struct vf610_adc *info;
804 struct iio_dev *indio_dev;
805 int irq;
806 int ret;
807
808 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
809 if (!indio_dev) {
810 dev_err(&pdev->dev, "Failed allocating iio device\n");
811 return -ENOMEM;
812 }
813
814 info = iio_priv(indio_dev);
815 info->dev = &pdev->dev;
816
817 info->regs = devm_platform_ioremap_resource(pdev, 0);
818 if (IS_ERR(info->regs))
819 return PTR_ERR(info->regs);
820
821 irq = platform_get_irq(pdev, 0);
822 if (irq < 0)
823 return irq;
824
825 ret = devm_request_irq(info->dev, irq,
826 vf610_adc_isr, 0,
827 dev_name(&pdev->dev), indio_dev);
828 if (ret < 0) {
829 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
830 return ret;
831 }
832
833 info->clk = devm_clk_get(&pdev->dev, "adc");
834 if (IS_ERR(info->clk)) {
835 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
836 PTR_ERR(info->clk));
837 return PTR_ERR(info->clk);
838 }
839
840 info->vref = devm_regulator_get(&pdev->dev, "vref");
841 if (IS_ERR(info->vref))
842 return PTR_ERR(info->vref);
843
844 ret = regulator_enable(info->vref);
845 if (ret)
846 return ret;
847
848 info->vref_uv = regulator_get_voltage(info->vref);
849
850 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
851 info->max_adck_rate, 3);
852
853 ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
854 &info->adc_feature.default_sample_time);
855 if (ret)
856 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
857
858 platform_set_drvdata(pdev, indio_dev);
859
860 init_completion(&info->completion);
861
862 indio_dev->name = dev_name(&pdev->dev);
863 indio_dev->dev.parent = &pdev->dev;
864 indio_dev->dev.of_node = pdev->dev.of_node;
865 indio_dev->info = &vf610_adc_iio_info;
866 indio_dev->modes = INDIO_DIRECT_MODE;
867 indio_dev->channels = vf610_adc_iio_channels;
868 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
869
870 ret = clk_prepare_enable(info->clk);
871 if (ret) {
872 dev_err(&pdev->dev,
873 "Could not prepare or enable the clock.\n");
874 goto error_adc_clk_enable;
875 }
876
877 vf610_adc_cfg_init(info);
878 vf610_adc_hw_init(info);
879
880 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
881 NULL, &iio_triggered_buffer_setup_ops);
882 if (ret < 0) {
883 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
884 goto error_iio_device_register;
885 }
886
887 ret = iio_device_register(indio_dev);
888 if (ret) {
889 dev_err(&pdev->dev, "Couldn't register the device.\n");
890 goto error_adc_buffer_init;
891 }
892
893 return 0;
894
895error_adc_buffer_init:
896 iio_triggered_buffer_cleanup(indio_dev);
897error_iio_device_register:
898 clk_disable_unprepare(info->clk);
899error_adc_clk_enable:
900 regulator_disable(info->vref);
901
902 return ret;
903}
904
905static int vf610_adc_remove(struct platform_device *pdev)
906{
907 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
908 struct vf610_adc *info = iio_priv(indio_dev);
909
910 iio_device_unregister(indio_dev);
911 iio_triggered_buffer_cleanup(indio_dev);
912 regulator_disable(info->vref);
913 clk_disable_unprepare(info->clk);
914
915 return 0;
916}
917
918#ifdef CONFIG_PM_SLEEP
919static int vf610_adc_suspend(struct device *dev)
920{
921 struct iio_dev *indio_dev = dev_get_drvdata(dev);
922 struct vf610_adc *info = iio_priv(indio_dev);
923 int hc_cfg;
924
925
926 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
927 hc_cfg |= VF610_ADC_CONV_DISABLE;
928 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
929
930 clk_disable_unprepare(info->clk);
931 regulator_disable(info->vref);
932
933 return 0;
934}
935
936static int vf610_adc_resume(struct device *dev)
937{
938 struct iio_dev *indio_dev = dev_get_drvdata(dev);
939 struct vf610_adc *info = iio_priv(indio_dev);
940 int ret;
941
942 ret = regulator_enable(info->vref);
943 if (ret)
944 return ret;
945
946 ret = clk_prepare_enable(info->clk);
947 if (ret)
948 goto disable_reg;
949
950 vf610_adc_hw_init(info);
951
952 return 0;
953
954disable_reg:
955 regulator_disable(info->vref);
956 return ret;
957}
958#endif
959
960static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
961
962static struct platform_driver vf610_adc_driver = {
963 .probe = vf610_adc_probe,
964 .remove = vf610_adc_remove,
965 .driver = {
966 .name = DRIVER_NAME,
967 .of_match_table = vf610_adc_match,
968 .pm = &vf610_adc_pm_ops,
969 },
970};
971
972module_platform_driver(vf610_adc_driver);
973
974MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
975MODULE_DESCRIPTION("Freescale VF610 ADC driver");
976MODULE_LICENSE("GPL v2");
977
