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10#include <linux/bitfield.h>
11#include <linux/delay.h>
12#include <linux/iio/iio.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17
18#include "stm32-dac-core.h"
19
20#define STM32_DAC_CHANNEL_1 1
21#define STM32_DAC_CHANNEL_2 2
22#define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1)
23
24#define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000
25
26
27
28
29
30struct stm32_dac {
31 struct stm32_dac_common *common;
32};
33
34static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
35{
36 struct stm32_dac *dac = iio_priv(indio_dev);
37 u32 en, val;
38 int ret;
39
40 ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
41 if (ret < 0)
42 return ret;
43 if (STM32_DAC_IS_CHAN_1(channel))
44 en = FIELD_GET(STM32_DAC_CR_EN1, val);
45 else
46 en = FIELD_GET(STM32_DAC_CR_EN2, val);
47
48 return !!en;
49}
50
51static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
52 bool enable)
53{
54 struct stm32_dac *dac = iio_priv(indio_dev);
55 struct device *dev = indio_dev->dev.parent;
56 u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
57 u32 en = enable ? msk : 0;
58 int ret;
59
60
61 mutex_lock(&indio_dev->mlock);
62 ret = stm32_dac_is_enabled(indio_dev, ch);
63 if (ret < 0 || enable == !!ret) {
64 mutex_unlock(&indio_dev->mlock);
65 return ret < 0 ? ret : 0;
66 }
67
68 if (enable) {
69 ret = pm_runtime_get_sync(dev);
70 if (ret < 0) {
71 pm_runtime_put_noidle(dev);
72 mutex_unlock(&indio_dev->mlock);
73 return ret;
74 }
75 }
76
77 ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
78 mutex_unlock(&indio_dev->mlock);
79 if (ret < 0) {
80 dev_err(&indio_dev->dev, "%s failed\n", en ?
81 "Enable" : "Disable");
82 goto err_put_pm;
83 }
84
85
86
87
88
89
90 if (en && dac->common->hfsel)
91 udelay(1);
92
93 if (!enable) {
94 pm_runtime_mark_last_busy(dev);
95 pm_runtime_put_autosuspend(dev);
96 }
97
98 return 0;
99
100err_put_pm:
101 if (enable) {
102 pm_runtime_mark_last_busy(dev);
103 pm_runtime_put_autosuspend(dev);
104 }
105
106 return ret;
107}
108
109static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
110{
111 int ret;
112
113 if (STM32_DAC_IS_CHAN_1(channel))
114 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
115 else
116 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
117
118 return ret ? ret : IIO_VAL_INT;
119}
120
121static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
122{
123 int ret;
124
125 if (STM32_DAC_IS_CHAN_1(channel))
126 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
127 else
128 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
129
130 return ret;
131}
132
133static int stm32_dac_read_raw(struct iio_dev *indio_dev,
134 struct iio_chan_spec const *chan,
135 int *val, int *val2, long mask)
136{
137 struct stm32_dac *dac = iio_priv(indio_dev);
138
139 switch (mask) {
140 case IIO_CHAN_INFO_RAW:
141 return stm32_dac_get_value(dac, chan->channel, val);
142 case IIO_CHAN_INFO_SCALE:
143 *val = dac->common->vref_mv;
144 *val2 = chan->scan_type.realbits;
145 return IIO_VAL_FRACTIONAL_LOG2;
146 default:
147 return -EINVAL;
148 }
149}
150
151static int stm32_dac_write_raw(struct iio_dev *indio_dev,
152 struct iio_chan_spec const *chan,
153 int val, int val2, long mask)
154{
155 struct stm32_dac *dac = iio_priv(indio_dev);
156
157 switch (mask) {
158 case IIO_CHAN_INFO_RAW:
159 return stm32_dac_set_value(dac, chan->channel, val);
160 default:
161 return -EINVAL;
162 }
163}
164
165static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
166 unsigned reg, unsigned writeval,
167 unsigned *readval)
168{
169 struct stm32_dac *dac = iio_priv(indio_dev);
170
171 if (!readval)
172 return regmap_write(dac->common->regmap, reg, writeval);
173 else
174 return regmap_read(dac->common->regmap, reg, readval);
175}
176
177static const struct iio_info stm32_dac_iio_info = {
178 .read_raw = stm32_dac_read_raw,
179 .write_raw = stm32_dac_write_raw,
180 .debugfs_reg_access = stm32_dac_debugfs_reg_access,
181};
182
183static const char * const stm32_dac_powerdown_modes[] = {
184 "three_state",
185};
186
187static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
188 const struct iio_chan_spec *chan)
189{
190 return 0;
191}
192
193static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
194 const struct iio_chan_spec *chan,
195 unsigned int type)
196{
197 return 0;
198}
199
200static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
201 uintptr_t private,
202 const struct iio_chan_spec *chan,
203 char *buf)
204{
205 int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
206
207 if (ret < 0)
208 return ret;
209
210 return sprintf(buf, "%d\n", ret ? 0 : 1);
211}
212
213static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
214 uintptr_t private,
215 const struct iio_chan_spec *chan,
216 const char *buf, size_t len)
217{
218 bool powerdown;
219 int ret;
220
221 ret = strtobool(buf, &powerdown);
222 if (ret)
223 return ret;
224
225 ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
226 if (ret)
227 return ret;
228
229 return len;
230}
231
232static const struct iio_enum stm32_dac_powerdown_mode_en = {
233 .items = stm32_dac_powerdown_modes,
234 .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
235 .get = stm32_dac_get_powerdown_mode,
236 .set = stm32_dac_set_powerdown_mode,
237};
238
239static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
240 {
241 .name = "powerdown",
242 .read = stm32_dac_read_powerdown,
243 .write = stm32_dac_write_powerdown,
244 .shared = IIO_SEPARATE,
245 },
246 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
247 IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
248 {},
249};
250
251#define STM32_DAC_CHANNEL(chan, name) { \
252 .type = IIO_VOLTAGE, \
253 .indexed = 1, \
254 .output = 1, \
255 .channel = chan, \
256 .info_mask_separate = \
257 BIT(IIO_CHAN_INFO_RAW) | \
258 BIT(IIO_CHAN_INFO_SCALE), \
259 \
260 .scan_type = { \
261 .sign = 'u', \
262 .realbits = 12, \
263 .storagebits = 16, \
264 }, \
265 .datasheet_name = name, \
266 .ext_info = stm32_dac_ext_info \
267}
268
269static const struct iio_chan_spec stm32_dac_channels[] = {
270 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
271 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
272};
273
274static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
275{
276 struct device_node *np = indio_dev->dev.of_node;
277 unsigned int i;
278 u32 channel;
279 int ret;
280
281 ret = of_property_read_u32(np, "reg", &channel);
282 if (ret) {
283 dev_err(&indio_dev->dev, "Failed to read reg property\n");
284 return ret;
285 }
286
287 for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
288 if (stm32_dac_channels[i].channel == channel)
289 break;
290 }
291 if (i >= ARRAY_SIZE(stm32_dac_channels)) {
292 dev_err(&indio_dev->dev, "Invalid reg property\n");
293 return -EINVAL;
294 }
295
296 indio_dev->channels = &stm32_dac_channels[i];
297
298
299
300
301
302 indio_dev->num_channels = 1;
303
304 return 0;
305};
306
307static int stm32_dac_probe(struct platform_device *pdev)
308{
309 struct device_node *np = pdev->dev.of_node;
310 struct device *dev = &pdev->dev;
311 struct iio_dev *indio_dev;
312 struct stm32_dac *dac;
313 int ret;
314
315 if (!np)
316 return -ENODEV;
317
318 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
319 if (!indio_dev)
320 return -ENOMEM;
321 platform_set_drvdata(pdev, indio_dev);
322
323 dac = iio_priv(indio_dev);
324 dac->common = dev_get_drvdata(pdev->dev.parent);
325 indio_dev->name = dev_name(&pdev->dev);
326 indio_dev->dev.parent = &pdev->dev;
327 indio_dev->dev.of_node = pdev->dev.of_node;
328 indio_dev->info = &stm32_dac_iio_info;
329 indio_dev->modes = INDIO_DIRECT_MODE;
330
331 ret = stm32_dac_chan_of_init(indio_dev);
332 if (ret < 0)
333 return ret;
334
335
336 pm_runtime_get_noresume(dev);
337 pm_runtime_set_active(dev);
338 pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
339 pm_runtime_use_autosuspend(dev);
340 pm_runtime_enable(dev);
341
342 ret = iio_device_register(indio_dev);
343 if (ret)
344 goto err_pm_put;
345
346 pm_runtime_mark_last_busy(dev);
347 pm_runtime_put_autosuspend(dev);
348
349 return 0;
350
351err_pm_put:
352 pm_runtime_disable(dev);
353 pm_runtime_set_suspended(dev);
354 pm_runtime_put_noidle(dev);
355
356 return ret;
357}
358
359static int stm32_dac_remove(struct platform_device *pdev)
360{
361 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
362
363 pm_runtime_get_sync(&pdev->dev);
364 iio_device_unregister(indio_dev);
365 pm_runtime_disable(&pdev->dev);
366 pm_runtime_set_suspended(&pdev->dev);
367 pm_runtime_put_noidle(&pdev->dev);
368
369 return 0;
370}
371
372static int __maybe_unused stm32_dac_suspend(struct device *dev)
373{
374 struct iio_dev *indio_dev = dev_get_drvdata(dev);
375 int channel = indio_dev->channels[0].channel;
376 int ret;
377
378
379 ret = stm32_dac_is_enabled(indio_dev, channel);
380 if (ret)
381 return ret < 0 ? ret : -EBUSY;
382
383 return pm_runtime_force_suspend(dev);
384}
385
386static const struct dev_pm_ops stm32_dac_pm_ops = {
387 SET_SYSTEM_SLEEP_PM_OPS(stm32_dac_suspend, pm_runtime_force_resume)
388};
389
390static const struct of_device_id stm32_dac_of_match[] = {
391 { .compatible = "st,stm32-dac", },
392 {},
393};
394MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
395
396static struct platform_driver stm32_dac_driver = {
397 .probe = stm32_dac_probe,
398 .remove = stm32_dac_remove,
399 .driver = {
400 .name = "stm32-dac",
401 .of_match_table = stm32_dac_of_match,
402 .pm = &stm32_dac_pm_ops,
403 },
404};
405module_platform_driver(stm32_dac_driver);
406
407MODULE_ALIAS("platform:stm32-dac");
408MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
409MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
410MODULE_LICENSE("GPL v2");
411
