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48#include <linux/kernel.h>
49#include <linux/module.h>
50#include <linux/delay.h>
51#include <linux/iio/events.h>
52#include <linux/iio/iio.h>
53#include <linux/iio/sysfs.h>
54#include <linux/interrupt.h>
55#include <linux/irq.h>
56#include <linux/pm.h>
57#include <linux/regmap.h>
58#include <linux/bitfield.h>
59
60#include <linux/platform_data/st_sensors_pdata.h>
61
62#include "st_lsm6dsx.h"
63
64#define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
65
66#define ST_LSM6DSX_TS_SENSITIVITY 25000UL
67
68static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = {
69 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0),
70 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1),
71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2),
72 IIO_CHAN_SOFT_TIMESTAMP(3),
73};
74
75static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = {
76 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0),
77 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1),
78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2),
79 IIO_CHAN_SOFT_TIMESTAMP(3),
80};
81
82static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = {
83 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0),
84 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1),
85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2),
86 IIO_CHAN_SOFT_TIMESTAMP(3),
87};
88
89static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
90 {
91 .wai = 0x68,
92 .reset = {
93 .addr = 0x22,
94 .mask = BIT(0),
95 },
96 .boot = {
97 .addr = 0x22,
98 .mask = BIT(7),
99 },
100 .bdu = {
101 .addr = 0x22,
102 .mask = BIT(6),
103 },
104 .max_fifo_size = 32,
105 .id = {
106 {
107 .hw_id = ST_LSM9DS1_ID,
108 .name = ST_LSM9DS1_DEV_NAME,
109 }, {
110 .hw_id = ST_LSM6DS0_ID,
111 .name = ST_LSM6DS0_DEV_NAME,
112 },
113 },
114 .channels = {
115 [ST_LSM6DSX_ID_ACC] = {
116 .chan = st_lsm6dsx_acc_channels,
117 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
118 },
119 [ST_LSM6DSX_ID_GYRO] = {
120 .chan = st_lsm6ds0_gyro_channels,
121 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels),
122 },
123 },
124 .odr_table = {
125 [ST_LSM6DSX_ID_ACC] = {
126 .reg = {
127 .addr = 0x20,
128 .mask = GENMASK(7, 5),
129 },
130 .odr_avl[0] = { 10000, 0x01 },
131 .odr_avl[1] = { 50000, 0x02 },
132 .odr_avl[2] = { 119000, 0x03 },
133 .odr_avl[3] = { 238000, 0x04 },
134 .odr_avl[4] = { 476000, 0x05 },
135 .odr_avl[5] = { 952000, 0x06 },
136 .odr_len = 6,
137 },
138 [ST_LSM6DSX_ID_GYRO] = {
139 .reg = {
140 .addr = 0x10,
141 .mask = GENMASK(7, 5),
142 },
143 .odr_avl[0] = { 14900, 0x01 },
144 .odr_avl[1] = { 59500, 0x02 },
145 .odr_avl[2] = { 119000, 0x03 },
146 .odr_avl[3] = { 238000, 0x04 },
147 .odr_avl[4] = { 476000, 0x05 },
148 .odr_avl[5] = { 952000, 0x06 },
149 .odr_len = 6,
150 },
151 },
152 .fs_table = {
153 [ST_LSM6DSX_ID_ACC] = {
154 .reg = {
155 .addr = 0x20,
156 .mask = GENMASK(4, 3),
157 },
158 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
159 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
160 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
161 .fs_avl[3] = { IIO_G_TO_M_S_2(732), 0x1 },
162 .fs_len = 4,
163 },
164 [ST_LSM6DSX_ID_GYRO] = {
165 .reg = {
166 .addr = 0x10,
167 .mask = GENMASK(4, 3),
168 },
169
170 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
171 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
172 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
173 .fs_len = 3,
174 },
175 },
176 .irq_config = {
177 .irq1 = {
178 .addr = 0x0c,
179 .mask = BIT(3),
180 },
181 .irq2 = {
182 .addr = 0x0d,
183 .mask = BIT(3),
184 },
185 .hla = {
186 .addr = 0x22,
187 .mask = BIT(5),
188 },
189 .od = {
190 .addr = 0x22,
191 .mask = BIT(4),
192 },
193 },
194 },
195 {
196 .wai = 0x69,
197 .reset = {
198 .addr = 0x12,
199 .mask = BIT(0),
200 },
201 .boot = {
202 .addr = 0x12,
203 .mask = BIT(7),
204 },
205 .bdu = {
206 .addr = 0x12,
207 .mask = BIT(6),
208 },
209 .max_fifo_size = 1365,
210 .id = {
211 {
212 .hw_id = ST_LSM6DS3_ID,
213 .name = ST_LSM6DS3_DEV_NAME,
214 },
215 },
216 .channels = {
217 [ST_LSM6DSX_ID_ACC] = {
218 .chan = st_lsm6dsx_acc_channels,
219 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
220 },
221 [ST_LSM6DSX_ID_GYRO] = {
222 .chan = st_lsm6dsx_gyro_channels,
223 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
224 },
225 },
226 .odr_table = {
227 [ST_LSM6DSX_ID_ACC] = {
228 .reg = {
229 .addr = 0x10,
230 .mask = GENMASK(7, 4),
231 },
232 .odr_avl[0] = { 12500, 0x01 },
233 .odr_avl[1] = { 26000, 0x02 },
234 .odr_avl[2] = { 52000, 0x03 },
235 .odr_avl[3] = { 104000, 0x04 },
236 .odr_avl[4] = { 208000, 0x05 },
237 .odr_avl[5] = { 416000, 0x06 },
238 .odr_len = 6,
239 },
240 [ST_LSM6DSX_ID_GYRO] = {
241 .reg = {
242 .addr = 0x11,
243 .mask = GENMASK(7, 4),
244 },
245 .odr_avl[0] = { 12500, 0x01 },
246 .odr_avl[1] = { 26000, 0x02 },
247 .odr_avl[2] = { 52000, 0x03 },
248 .odr_avl[3] = { 104000, 0x04 },
249 .odr_avl[4] = { 208000, 0x05 },
250 .odr_avl[5] = { 416000, 0x06 },
251 .odr_len = 6,
252 },
253 },
254 .fs_table = {
255 [ST_LSM6DSX_ID_ACC] = {
256 .reg = {
257 .addr = 0x10,
258 .mask = GENMASK(3, 2),
259 },
260 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
261 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
262 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
263 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
264 .fs_len = 4,
265 },
266 [ST_LSM6DSX_ID_GYRO] = {
267 .reg = {
268 .addr = 0x11,
269 .mask = GENMASK(3, 2),
270 },
271 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
272 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
273 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
274 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
275 .fs_len = 4,
276 },
277 },
278 .irq_config = {
279 .irq1 = {
280 .addr = 0x0d,
281 .mask = BIT(3),
282 },
283 .irq2 = {
284 .addr = 0x0e,
285 .mask = BIT(3),
286 },
287 .lir = {
288 .addr = 0x58,
289 .mask = BIT(0),
290 },
291 .irq1_func = {
292 .addr = 0x5e,
293 .mask = BIT(5),
294 },
295 .irq2_func = {
296 .addr = 0x5f,
297 .mask = BIT(5),
298 },
299 .hla = {
300 .addr = 0x12,
301 .mask = BIT(5),
302 },
303 .od = {
304 .addr = 0x12,
305 .mask = BIT(4),
306 },
307 },
308 .decimator = {
309 [ST_LSM6DSX_ID_ACC] = {
310 .addr = 0x08,
311 .mask = GENMASK(2, 0),
312 },
313 [ST_LSM6DSX_ID_GYRO] = {
314 .addr = 0x08,
315 .mask = GENMASK(5, 3),
316 },
317 },
318 .fifo_ops = {
319 .update_fifo = st_lsm6dsx_update_fifo,
320 .read_fifo = st_lsm6dsx_read_fifo,
321 .fifo_th = {
322 .addr = 0x06,
323 .mask = GENMASK(11, 0),
324 },
325 .fifo_diff = {
326 .addr = 0x3a,
327 .mask = GENMASK(11, 0),
328 },
329 .th_wl = 3,
330 },
331 .ts_settings = {
332 .timer_en = {
333 .addr = 0x58,
334 .mask = BIT(7),
335 },
336 .hr_timer = {
337 .addr = 0x5c,
338 .mask = BIT(4),
339 },
340 .fifo_en = {
341 .addr = 0x07,
342 .mask = BIT(7),
343 },
344 .decimator = {
345 .addr = 0x09,
346 .mask = GENMASK(5, 3),
347 },
348 },
349 .event_settings = {
350 .wakeup_reg = {
351 .addr = 0x5B,
352 .mask = GENMASK(5, 0),
353 },
354 .wakeup_src_reg = 0x1b,
355 .wakeup_src_status_mask = BIT(3),
356 .wakeup_src_z_mask = BIT(0),
357 .wakeup_src_y_mask = BIT(1),
358 .wakeup_src_x_mask = BIT(2),
359 },
360 },
361 {
362 .wai = 0x69,
363 .reset = {
364 .addr = 0x12,
365 .mask = BIT(0),
366 },
367 .boot = {
368 .addr = 0x12,
369 .mask = BIT(7),
370 },
371 .bdu = {
372 .addr = 0x12,
373 .mask = BIT(6),
374 },
375 .max_fifo_size = 682,
376 .id = {
377 {
378 .hw_id = ST_LSM6DS3H_ID,
379 .name = ST_LSM6DS3H_DEV_NAME,
380 },
381 },
382 .channels = {
383 [ST_LSM6DSX_ID_ACC] = {
384 .chan = st_lsm6dsx_acc_channels,
385 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
386 },
387 [ST_LSM6DSX_ID_GYRO] = {
388 .chan = st_lsm6dsx_gyro_channels,
389 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
390 },
391 },
392 .odr_table = {
393 [ST_LSM6DSX_ID_ACC] = {
394 .reg = {
395 .addr = 0x10,
396 .mask = GENMASK(7, 4),
397 },
398 .odr_avl[0] = { 12500, 0x01 },
399 .odr_avl[1] = { 26000, 0x02 },
400 .odr_avl[2] = { 52000, 0x03 },
401 .odr_avl[3] = { 104000, 0x04 },
402 .odr_avl[4] = { 208000, 0x05 },
403 .odr_avl[5] = { 416000, 0x06 },
404 .odr_len = 6,
405 },
406 [ST_LSM6DSX_ID_GYRO] = {
407 .reg = {
408 .addr = 0x11,
409 .mask = GENMASK(7, 4),
410 },
411 .odr_avl[0] = { 12500, 0x01 },
412 .odr_avl[1] = { 26000, 0x02 },
413 .odr_avl[2] = { 52000, 0x03 },
414 .odr_avl[3] = { 104000, 0x04 },
415 .odr_avl[4] = { 208000, 0x05 },
416 .odr_avl[5] = { 416000, 0x06 },
417 .odr_len = 6,
418 },
419 },
420 .fs_table = {
421 [ST_LSM6DSX_ID_ACC] = {
422 .reg = {
423 .addr = 0x10,
424 .mask = GENMASK(3, 2),
425 },
426 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
427 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
428 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
429 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
430 .fs_len = 4,
431 },
432 [ST_LSM6DSX_ID_GYRO] = {
433 .reg = {
434 .addr = 0x11,
435 .mask = GENMASK(3, 2),
436 },
437 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
438 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
439 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
440 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
441 .fs_len = 4,
442 },
443 },
444 .irq_config = {
445 .irq1 = {
446 .addr = 0x0d,
447 .mask = BIT(3),
448 },
449 .irq2 = {
450 .addr = 0x0e,
451 .mask = BIT(3),
452 },
453 .lir = {
454 .addr = 0x58,
455 .mask = BIT(0),
456 },
457 .irq1_func = {
458 .addr = 0x5e,
459 .mask = BIT(5),
460 },
461 .irq2_func = {
462 .addr = 0x5f,
463 .mask = BIT(5),
464 },
465 .hla = {
466 .addr = 0x12,
467 .mask = BIT(5),
468 },
469 .od = {
470 .addr = 0x12,
471 .mask = BIT(4),
472 },
473 },
474 .decimator = {
475 [ST_LSM6DSX_ID_ACC] = {
476 .addr = 0x08,
477 .mask = GENMASK(2, 0),
478 },
479 [ST_LSM6DSX_ID_GYRO] = {
480 .addr = 0x08,
481 .mask = GENMASK(5, 3),
482 },
483 },
484 .fifo_ops = {
485 .update_fifo = st_lsm6dsx_update_fifo,
486 .read_fifo = st_lsm6dsx_read_fifo,
487 .fifo_th = {
488 .addr = 0x06,
489 .mask = GENMASK(11, 0),
490 },
491 .fifo_diff = {
492 .addr = 0x3a,
493 .mask = GENMASK(11, 0),
494 },
495 .th_wl = 3,
496 },
497 .ts_settings = {
498 .timer_en = {
499 .addr = 0x58,
500 .mask = BIT(7),
501 },
502 .hr_timer = {
503 .addr = 0x5c,
504 .mask = BIT(4),
505 },
506 .fifo_en = {
507 .addr = 0x07,
508 .mask = BIT(7),
509 },
510 .decimator = {
511 .addr = 0x09,
512 .mask = GENMASK(5, 3),
513 },
514 },
515 .event_settings = {
516 .wakeup_reg = {
517 .addr = 0x5B,
518 .mask = GENMASK(5, 0),
519 },
520 .wakeup_src_reg = 0x1b,
521 .wakeup_src_status_mask = BIT(3),
522 .wakeup_src_z_mask = BIT(0),
523 .wakeup_src_y_mask = BIT(1),
524 .wakeup_src_x_mask = BIT(2),
525 },
526 },
527 {
528 .wai = 0x6a,
529 .reset = {
530 .addr = 0x12,
531 .mask = BIT(0),
532 },
533 .boot = {
534 .addr = 0x12,
535 .mask = BIT(7),
536 },
537 .bdu = {
538 .addr = 0x12,
539 .mask = BIT(6),
540 },
541 .max_fifo_size = 682,
542 .id = {
543 {
544 .hw_id = ST_LSM6DSL_ID,
545 .name = ST_LSM6DSL_DEV_NAME,
546 }, {
547 .hw_id = ST_LSM6DSM_ID,
548 .name = ST_LSM6DSM_DEV_NAME,
549 }, {
550 .hw_id = ST_ISM330DLC_ID,
551 .name = ST_ISM330DLC_DEV_NAME,
552 }, {
553 .hw_id = ST_LSM6DS3TRC_ID,
554 .name = ST_LSM6DS3TRC_DEV_NAME,
555 },
556 },
557 .channels = {
558 [ST_LSM6DSX_ID_ACC] = {
559 .chan = st_lsm6dsx_acc_channels,
560 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
561 },
562 [ST_LSM6DSX_ID_GYRO] = {
563 .chan = st_lsm6dsx_gyro_channels,
564 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
565 },
566 },
567 .odr_table = {
568 [ST_LSM6DSX_ID_ACC] = {
569 .reg = {
570 .addr = 0x10,
571 .mask = GENMASK(7, 4),
572 },
573 .odr_avl[0] = { 12500, 0x01 },
574 .odr_avl[1] = { 26000, 0x02 },
575 .odr_avl[2] = { 52000, 0x03 },
576 .odr_avl[3] = { 104000, 0x04 },
577 .odr_avl[4] = { 208000, 0x05 },
578 .odr_avl[5] = { 416000, 0x06 },
579 .odr_len = 6,
580 },
581 [ST_LSM6DSX_ID_GYRO] = {
582 .reg = {
583 .addr = 0x11,
584 .mask = GENMASK(7, 4),
585 },
586 .odr_avl[0] = { 12500, 0x01 },
587 .odr_avl[1] = { 26000, 0x02 },
588 .odr_avl[2] = { 52000, 0x03 },
589 .odr_avl[3] = { 104000, 0x04 },
590 .odr_avl[4] = { 208000, 0x05 },
591 .odr_avl[5] = { 416000, 0x06 },
592 .odr_len = 6,
593 },
594 },
595 .fs_table = {
596 [ST_LSM6DSX_ID_ACC] = {
597 .reg = {
598 .addr = 0x10,
599 .mask = GENMASK(3, 2),
600 },
601 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
602 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
603 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
604 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
605 .fs_len = 4,
606 },
607 [ST_LSM6DSX_ID_GYRO] = {
608 .reg = {
609 .addr = 0x11,
610 .mask = GENMASK(3, 2),
611 },
612 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
613 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
614 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
615 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
616 .fs_len = 4,
617 },
618 },
619 .irq_config = {
620 .irq1 = {
621 .addr = 0x0d,
622 .mask = BIT(3),
623 },
624 .irq2 = {
625 .addr = 0x0e,
626 .mask = BIT(3),
627 },
628 .lir = {
629 .addr = 0x58,
630 .mask = BIT(0),
631 },
632 .irq1_func = {
633 .addr = 0x5e,
634 .mask = BIT(5),
635 },
636 .irq2_func = {
637 .addr = 0x5f,
638 .mask = BIT(5),
639 },
640 .hla = {
641 .addr = 0x12,
642 .mask = BIT(5),
643 },
644 .od = {
645 .addr = 0x12,
646 .mask = BIT(4),
647 },
648 },
649 .decimator = {
650 [ST_LSM6DSX_ID_ACC] = {
651 .addr = 0x08,
652 .mask = GENMASK(2, 0),
653 },
654 [ST_LSM6DSX_ID_GYRO] = {
655 .addr = 0x08,
656 .mask = GENMASK(5, 3),
657 },
658 },
659 .fifo_ops = {
660 .update_fifo = st_lsm6dsx_update_fifo,
661 .read_fifo = st_lsm6dsx_read_fifo,
662 .fifo_th = {
663 .addr = 0x06,
664 .mask = GENMASK(10, 0),
665 },
666 .fifo_diff = {
667 .addr = 0x3a,
668 .mask = GENMASK(10, 0),
669 },
670 .th_wl = 3,
671 },
672 .ts_settings = {
673 .timer_en = {
674 .addr = 0x19,
675 .mask = BIT(5),
676 },
677 .hr_timer = {
678 .addr = 0x5c,
679 .mask = BIT(4),
680 },
681 .fifo_en = {
682 .addr = 0x07,
683 .mask = BIT(7),
684 },
685 .decimator = {
686 .addr = 0x09,
687 .mask = GENMASK(5, 3),
688 },
689 },
690 .event_settings = {
691 .enable_reg = {
692 .addr = 0x58,
693 .mask = BIT(7),
694 },
695 .wakeup_reg = {
696 .addr = 0x5B,
697 .mask = GENMASK(5, 0),
698 },
699 .wakeup_src_reg = 0x1b,
700 .wakeup_src_status_mask = BIT(3),
701 .wakeup_src_z_mask = BIT(0),
702 .wakeup_src_y_mask = BIT(1),
703 .wakeup_src_x_mask = BIT(2),
704 },
705 },
706 {
707 .wai = 0x6c,
708 .reset = {
709 .addr = 0x12,
710 .mask = BIT(0),
711 },
712 .boot = {
713 .addr = 0x12,
714 .mask = BIT(7),
715 },
716 .bdu = {
717 .addr = 0x12,
718 .mask = BIT(6),
719 },
720 .max_fifo_size = 512,
721 .id = {
722 {
723 .hw_id = ST_LSM6DSO_ID,
724 .name = ST_LSM6DSO_DEV_NAME,
725 }, {
726 .hw_id = ST_LSM6DSOX_ID,
727 .name = ST_LSM6DSOX_DEV_NAME,
728 },
729 },
730 .channels = {
731 [ST_LSM6DSX_ID_ACC] = {
732 .chan = st_lsm6dsx_acc_channels,
733 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
734 },
735 [ST_LSM6DSX_ID_GYRO] = {
736 .chan = st_lsm6dsx_gyro_channels,
737 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
738 },
739 },
740 .drdy_mask = {
741 .addr = 0x13,
742 .mask = BIT(3),
743 },
744 .odr_table = {
745 [ST_LSM6DSX_ID_ACC] = {
746 .reg = {
747 .addr = 0x10,
748 .mask = GENMASK(7, 4),
749 },
750 .odr_avl[0] = { 12500, 0x01 },
751 .odr_avl[1] = { 26000, 0x02 },
752 .odr_avl[2] = { 52000, 0x03 },
753 .odr_avl[3] = { 104000, 0x04 },
754 .odr_avl[4] = { 208000, 0x05 },
755 .odr_avl[5] = { 416000, 0x06 },
756 .odr_len = 6,
757 },
758 [ST_LSM6DSX_ID_GYRO] = {
759 .reg = {
760 .addr = 0x11,
761 .mask = GENMASK(7, 4),
762 },
763 .odr_avl[0] = { 12500, 0x01 },
764 .odr_avl[1] = { 26000, 0x02 },
765 .odr_avl[2] = { 52000, 0x03 },
766 .odr_avl[3] = { 104000, 0x04 },
767 .odr_avl[4] = { 208000, 0x05 },
768 .odr_avl[5] = { 416000, 0x06 },
769 .odr_len = 6,
770 },
771 },
772 .fs_table = {
773 [ST_LSM6DSX_ID_ACC] = {
774 .reg = {
775 .addr = 0x10,
776 .mask = GENMASK(3, 2),
777 },
778 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
779 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
780 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
781 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
782 .fs_len = 4,
783 },
784 [ST_LSM6DSX_ID_GYRO] = {
785 .reg = {
786 .addr = 0x11,
787 .mask = GENMASK(3, 2),
788 },
789 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
790 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
791 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
792 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
793 .fs_len = 4,
794 },
795 },
796 .irq_config = {
797 .irq1 = {
798 .addr = 0x0d,
799 .mask = BIT(3),
800 },
801 .irq2 = {
802 .addr = 0x0e,
803 .mask = BIT(3),
804 },
805 .lir = {
806 .addr = 0x56,
807 .mask = BIT(0),
808 },
809 .clear_on_read = {
810 .addr = 0x56,
811 .mask = BIT(6),
812 },
813 .irq1_func = {
814 .addr = 0x5e,
815 .mask = BIT(5),
816 },
817 .irq2_func = {
818 .addr = 0x5f,
819 .mask = BIT(5),
820 },
821 .hla = {
822 .addr = 0x12,
823 .mask = BIT(5),
824 },
825 .od = {
826 .addr = 0x12,
827 .mask = BIT(4),
828 },
829 },
830 .batch = {
831 [ST_LSM6DSX_ID_ACC] = {
832 .addr = 0x09,
833 .mask = GENMASK(3, 0),
834 },
835 [ST_LSM6DSX_ID_GYRO] = {
836 .addr = 0x09,
837 .mask = GENMASK(7, 4),
838 },
839 },
840 .fifo_ops = {
841 .update_fifo = st_lsm6dsx_update_fifo,
842 .read_fifo = st_lsm6dsx_read_tagged_fifo,
843 .fifo_th = {
844 .addr = 0x07,
845 .mask = GENMASK(8, 0),
846 },
847 .fifo_diff = {
848 .addr = 0x3a,
849 .mask = GENMASK(9, 0),
850 },
851 .th_wl = 1,
852 },
853 .ts_settings = {
854 .timer_en = {
855 .addr = 0x19,
856 .mask = BIT(5),
857 },
858 .decimator = {
859 .addr = 0x0a,
860 .mask = GENMASK(7, 6),
861 },
862 .freq_fine = 0x63,
863 },
864 .shub_settings = {
865 .page_mux = {
866 .addr = 0x01,
867 .mask = BIT(6),
868 },
869 .master_en = {
870 .addr = 0x14,
871 .mask = BIT(2),
872 },
873 .pullup_en = {
874 .addr = 0x14,
875 .mask = BIT(3),
876 },
877 .aux_sens = {
878 .addr = 0x14,
879 .mask = GENMASK(1, 0),
880 },
881 .wr_once = {
882 .addr = 0x14,
883 .mask = BIT(6),
884 },
885 .shub_out = 0x02,
886 .slv0_addr = 0x15,
887 .dw_slv0_addr = 0x21,
888 .batch_en = BIT(3),
889 },
890 .event_settings = {
891 .enable_reg = {
892 .addr = 0x58,
893 .mask = BIT(7),
894 },
895 .wakeup_reg = {
896 .addr = 0x5b,
897 .mask = GENMASK(5, 0),
898 },
899 .wakeup_src_reg = 0x1b,
900 .wakeup_src_status_mask = BIT(3),
901 .wakeup_src_z_mask = BIT(0),
902 .wakeup_src_y_mask = BIT(1),
903 .wakeup_src_x_mask = BIT(2),
904 },
905 },
906 {
907 .wai = 0x6b,
908 .reset = {
909 .addr = 0x12,
910 .mask = BIT(0),
911 },
912 .boot = {
913 .addr = 0x12,
914 .mask = BIT(7),
915 },
916 .bdu = {
917 .addr = 0x12,
918 .mask = BIT(6),
919 },
920 .max_fifo_size = 512,
921 .id = {
922 {
923 .hw_id = ST_ASM330LHH_ID,
924 .name = ST_ASM330LHH_DEV_NAME,
925 },
926 },
927 .channels = {
928 [ST_LSM6DSX_ID_ACC] = {
929 .chan = st_lsm6dsx_acc_channels,
930 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
931 },
932 [ST_LSM6DSX_ID_GYRO] = {
933 .chan = st_lsm6dsx_gyro_channels,
934 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
935 },
936 },
937 .drdy_mask = {
938 .addr = 0x13,
939 .mask = BIT(3),
940 },
941 .odr_table = {
942 [ST_LSM6DSX_ID_ACC] = {
943 .reg = {
944 .addr = 0x10,
945 .mask = GENMASK(7, 4),
946 },
947 .odr_avl[0] = { 12500, 0x01 },
948 .odr_avl[1] = { 26000, 0x02 },
949 .odr_avl[2] = { 52000, 0x03 },
950 .odr_avl[3] = { 104000, 0x04 },
951 .odr_avl[4] = { 208000, 0x05 },
952 .odr_avl[5] = { 416000, 0x06 },
953 .odr_len = 6,
954 },
955 [ST_LSM6DSX_ID_GYRO] = {
956 .reg = {
957 .addr = 0x11,
958 .mask = GENMASK(7, 4),
959 },
960 .odr_avl[0] = { 12500, 0x01 },
961 .odr_avl[1] = { 26000, 0x02 },
962 .odr_avl[2] = { 52000, 0x03 },
963 .odr_avl[3] = { 104000, 0x04 },
964 .odr_avl[4] = { 208000, 0x05 },
965 .odr_avl[5] = { 416000, 0x06 },
966 .odr_len = 6,
967 },
968 },
969 .fs_table = {
970 [ST_LSM6DSX_ID_ACC] = {
971 .reg = {
972 .addr = 0x10,
973 .mask = GENMASK(3, 2),
974 },
975 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
976 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
977 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
978 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
979 .fs_len = 4,
980 },
981 [ST_LSM6DSX_ID_GYRO] = {
982 .reg = {
983 .addr = 0x11,
984 .mask = GENMASK(3, 2),
985 },
986 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
987 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
988 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
989 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
990 .fs_len = 4,
991 },
992 },
993 .irq_config = {
994 .irq1 = {
995 .addr = 0x0d,
996 .mask = BIT(3),
997 },
998 .irq2 = {
999 .addr = 0x0e,
1000 .mask = BIT(3),
1001 },
1002 .lir = {
1003 .addr = 0x56,
1004 .mask = BIT(0),
1005 },
1006 .clear_on_read = {
1007 .addr = 0x56,
1008 .mask = BIT(6),
1009 },
1010 .irq1_func = {
1011 .addr = 0x5e,
1012 .mask = BIT(5),
1013 },
1014 .irq2_func = {
1015 .addr = 0x5f,
1016 .mask = BIT(5),
1017 },
1018 .hla = {
1019 .addr = 0x12,
1020 .mask = BIT(5),
1021 },
1022 .od = {
1023 .addr = 0x12,
1024 .mask = BIT(4),
1025 },
1026 },
1027 .batch = {
1028 [ST_LSM6DSX_ID_ACC] = {
1029 .addr = 0x09,
1030 .mask = GENMASK(3, 0),
1031 },
1032 [ST_LSM6DSX_ID_GYRO] = {
1033 .addr = 0x09,
1034 .mask = GENMASK(7, 4),
1035 },
1036 },
1037 .fifo_ops = {
1038 .update_fifo = st_lsm6dsx_update_fifo,
1039 .read_fifo = st_lsm6dsx_read_tagged_fifo,
1040 .fifo_th = {
1041 .addr = 0x07,
1042 .mask = GENMASK(8, 0),
1043 },
1044 .fifo_diff = {
1045 .addr = 0x3a,
1046 .mask = GENMASK(9, 0),
1047 },
1048 .th_wl = 1,
1049 },
1050 .ts_settings = {
1051 .timer_en = {
1052 .addr = 0x19,
1053 .mask = BIT(5),
1054 },
1055 .decimator = {
1056 .addr = 0x0a,
1057 .mask = GENMASK(7, 6),
1058 },
1059 .freq_fine = 0x63,
1060 },
1061 .event_settings = {
1062 .enable_reg = {
1063 .addr = 0x58,
1064 .mask = BIT(7),
1065 },
1066 .wakeup_reg = {
1067 .addr = 0x5B,
1068 .mask = GENMASK(5, 0),
1069 },
1070 .wakeup_src_reg = 0x1b,
1071 .wakeup_src_status_mask = BIT(3),
1072 .wakeup_src_z_mask = BIT(0),
1073 .wakeup_src_y_mask = BIT(1),
1074 .wakeup_src_x_mask = BIT(2),
1075 },
1076 },
1077 {
1078 .wai = 0x6b,
1079 .reset = {
1080 .addr = 0x12,
1081 .mask = BIT(0),
1082 },
1083 .boot = {
1084 .addr = 0x12,
1085 .mask = BIT(7),
1086 },
1087 .bdu = {
1088 .addr = 0x12,
1089 .mask = BIT(6),
1090 },
1091 .max_fifo_size = 512,
1092 .id = {
1093 {
1094 .hw_id = ST_LSM6DSR_ID,
1095 .name = ST_LSM6DSR_DEV_NAME,
1096 }, {
1097 .hw_id = ST_ISM330DHCX_ID,
1098 .name = ST_ISM330DHCX_DEV_NAME,
1099 }, {
1100 .hw_id = ST_LSM6DSRX_ID,
1101 .name = ST_LSM6DSRX_DEV_NAME,
1102 },
1103 },
1104 .channels = {
1105 [ST_LSM6DSX_ID_ACC] = {
1106 .chan = st_lsm6dsx_acc_channels,
1107 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1108 },
1109 [ST_LSM6DSX_ID_GYRO] = {
1110 .chan = st_lsm6dsx_gyro_channels,
1111 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
1112 },
1113 },
1114 .drdy_mask = {
1115 .addr = 0x13,
1116 .mask = BIT(3),
1117 },
1118 .odr_table = {
1119 [ST_LSM6DSX_ID_ACC] = {
1120 .reg = {
1121 .addr = 0x10,
1122 .mask = GENMASK(7, 4),
1123 },
1124 .odr_avl[0] = { 12500, 0x01 },
1125 .odr_avl[1] = { 26000, 0x02 },
1126 .odr_avl[2] = { 52000, 0x03 },
1127 .odr_avl[3] = { 104000, 0x04 },
1128 .odr_avl[4] = { 208000, 0x05 },
1129 .odr_avl[5] = { 416000, 0x06 },
1130 .odr_len = 6,
1131 },
1132 [ST_LSM6DSX_ID_GYRO] = {
1133 .reg = {
1134 .addr = 0x11,
1135 .mask = GENMASK(7, 4),
1136 },
1137 .odr_avl[0] = { 12500, 0x01 },
1138 .odr_avl[1] = { 26000, 0x02 },
1139 .odr_avl[2] = { 52000, 0x03 },
1140 .odr_avl[3] = { 104000, 0x04 },
1141 .odr_avl[4] = { 208000, 0x05 },
1142 .odr_avl[5] = { 416000, 0x06 },
1143 .odr_len = 6,
1144 },
1145 },
1146 .fs_table = {
1147 [ST_LSM6DSX_ID_ACC] = {
1148 .reg = {
1149 .addr = 0x10,
1150 .mask = GENMASK(3, 2),
1151 },
1152 .fs_avl[0] = { IIO_G_TO_M_S_2(61), 0x0 },
1153 .fs_avl[1] = { IIO_G_TO_M_S_2(122), 0x2 },
1154 .fs_avl[2] = { IIO_G_TO_M_S_2(244), 0x3 },
1155 .fs_avl[3] = { IIO_G_TO_M_S_2(488), 0x1 },
1156 .fs_len = 4,
1157 },
1158 [ST_LSM6DSX_ID_GYRO] = {
1159 .reg = {
1160 .addr = 0x11,
1161 .mask = GENMASK(3, 2),
1162 },
1163 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750), 0x0 },
1164 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500), 0x1 },
1165 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000), 0x2 },
1166 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000), 0x3 },
1167 .fs_len = 4,
1168 },
1169 },
1170 .irq_config = {
1171 .irq1 = {
1172 .addr = 0x0d,
1173 .mask = BIT(3),
1174 },
1175 .irq2 = {
1176 .addr = 0x0e,
1177 .mask = BIT(3),
1178 },
1179 .lir = {
1180 .addr = 0x56,
1181 .mask = BIT(0),
1182 },
1183 .clear_on_read = {
1184 .addr = 0x56,
1185 .mask = BIT(6),
1186 },
1187 .irq1_func = {
1188 .addr = 0x5e,
1189 .mask = BIT(5),
1190 },
1191 .irq2_func = {
1192 .addr = 0x5f,
1193 .mask = BIT(5),
1194 },
1195 .hla = {
1196 .addr = 0x12,
1197 .mask = BIT(5),
1198 },
1199 .od = {
1200 .addr = 0x12,
1201 .mask = BIT(4),
1202 },
1203 },
1204 .batch = {
1205 [ST_LSM6DSX_ID_ACC] = {
1206 .addr = 0x09,
1207 .mask = GENMASK(3, 0),
1208 },
1209 [ST_LSM6DSX_ID_GYRO] = {
1210 .addr = 0x09,
1211 .mask = GENMASK(7, 4),
1212 },
1213 },
1214 .fifo_ops = {
1215 .update_fifo = st_lsm6dsx_update_fifo,
1216 .read_fifo = st_lsm6dsx_read_tagged_fifo,
1217 .fifo_th = {
1218 .addr = 0x07,
1219 .mask = GENMASK(8, 0),
1220 },
1221 .fifo_diff = {
1222 .addr = 0x3a,
1223 .mask = GENMASK(9, 0),
1224 },
1225 .th_wl = 1,
1226 },
1227 .ts_settings = {
1228 .timer_en = {
1229 .addr = 0x19,
1230 .mask = BIT(5),
1231 },
1232 .decimator = {
1233 .addr = 0x0a,
1234 .mask = GENMASK(7, 6),
1235 },
1236 .freq_fine = 0x63,
1237 },
1238 .shub_settings = {
1239 .page_mux = {
1240 .addr = 0x01,
1241 .mask = BIT(6),
1242 },
1243 .master_en = {
1244 .addr = 0x14,
1245 .mask = BIT(2),
1246 },
1247 .pullup_en = {
1248 .addr = 0x14,
1249 .mask = BIT(3),
1250 },
1251 .aux_sens = {
1252 .addr = 0x14,
1253 .mask = GENMASK(1, 0),
1254 },
1255 .wr_once = {
1256 .addr = 0x14,
1257 .mask = BIT(6),
1258 },
1259 .shub_out = 0x02,
1260 .slv0_addr = 0x15,
1261 .dw_slv0_addr = 0x21,
1262 .batch_en = BIT(3),
1263 },
1264 .event_settings = {
1265 .enable_reg = {
1266 .addr = 0x58,
1267 .mask = BIT(7),
1268 },
1269 .wakeup_reg = {
1270 .addr = 0x5B,
1271 .mask = GENMASK(5, 0),
1272 },
1273 .wakeup_src_reg = 0x1b,
1274 .wakeup_src_status_mask = BIT(3),
1275 .wakeup_src_z_mask = BIT(0),
1276 .wakeup_src_y_mask = BIT(1),
1277 .wakeup_src_x_mask = BIT(2),
1278 }
1279 },
1280};
1281
1282int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable)
1283{
1284 const struct st_lsm6dsx_shub_settings *hub_settings;
1285 unsigned int data;
1286 int err;
1287
1288 hub_settings = &hw->settings->shub_settings;
1289 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask);
1290 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr,
1291 hub_settings->page_mux.mask, data);
1292 usleep_range(100, 150);
1293
1294 return err;
1295}
1296
1297static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id,
1298 const char **name)
1299{
1300 int err, i, j, data;
1301
1302 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) {
1303 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) {
1304 if (st_lsm6dsx_sensor_settings[i].id[j].name &&
1305 id == st_lsm6dsx_sensor_settings[i].id[j].hw_id)
1306 break;
1307 }
1308 if (j < ST_LSM6DSX_MAX_ID)
1309 break;
1310 }
1311
1312 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) {
1313 dev_err(hw->dev, "unsupported hw id [%02x]\n", id);
1314 return -ENODEV;
1315 }
1316
1317 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data);
1318 if (err < 0) {
1319 dev_err(hw->dev, "failed to read whoami register\n");
1320 return err;
1321 }
1322
1323 if (data != st_lsm6dsx_sensor_settings[i].wai) {
1324 dev_err(hw->dev, "unsupported whoami [%02x]\n", data);
1325 return -ENODEV;
1326 }
1327
1328 *name = st_lsm6dsx_sensor_settings[i].id[j].name;
1329 hw->settings = &st_lsm6dsx_sensor_settings[i];
1330
1331 return 0;
1332}
1333
1334static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor,
1335 u32 gain)
1336{
1337 const struct st_lsm6dsx_fs_table_entry *fs_table;
1338 unsigned int data;
1339 int i, err;
1340
1341 fs_table = &sensor->hw->settings->fs_table[sensor->id];
1342 for (i = 0; i < fs_table->fs_len; i++) {
1343 if (fs_table->fs_avl[i].gain == gain)
1344 break;
1345 }
1346
1347 if (i == fs_table->fs_len)
1348 return -EINVAL;
1349
1350 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val,
1351 fs_table->reg.mask);
1352 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr,
1353 fs_table->reg.mask, data);
1354 if (err < 0)
1355 return err;
1356
1357 sensor->gain = gain;
1358
1359 return 0;
1360}
1361
1362int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u32 odr, u8 *val)
1363{
1364 const struct st_lsm6dsx_odr_table_entry *odr_table;
1365 int i;
1366
1367 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1368 for (i = 0; i < odr_table->odr_len; i++) {
1369
1370
1371
1372
1373 if (odr_table->odr_avl[i].milli_hz >= odr)
1374 break;
1375 }
1376
1377 if (i == odr_table->odr_len)
1378 return -EINVAL;
1379
1380 *val = odr_table->odr_avl[i].val;
1381 return odr_table->odr_avl[i].milli_hz;
1382}
1383
1384static int
1385st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u32 odr,
1386 enum st_lsm6dsx_sensor_id id)
1387{
1388 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]);
1389
1390 if (odr > 0) {
1391 if (hw->enable_mask & BIT(id))
1392 return max_t(u32, ref->odr, odr);
1393 else
1394 return odr;
1395 } else {
1396 return (hw->enable_mask & BIT(id)) ? ref->odr : 0;
1397 }
1398}
1399
1400static int
1401st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u32 req_odr)
1402{
1403 struct st_lsm6dsx_sensor *ref_sensor = sensor;
1404 struct st_lsm6dsx_hw *hw = sensor->hw;
1405 const struct st_lsm6dsx_reg *reg;
1406 unsigned int data;
1407 u8 val = 0;
1408 int err;
1409
1410 switch (sensor->id) {
1411 case ST_LSM6DSX_ID_EXT0:
1412 case ST_LSM6DSX_ID_EXT1:
1413 case ST_LSM6DSX_ID_EXT2:
1414 case ST_LSM6DSX_ID_ACC: {
1415 u32 odr;
1416 int i;
1417
1418
1419
1420
1421
1422
1423
1424 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
1425 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) {
1426 if (!hw->iio_devs[i] || i == sensor->id)
1427 continue;
1428
1429 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i);
1430 if (odr != req_odr)
1431
1432 return 0;
1433 }
1434 break;
1435 }
1436 default:
1437 break;
1438 }
1439
1440 if (req_odr > 0) {
1441 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val);
1442 if (err < 0)
1443 return err;
1444 }
1445
1446 reg = &hw->settings->odr_table[ref_sensor->id].reg;
1447 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1448 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data);
1449}
1450
1451static int
1452__st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1453 bool enable)
1454{
1455 struct st_lsm6dsx_hw *hw = sensor->hw;
1456 u32 odr = enable ? sensor->odr : 0;
1457 int err;
1458
1459 err = st_lsm6dsx_set_odr(sensor, odr);
1460 if (err < 0)
1461 return err;
1462
1463 if (enable)
1464 hw->enable_mask |= BIT(sensor->id);
1465 else
1466 hw->enable_mask &= ~BIT(sensor->id);
1467
1468 return 0;
1469}
1470
1471static int
1472st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor, bool enable)
1473{
1474 struct st_lsm6dsx_hw *hw = sensor->hw;
1475
1476 if (sensor->id == ST_LSM6DSX_ID_GYRO || enable)
1477 return 0;
1478
1479 return hw->enable_event;
1480}
1481
1482int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1483 bool enable)
1484{
1485 if (st_lsm6dsx_check_events(sensor, enable))
1486 return 0;
1487
1488 return __st_lsm6dsx_sensor_set_enable(sensor, enable);
1489}
1490
1491static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor,
1492 u8 addr, int *val)
1493{
1494 struct st_lsm6dsx_hw *hw = sensor->hw;
1495 int err, delay;
1496 __le16 data;
1497
1498 err = st_lsm6dsx_sensor_set_enable(sensor, true);
1499 if (err < 0)
1500 return err;
1501
1502 delay = 1000000000 / sensor->odr;
1503 usleep_range(delay, 2 * delay);
1504
1505 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data));
1506 if (err < 0)
1507 return err;
1508
1509 if (!hw->enable_event)
1510 st_lsm6dsx_sensor_set_enable(sensor, false);
1511
1512 *val = (s16)le16_to_cpu(data);
1513
1514 return IIO_VAL_INT;
1515}
1516
1517static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev,
1518 struct iio_chan_spec const *ch,
1519 int *val, int *val2, long mask)
1520{
1521 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1522 int ret;
1523
1524 switch (mask) {
1525 case IIO_CHAN_INFO_RAW:
1526 ret = iio_device_claim_direct_mode(iio_dev);
1527 if (ret)
1528 break;
1529
1530 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val);
1531 iio_device_release_direct_mode(iio_dev);
1532 break;
1533 case IIO_CHAN_INFO_SAMP_FREQ:
1534 *val = sensor->odr / 1000;
1535 *val2 = (sensor->odr % 1000) * 1000;
1536 ret = IIO_VAL_INT_PLUS_MICRO;
1537 break;
1538 case IIO_CHAN_INFO_SCALE:
1539 *val = 0;
1540 *val2 = sensor->gain;
1541 ret = IIO_VAL_INT_PLUS_MICRO;
1542 break;
1543 default:
1544 ret = -EINVAL;
1545 break;
1546 }
1547
1548 return ret;
1549}
1550
1551static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev,
1552 struct iio_chan_spec const *chan,
1553 int val, int val2, long mask)
1554{
1555 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1556 int err;
1557
1558 err = iio_device_claim_direct_mode(iio_dev);
1559 if (err)
1560 return err;
1561
1562 switch (mask) {
1563 case IIO_CHAN_INFO_SCALE:
1564 err = st_lsm6dsx_set_full_scale(sensor, val2);
1565 break;
1566 case IIO_CHAN_INFO_SAMP_FREQ: {
1567 u8 data;
1568
1569 val = val * 1000 + val2 / 1000;
1570 val = st_lsm6dsx_check_odr(sensor, val, &data);
1571 if (val < 0)
1572 err = val;
1573 else
1574 sensor->odr = val;
1575 break;
1576 }
1577 default:
1578 err = -EINVAL;
1579 break;
1580 }
1581
1582 iio_device_release_direct_mode(iio_dev);
1583
1584 return err;
1585}
1586
1587static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)
1588{
1589 const struct st_lsm6dsx_reg *reg;
1590 unsigned int data;
1591 int err;
1592
1593 if (!hw->settings->irq_config.irq1_func.addr)
1594 return -ENOTSUPP;
1595
1596 reg = &hw->settings->event_settings.enable_reg;
1597 if (reg->addr) {
1598 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask);
1599 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1600 reg->mask, data);
1601 if (err < 0)
1602 return err;
1603 }
1604
1605
1606 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask);
1607 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr,
1608 hw->irq_routing->mask, data);
1609}
1610
1611static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
1612 const struct iio_chan_spec *chan,
1613 enum iio_event_type type,
1614 enum iio_event_direction dir,
1615 enum iio_event_info info,
1616 int *val, int *val2)
1617{
1618 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1619 struct st_lsm6dsx_hw *hw = sensor->hw;
1620
1621 if (type != IIO_EV_TYPE_THRESH)
1622 return -EINVAL;
1623
1624 *val2 = 0;
1625 *val = hw->event_threshold;
1626
1627 return IIO_VAL_INT;
1628}
1629
1630static int
1631st_lsm6dsx_write_event(struct iio_dev *iio_dev,
1632 const struct iio_chan_spec *chan,
1633 enum iio_event_type type,
1634 enum iio_event_direction dir,
1635 enum iio_event_info info,
1636 int val, int val2)
1637{
1638 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1639 struct st_lsm6dsx_hw *hw = sensor->hw;
1640 const struct st_lsm6dsx_reg *reg;
1641 unsigned int data;
1642 int err;
1643
1644 if (type != IIO_EV_TYPE_THRESH)
1645 return -EINVAL;
1646
1647 if (val < 0 || val > 31)
1648 return -EINVAL;
1649
1650 reg = &hw->settings->event_settings.wakeup_reg;
1651 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1652 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1653 reg->mask, data);
1654 if (err < 0)
1655 return -EINVAL;
1656
1657 hw->event_threshold = val;
1658
1659 return 0;
1660}
1661
1662static int
1663st_lsm6dsx_read_event_config(struct iio_dev *iio_dev,
1664 const struct iio_chan_spec *chan,
1665 enum iio_event_type type,
1666 enum iio_event_direction dir)
1667{
1668 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1669 struct st_lsm6dsx_hw *hw = sensor->hw;
1670
1671 if (type != IIO_EV_TYPE_THRESH)
1672 return -EINVAL;
1673
1674 return !!(hw->enable_event & BIT(chan->channel2));
1675}
1676
1677static int
1678st_lsm6dsx_write_event_config(struct iio_dev *iio_dev,
1679 const struct iio_chan_spec *chan,
1680 enum iio_event_type type,
1681 enum iio_event_direction dir, int state)
1682{
1683 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1684 struct st_lsm6dsx_hw *hw = sensor->hw;
1685 u8 enable_event;
1686 int err;
1687
1688 if (type != IIO_EV_TYPE_THRESH)
1689 return -EINVAL;
1690
1691 if (state) {
1692 enable_event = hw->enable_event | BIT(chan->channel2);
1693
1694
1695 if (hw->enable_event)
1696 goto out;
1697 } else {
1698 enable_event = hw->enable_event & ~BIT(chan->channel2);
1699
1700
1701 if (enable_event)
1702 goto out;
1703 }
1704
1705
1706 if (hw->enable_event == enable_event)
1707 return 0;
1708
1709 err = st_lsm6dsx_event_setup(hw, state);
1710 if (err < 0)
1711 return err;
1712
1713 mutex_lock(&hw->conf_lock);
1714 if (enable_event || !(hw->fifo_mask & BIT(sensor->id)))
1715 err = __st_lsm6dsx_sensor_set_enable(sensor, state);
1716 mutex_unlock(&hw->conf_lock);
1717 if (err < 0)
1718 return err;
1719
1720out:
1721 hw->enable_event = enable_event;
1722
1723 return 0;
1724}
1725
1726int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val)
1727{
1728 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1729 struct st_lsm6dsx_hw *hw = sensor->hw;
1730 int err;
1731
1732 if (val < 1 || val > hw->settings->max_fifo_size)
1733 return -EINVAL;
1734
1735 mutex_lock(&hw->conf_lock);
1736
1737 err = st_lsm6dsx_update_watermark(sensor, val);
1738
1739 mutex_unlock(&hw->conf_lock);
1740
1741 if (err < 0)
1742 return err;
1743
1744 sensor->watermark = val;
1745
1746 return 0;
1747}
1748
1749static ssize_t
1750st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev,
1751 struct device_attribute *attr,
1752 char *buf)
1753{
1754 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev));
1755 const struct st_lsm6dsx_odr_table_entry *odr_table;
1756 int i, len = 0;
1757
1758 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1759 for (i = 0; i < odr_table->odr_len; i++)
1760 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%03d ",
1761 odr_table->odr_avl[i].milli_hz / 1000,
1762 odr_table->odr_avl[i].milli_hz % 1000);
1763 buf[len - 1] = '\n';
1764
1765 return len;
1766}
1767
1768static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev,
1769 struct device_attribute *attr,
1770 char *buf)
1771{
1772 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev));
1773 const struct st_lsm6dsx_fs_table_entry *fs_table;
1774 struct st_lsm6dsx_hw *hw = sensor->hw;
1775 int i, len = 0;
1776
1777 fs_table = &hw->settings->fs_table[sensor->id];
1778 for (i = 0; i < fs_table->fs_len; i++)
1779 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06u ",
1780 fs_table->fs_avl[i].gain);
1781 buf[len - 1] = '\n';
1782
1783 return len;
1784}
1785
1786static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail);
1787static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
1788 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
1789static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444,
1790 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
1791
1792static struct attribute *st_lsm6dsx_acc_attributes[] = {
1793 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1794 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1795 NULL,
1796};
1797
1798static const struct attribute_group st_lsm6dsx_acc_attribute_group = {
1799 .attrs = st_lsm6dsx_acc_attributes,
1800};
1801
1802static const struct iio_info st_lsm6dsx_acc_info = {
1803 .attrs = &st_lsm6dsx_acc_attribute_group,
1804 .read_raw = st_lsm6dsx_read_raw,
1805 .write_raw = st_lsm6dsx_write_raw,
1806 .read_event_value = st_lsm6dsx_read_event,
1807 .write_event_value = st_lsm6dsx_write_event,
1808 .read_event_config = st_lsm6dsx_read_event_config,
1809 .write_event_config = st_lsm6dsx_write_event_config,
1810 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
1811};
1812
1813static struct attribute *st_lsm6dsx_gyro_attributes[] = {
1814 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1815 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr,
1816 NULL,
1817};
1818
1819static const struct attribute_group st_lsm6dsx_gyro_attribute_group = {
1820 .attrs = st_lsm6dsx_gyro_attributes,
1821};
1822
1823static const struct iio_info st_lsm6dsx_gyro_info = {
1824 .attrs = &st_lsm6dsx_gyro_attribute_group,
1825 .read_raw = st_lsm6dsx_read_raw,
1826 .write_raw = st_lsm6dsx_write_raw,
1827 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
1828};
1829
1830static int st_lsm6dsx_of_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
1831{
1832 struct device_node *np = hw->dev->of_node;
1833
1834 if (!np)
1835 return -EINVAL;
1836
1837 return of_property_read_u32(np, "st,drdy-int-pin", drdy_pin);
1838}
1839
1840static int
1841st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw,
1842 const struct st_lsm6dsx_reg **drdy_reg)
1843{
1844 int err = 0, drdy_pin;
1845
1846 if (st_lsm6dsx_of_get_drdy_pin(hw, &drdy_pin) < 0) {
1847 struct st_sensors_platform_data *pdata;
1848 struct device *dev = hw->dev;
1849
1850 pdata = (struct st_sensors_platform_data *)dev->platform_data;
1851 drdy_pin = pdata ? pdata->drdy_int_pin : 1;
1852 }
1853
1854 switch (drdy_pin) {
1855 case 1:
1856 hw->irq_routing = &hw->settings->irq_config.irq1_func;
1857 *drdy_reg = &hw->settings->irq_config.irq1;
1858 break;
1859 case 2:
1860 hw->irq_routing = &hw->settings->irq_config.irq2_func;
1861 *drdy_reg = &hw->settings->irq_config.irq2;
1862 break;
1863 default:
1864 dev_err(hw->dev, "unsupported data ready pin\n");
1865 err = -EINVAL;
1866 break;
1867 }
1868
1869 return err;
1870}
1871
1872static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw)
1873{
1874 const struct st_lsm6dsx_shub_settings *hub_settings;
1875 struct device_node *np = hw->dev->of_node;
1876 struct st_sensors_platform_data *pdata;
1877 unsigned int data;
1878 int err = 0;
1879
1880 hub_settings = &hw->settings->shub_settings;
1881
1882 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data;
1883 if ((np && of_property_read_bool(np, "st,pullups")) ||
1884 (pdata && pdata->pullups)) {
1885 err = st_lsm6dsx_set_page(hw, true);
1886 if (err < 0)
1887 return err;
1888
1889 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask);
1890 err = regmap_update_bits(hw->regmap,
1891 hub_settings->pullup_en.addr,
1892 hub_settings->pullup_en.mask, data);
1893
1894 st_lsm6dsx_set_page(hw, false);
1895
1896 if (err < 0)
1897 return err;
1898 }
1899
1900 if (hub_settings->aux_sens.addr) {
1901
1902 err = st_lsm6dsx_set_page(hw, true);
1903 if (err < 0)
1904 return err;
1905
1906 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask);
1907 err = regmap_update_bits(hw->regmap,
1908 hub_settings->aux_sens.addr,
1909 hub_settings->aux_sens.mask, data);
1910
1911 st_lsm6dsx_set_page(hw, false);
1912 }
1913
1914 return err;
1915}
1916
1917static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)
1918{
1919 const struct st_lsm6dsx_hw_ts_settings *ts_settings;
1920 int err, val;
1921
1922 ts_settings = &hw->settings->ts_settings;
1923
1924 if (ts_settings->timer_en.addr) {
1925 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask);
1926 err = regmap_update_bits(hw->regmap,
1927 ts_settings->timer_en.addr,
1928 ts_settings->timer_en.mask, val);
1929 if (err < 0)
1930 return err;
1931 }
1932
1933
1934 if (ts_settings->hr_timer.addr) {
1935 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask);
1936 err = regmap_update_bits(hw->regmap,
1937 ts_settings->hr_timer.addr,
1938 ts_settings->hr_timer.mask, val);
1939 if (err < 0)
1940 return err;
1941 }
1942
1943
1944 if (ts_settings->fifo_en.addr) {
1945 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask);
1946 err = regmap_update_bits(hw->regmap,
1947 ts_settings->fifo_en.addr,
1948 ts_settings->fifo_en.mask, val);
1949 if (err < 0)
1950 return err;
1951 }
1952
1953
1954 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY;
1955 if (ts_settings->freq_fine) {
1956 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val);
1957 if (err < 0)
1958 return err;
1959
1960
1961
1962
1963
1964
1965
1966
1967 hw->ts_gain -= ((s8)val * 37500) / 1000;
1968 }
1969
1970 return 0;
1971}
1972
1973static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
1974{
1975 const struct st_lsm6dsx_reg *reg;
1976 int err;
1977
1978
1979 reg = &hw->settings->reset;
1980 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1981 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1982 if (err < 0)
1983 return err;
1984
1985 msleep(50);
1986
1987
1988 reg = &hw->settings->boot;
1989 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1990 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1991 if (err < 0)
1992 return err;
1993
1994 msleep(50);
1995
1996
1997 reg = &hw->settings->bdu;
1998 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1999 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2000 if (err < 0)
2001 return err;
2002
2003
2004 err = st_lsm6dsx_get_drdy_reg(hw, ®);
2005 if (err < 0)
2006 return err;
2007
2008 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2009 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2010 if (err < 0)
2011 return err;
2012
2013
2014 if (hw->settings->irq_config.lir.addr) {
2015 reg = &hw->settings->irq_config.lir;
2016 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2017 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2018 if (err < 0)
2019 return err;
2020
2021
2022 if (hw->settings->irq_config.clear_on_read.addr) {
2023 reg = &hw->settings->irq_config.clear_on_read;
2024 err = regmap_update_bits(hw->regmap,
2025 reg->addr, reg->mask,
2026 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2027 if (err < 0)
2028 return err;
2029 }
2030 }
2031
2032
2033 if (hw->settings->drdy_mask.addr) {
2034 reg = &hw->settings->drdy_mask;
2035 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2036 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2037 if (err < 0)
2038 return err;
2039 }
2040
2041 err = st_lsm6dsx_init_shub(hw);
2042 if (err < 0)
2043 return err;
2044
2045 return st_lsm6dsx_init_hw_timer(hw);
2046}
2047
2048static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
2049 enum st_lsm6dsx_sensor_id id,
2050 const char *name)
2051{
2052 struct st_lsm6dsx_sensor *sensor;
2053 struct iio_dev *iio_dev;
2054
2055 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor));
2056 if (!iio_dev)
2057 return NULL;
2058
2059 iio_dev->modes = INDIO_DIRECT_MODE;
2060 iio_dev->dev.parent = hw->dev;
2061 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks;
2062 iio_dev->channels = hw->settings->channels[id].chan;
2063 iio_dev->num_channels = hw->settings->channels[id].len;
2064
2065 sensor = iio_priv(iio_dev);
2066 sensor->id = id;
2067 sensor->hw = hw;
2068 sensor->odr = hw->settings->odr_table[id].odr_avl[0].milli_hz;
2069 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain;
2070 sensor->watermark = 1;
2071
2072 switch (id) {
2073 case ST_LSM6DSX_ID_ACC:
2074 iio_dev->info = &st_lsm6dsx_acc_info;
2075 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel",
2076 name);
2077 break;
2078 case ST_LSM6DSX_ID_GYRO:
2079 iio_dev->info = &st_lsm6dsx_gyro_info;
2080 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro",
2081 name);
2082 break;
2083 default:
2084 return NULL;
2085 }
2086 iio_dev->name = sensor->name;
2087
2088 return iio_dev;
2089}
2090
2091static bool
2092st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw)
2093{
2094 const struct st_lsm6dsx_event_settings *event_settings;
2095 int err, data;
2096 s64 timestamp;
2097
2098 if (!hw->enable_event)
2099 return false;
2100
2101 event_settings = &hw->settings->event_settings;
2102 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg,
2103 &data, sizeof(data));
2104 if (err < 0)
2105 return false;
2106
2107 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
2108 if ((data & hw->settings->event_settings.wakeup_src_z_mask) &&
2109 (hw->enable_event & BIT(IIO_MOD_Z)))
2110 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2111 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2112 0,
2113 IIO_MOD_Z,
2114 IIO_EV_TYPE_THRESH,
2115 IIO_EV_DIR_EITHER),
2116 timestamp);
2117
2118 if ((data & hw->settings->event_settings.wakeup_src_y_mask) &&
2119 (hw->enable_event & BIT(IIO_MOD_Y)))
2120 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2121 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2122 0,
2123 IIO_MOD_Y,
2124 IIO_EV_TYPE_THRESH,
2125 IIO_EV_DIR_EITHER),
2126 timestamp);
2127
2128 if ((data & hw->settings->event_settings.wakeup_src_x_mask) &&
2129 (hw->enable_event & BIT(IIO_MOD_X)))
2130 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2131 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2132 0,
2133 IIO_MOD_X,
2134 IIO_EV_TYPE_THRESH,
2135 IIO_EV_DIR_EITHER),
2136 timestamp);
2137
2138 return data & event_settings->wakeup_src_status_mask;
2139}
2140
2141static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private)
2142{
2143 struct st_lsm6dsx_hw *hw = private;
2144 bool event;
2145 int count;
2146
2147 event = st_lsm6dsx_report_motion_event(hw);
2148
2149 if (!hw->settings->fifo_ops.read_fifo)
2150 return event ? IRQ_HANDLED : IRQ_NONE;
2151
2152 mutex_lock(&hw->fifo_lock);
2153 count = hw->settings->fifo_ops.read_fifo(hw);
2154 mutex_unlock(&hw->fifo_lock);
2155
2156 return count || event ? IRQ_HANDLED : IRQ_NONE;
2157}
2158
2159static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw)
2160{
2161 struct device_node *np = hw->dev->of_node;
2162 struct st_sensors_platform_data *pdata;
2163 const struct st_lsm6dsx_reg *reg;
2164 unsigned long irq_type;
2165 bool irq_active_low;
2166 int err;
2167
2168 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq));
2169
2170 switch (irq_type) {
2171 case IRQF_TRIGGER_HIGH:
2172 case IRQF_TRIGGER_RISING:
2173 irq_active_low = false;
2174 break;
2175 case IRQF_TRIGGER_LOW:
2176 case IRQF_TRIGGER_FALLING:
2177 irq_active_low = true;
2178 break;
2179 default:
2180 dev_info(hw->dev, "mode %lx unsupported\n", irq_type);
2181 return -EINVAL;
2182 }
2183
2184 reg = &hw->settings->irq_config.hla;
2185 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2186 ST_LSM6DSX_SHIFT_VAL(irq_active_low,
2187 reg->mask));
2188 if (err < 0)
2189 return err;
2190
2191 pdata = (struct st_sensors_platform_data *)hw->dev->platform_data;
2192 if ((np && of_property_read_bool(np, "drive-open-drain")) ||
2193 (pdata && pdata->open_drain)) {
2194 reg = &hw->settings->irq_config.od;
2195 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2196 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2197 if (err < 0)
2198 return err;
2199
2200 irq_type |= IRQF_SHARED;
2201 }
2202
2203 err = devm_request_threaded_irq(hw->dev, hw->irq,
2204 NULL,
2205 st_lsm6dsx_handler_thread,
2206 irq_type | IRQF_ONESHOT,
2207 "lsm6dsx", hw);
2208 if (err) {
2209 dev_err(hw->dev, "failed to request trigger irq %d\n",
2210 hw->irq);
2211 return err;
2212 }
2213
2214 return 0;
2215}
2216
2217int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id,
2218 struct regmap *regmap)
2219{
2220 struct st_sensors_platform_data *pdata = dev->platform_data;
2221 const struct st_lsm6dsx_shub_settings *hub_settings;
2222 struct device_node *np = dev->of_node;
2223 struct st_lsm6dsx_hw *hw;
2224 const char *name = NULL;
2225 int i, err;
2226
2227 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
2228 if (!hw)
2229 return -ENOMEM;
2230
2231 dev_set_drvdata(dev, (void *)hw);
2232
2233 mutex_init(&hw->fifo_lock);
2234 mutex_init(&hw->conf_lock);
2235 mutex_init(&hw->page_lock);
2236
2237 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL);
2238 if (!hw->buff)
2239 return -ENOMEM;
2240
2241 hw->dev = dev;
2242 hw->irq = irq;
2243 hw->regmap = regmap;
2244
2245 err = st_lsm6dsx_check_whoami(hw, hw_id, &name);
2246 if (err < 0)
2247 return err;
2248
2249 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) {
2250 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
2251 if (!hw->iio_devs[i])
2252 return -ENOMEM;
2253 }
2254
2255 err = st_lsm6dsx_init_device(hw);
2256 if (err < 0)
2257 return err;
2258
2259 hub_settings = &hw->settings->shub_settings;
2260 if (hub_settings->master_en.addr) {
2261 err = st_lsm6dsx_shub_probe(hw, name);
2262 if (err < 0)
2263 return err;
2264 }
2265
2266 if (hw->irq > 0) {
2267 err = st_lsm6dsx_irq_setup(hw);
2268 if (err < 0)
2269 return err;
2270
2271 err = st_lsm6dsx_fifo_setup(hw);
2272 if (err < 0)
2273 return err;
2274 }
2275
2276 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2277 if (!hw->iio_devs[i])
2278 continue;
2279
2280 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]);
2281 if (err)
2282 return err;
2283 }
2284
2285 if ((np && of_property_read_bool(np, "wakeup-source")) ||
2286 (pdata && pdata->wakeup_source))
2287 device_init_wakeup(dev, true);
2288
2289 return 0;
2290}
2291EXPORT_SYMBOL(st_lsm6dsx_probe);
2292
2293static int __maybe_unused st_lsm6dsx_suspend(struct device *dev)
2294{
2295 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2296 struct st_lsm6dsx_sensor *sensor;
2297 int i, err = 0;
2298
2299 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2300 if (!hw->iio_devs[i])
2301 continue;
2302
2303 sensor = iio_priv(hw->iio_devs[i]);
2304 if (!(hw->enable_mask & BIT(sensor->id)))
2305 continue;
2306
2307 if (device_may_wakeup(dev) &&
2308 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) {
2309
2310 enable_irq_wake(hw->irq);
2311 continue;
2312 }
2313
2314 if (sensor->id == ST_LSM6DSX_ID_EXT0 ||
2315 sensor->id == ST_LSM6DSX_ID_EXT1 ||
2316 sensor->id == ST_LSM6DSX_ID_EXT2)
2317 err = st_lsm6dsx_shub_set_enable(sensor, false);
2318 else
2319 err = st_lsm6dsx_sensor_set_enable(sensor, false);
2320 if (err < 0)
2321 return err;
2322
2323 hw->suspend_mask |= BIT(sensor->id);
2324 }
2325
2326 if (hw->fifo_mask)
2327 err = st_lsm6dsx_flush_fifo(hw);
2328
2329 return err;
2330}
2331
2332static int __maybe_unused st_lsm6dsx_resume(struct device *dev)
2333{
2334 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2335 struct st_lsm6dsx_sensor *sensor;
2336 int i, err = 0;
2337
2338 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2339 if (!hw->iio_devs[i])
2340 continue;
2341
2342 sensor = iio_priv(hw->iio_devs[i]);
2343 if (device_may_wakeup(dev) &&
2344 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event)
2345 disable_irq_wake(hw->irq);
2346
2347 if (!(hw->suspend_mask & BIT(sensor->id)))
2348 continue;
2349
2350 if (sensor->id == ST_LSM6DSX_ID_EXT0 ||
2351 sensor->id == ST_LSM6DSX_ID_EXT1 ||
2352 sensor->id == ST_LSM6DSX_ID_EXT2)
2353 err = st_lsm6dsx_shub_set_enable(sensor, true);
2354 else
2355 err = st_lsm6dsx_sensor_set_enable(sensor, true);
2356 if (err < 0)
2357 return err;
2358
2359 hw->suspend_mask &= ~BIT(sensor->id);
2360 }
2361
2362 if (hw->fifo_mask)
2363 err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT);
2364
2365 return err;
2366}
2367
2368const struct dev_pm_ops st_lsm6dsx_pm_ops = {
2369 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume)
2370};
2371EXPORT_SYMBOL(st_lsm6dsx_pm_ops);
2372
2373MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>");
2374MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
2375MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver");
2376MODULE_LICENSE("GPL v2");
2377
