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11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/rtsx_pci.h>
14
15#include "rts5261.h"
16#include "rtsx_pcr.h"
17
18static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
19{
20 u8 val;
21
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
23 return val & IC_VERSION_MASK;
24}
25
26static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
27{
28 u8 driving_3v3[4][3] = {
29 {0x13, 0x13, 0x13},
30 {0x96, 0x96, 0x96},
31 {0x7F, 0x7F, 0x7F},
32 {0x96, 0x96, 0x96},
33 };
34 u8 driving_1v8[4][3] = {
35 {0x99, 0x99, 0x99},
36 {0x3A, 0x3A, 0x3A},
37 {0xE6, 0xE6, 0xE6},
38 {0xB3, 0xB3, 0xB3},
39 };
40 u8 (*driving)[3], drive_sel;
41
42 if (voltage == OUTPUT_3V3) {
43 driving = driving_3v3;
44 drive_sel = pcr->sd30_drive_sel_3v3;
45 } else {
46 driving = driving_1v8;
47 drive_sel = pcr->sd30_drive_sel_1v8;
48 }
49
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
51 0xFF, driving[drive_sel][0]);
52
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
54 0xFF, driving[drive_sel][1]);
55
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 0xFF, driving[drive_sel][2]);
58}
59
60static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61{
62 u32 reg;
63
64 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
65 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
66
67 if (!rts5261_vendor_setting_valid(reg)) {
68 pcr_dbg(pcr, "skip fetch vendor setting\n");
69 return;
70 }
71
72 pcr->card_drive_sel &= 0x3F;
73 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
74
75 if (rts5261_reg_check_reverse_socket(reg))
76 pcr->flags |= PCR_REVERSE_SOCKET;
77
78
79 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
80 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
81
82 pcr->aspm_en = rts5261_reg_to_aspm(reg);
83 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
84 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
85}
86
87static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
88{
89
90 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
91 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
92 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
93 RELINK_TIME_MASK, 0);
94
95 if (pm_state == HOST_ENTER_S3)
96 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
97 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
98
99 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
100 SSC_POWER_DOWN, SSC_POWER_DOWN);
101}
102
103static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
104{
105 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
106 LED_SHINE_MASK, LED_SHINE_EN);
107}
108
109static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
110{
111 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
112 LED_SHINE_MASK, LED_SHINE_DISABLE);
113}
114
115static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
116{
117 return rtsx_pci_write_register(pcr, GPIO_CTL,
118 0x02, 0x02);
119}
120
121static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
122{
123 return rtsx_pci_write_register(pcr, GPIO_CTL,
124 0x02, 0x00);
125}
126
127
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130
131
132
133
134static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
135 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
136 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
137 0,
138};
139
140
141
142
143
144
145
146
147static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
148 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
149 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
150 0,
151};
152
153static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
154{
155 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
156 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
157 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
158 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
159 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
160 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
161
162 return 0;
163}
164
165static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
166{
167 struct rtsx_cr_option *option = &pcr->option;
168
169 if (option->ocp_en)
170 rtsx_pci_enable_ocp(pcr);
171
172
173 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
174 RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
175 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
176 RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
177
178 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
179 RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
180
181 msleep(20);
182
183 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
184
185
186 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
187 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
188
189 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
190 0xFF, SD20_RX_POS_EDGE);
191 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
192 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
193 SD_STOP | SD_CLR_ERR);
194
195
196 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
197 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
198 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
199 SD30_CLK_STOP_CFG0, 0);
200
201 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
202 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
203 rts5261_sd_set_sample_push_timing_sd30(pcr);
204
205 return 0;
206}
207
208static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
209{
210 int err;
211 u16 val = 0;
212
213 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
214 RTS5261_PUPDC, RTS5261_PUPDC);
215
216 switch (voltage) {
217 case OUTPUT_3V3:
218 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
219 val |= PHY_TUNE_SDBUS_33;
220 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
221 if (err < 0)
222 return err;
223
224 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
225 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
226 rtsx_pci_write_register(pcr, SD_PAD_CTL,
227 SD_IO_USING_1V8, 0);
228 break;
229 case OUTPUT_1V8:
230 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
231 val &= ~PHY_TUNE_SDBUS_33;
232 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
233 if (err < 0)
234 return err;
235
236 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
237 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
238 rtsx_pci_write_register(pcr, SD_PAD_CTL,
239 SD_IO_USING_1V8, SD_IO_USING_1V8);
240 break;
241 default:
242 return -EINVAL;
243 }
244
245
246 rts5261_fill_driving(pcr, voltage);
247
248 return 0;
249}
250
251static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
252{
253 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
254 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
255 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
256 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
257 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
258 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
259}
260
261static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
262{
263 rts5261_stop_cmd(pcr);
264 rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
265
266}
267
268static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
269{
270 u8 val = 0;
271
272 val = SD_OCP_INT_EN | SD_DETECT_EN;
273 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
274
275}
276
277static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
278{
279 u8 mask = 0;
280
281 mask = SD_OCP_INT_EN | SD_DETECT_EN;
282 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
283 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
284 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
285
286}
287
288static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
289{
290 int err = 0;
291
292 rts5261_card_before_power_off(pcr);
293 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
294 RTS5261_LDO_POWERON_MASK, 0);
295
296 if (pcr->option.ocp_en)
297 rtsx_pci_disable_ocp(pcr);
298
299 return err;
300}
301
302static void rts5261_init_ocp(struct rtsx_pcr *pcr)
303{
304 struct rtsx_cr_option *option = &pcr->option;
305
306 if (option->ocp_en) {
307 u8 mask, val;
308
309 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
310 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
311 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
312
313 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
314 RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
315
316 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
317 RTS5261_LDO1_OCP_LMT_THD_MASK,
318 RTS5261_LDO1_LMT_THD_2000);
319
320 mask = SD_OCP_GLITCH_MASK;
321 val = pcr->hw_param.ocp_glitch;
322 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
323
324 rts5261_enable_ocp(pcr);
325 } else {
326 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
327 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
328 }
329}
330
331static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
332{
333 u8 mask = 0;
334 u8 val = 0;
335
336 mask = SD_OCP_INT_CLR | SD_OC_CLR;
337 val = SD_OCP_INT_CLR | SD_OC_CLR;
338
339 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
340
341 udelay(10);
342 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
343
344}
345
346static void rts5261_process_ocp(struct rtsx_pcr *pcr)
347{
348 if (!pcr->option.ocp_en)
349 return;
350
351 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
352
353 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
354 rts5261_card_power_off(pcr, RTSX_SD_CARD);
355 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
356 rts5261_clear_ocpstat(pcr);
357 pcr->ocp_stat = 0;
358 }
359
360}
361
362static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
363{
364 int retval;
365 u32 lval, i;
366 u8 valid, efuse_valid, tmp;
367
368 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
369 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
370 REG_EFUSE_POR | REG_EFUSE_POWERON);
371 udelay(1);
372 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
373 RTS5261_EFUSE_ADDR_MASK, 0x00);
374 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
375 RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
376 RTS5261_EFUSE_ENABLE);
377
378
379 for (i = 0; i < MAX_RW_REG_CNT; i++) {
380 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
381 if ((tmp & 0x80) == 0)
382 break;
383 }
384 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
385 efuse_valid = ((tmp & 0x0C) >> 2);
386 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
387
388 if (efuse_valid == 0) {
389 retval = rtsx_pci_read_config_dword(pcr,
390 PCR_SETTING_REG2, &lval);
391 if (retval != 0)
392 pcr_dbg(pcr, "read 0x814 DW fail\n");
393 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
394
395 valid = (u8)((lval >> 16) & 0x03);
396 pcr_dbg(pcr, "0x816: %d\n", valid);
397 }
398 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
399 REG_EFUSE_POR, 0);
400 pcr_dbg(pcr, "Disable efuse por!\n");
401
402 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &lval);
403 lval = lval & 0x00FFFFFF;
404 retval = rtsx_pci_write_config_dword(pcr, PCR_SETTING_REG2, lval);
405 if (retval != 0)
406 pcr_dbg(pcr, "write config fail\n");
407
408 return retval;
409}
410
411static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
412{
413 u32 lval;
414 struct rtsx_cr_option *option = &pcr->option;
415
416 rtsx_pci_read_config_dword(pcr, PCR_ASPM_SETTING_REG1, &lval);
417
418 if (lval & ASPM_L1_1_EN_MASK)
419 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
420 else
421 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
422
423 if (lval & ASPM_L1_2_EN_MASK)
424 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
425 else
426 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
427
428 if (lval & PM_L1_1_EN_MASK)
429 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
430 else
431 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
432
433 if (lval & PM_L1_2_EN_MASK)
434 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
435 else
436 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
437
438 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
439 if (option->ltr_en) {
440 u16 val;
441
442 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
443 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
444 option->ltr_enabled = true;
445 option->ltr_active = true;
446 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
447 } else {
448 option->ltr_enabled = false;
449 }
450 }
451
452 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
453 | PM_L1_1_EN | PM_L1_2_EN))
454 option->force_clkreq_0 = false;
455 else
456 option->force_clkreq_0 = true;
457}
458
459static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
460{
461 struct rtsx_cr_option *option = &pcr->option;
462
463 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
464 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
465
466 rts5261_init_from_cfg(pcr);
467 rts5261_init_from_hw(pcr);
468
469
470 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
471 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
472 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
473 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
474 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
475
476 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
477 RTS5261_AUX_CLK_16M_EN, 0);
478
479
480 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
481 RTS5261_FORCE_PRSNT_LOW, 0);
482 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
483 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
484
485 rtsx_pci_write_register(pcr, PCLK_CTL,
486 PCLK_MODE_SEL, PCLK_MODE_SEL);
487
488 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
489 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
490
491
492 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
493
494
495 rts5261_fill_driving(pcr, OUTPUT_3V3);
496
497
498
499
500
501 if (option->force_clkreq_0)
502 rtsx_pci_write_register(pcr, PETXCFG,
503 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
504 else
505 rtsx_pci_write_register(pcr, PETXCFG,
506 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
507
508 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
509 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
510 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
511
512
513 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
514 RTS5261_INFORM_RTD3_COLD, 0);
515
516 return 0;
517}
518
519static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
520{
521 struct rtsx_cr_option *option = &pcr->option;
522 u8 val = 0;
523
524 if (pcr->aspm_enabled == enable)
525 return;
526
527 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
528 val = pcr->aspm_en;
529 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
530 ASPM_MASK_NEG, val);
531 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
532 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
533
534 val = FORCE_ASPM_CTL0;
535 val |= (pcr->aspm_en & 0x02);
536 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
537 val = pcr->aspm_en;
538 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
539 ASPM_MASK_NEG, val);
540 }
541 pcr->aspm_enabled = enable;
542
543}
544
545static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
546{
547 struct rtsx_cr_option *option = &pcr->option;
548 u8 val = 0;
549
550 if (pcr->aspm_enabled == enable)
551 return;
552
553 if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) {
554 val = 0;
555 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
556 ASPM_MASK_NEG, val);
557 } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) {
558 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0;
559
560 val = 0;
561 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
562 ASPM_MASK_NEG, val);
563 val = FORCE_ASPM_CTL0;
564 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
565 }
566 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
567 udelay(10);
568 pcr->aspm_enabled = enable;
569}
570
571static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
572{
573 if (enable)
574 rts5261_enable_aspm(pcr, true);
575 else
576 rts5261_disable_aspm(pcr, false);
577}
578
579static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
580{
581 struct rtsx_cr_option *option = &pcr->option;
582 int aspm_L1_1, aspm_L1_2;
583 u8 val = 0;
584
585 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
586 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
587
588 if (active) {
589
590 if (aspm_L1_1)
591 val = option->ltr_l1off_snooze_sspwrgate;
592 } else {
593
594 if (aspm_L1_2)
595 val = option->ltr_l1off_sspwrgate;
596 }
597
598 rtsx_set_l1off_sub(pcr, val);
599}
600
601static const struct pcr_ops rts5261_pcr_ops = {
602 .fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
603 .turn_on_led = rts5261_turn_on_led,
604 .turn_off_led = rts5261_turn_off_led,
605 .extra_init_hw = rts5261_extra_init_hw,
606 .enable_auto_blink = rts5261_enable_auto_blink,
607 .disable_auto_blink = rts5261_disable_auto_blink,
608 .card_power_on = rts5261_card_power_on,
609 .card_power_off = rts5261_card_power_off,
610 .switch_output_voltage = rts5261_switch_output_voltage,
611 .force_power_down = rts5261_force_power_down,
612 .stop_cmd = rts5261_stop_cmd,
613 .set_aspm = rts5261_set_aspm,
614 .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
615 .enable_ocp = rts5261_enable_ocp,
616 .disable_ocp = rts5261_disable_ocp,
617 .init_ocp = rts5261_init_ocp,
618 .process_ocp = rts5261_process_ocp,
619 .clear_ocpstat = rts5261_clear_ocpstat,
620};
621
622static inline u8 double_ssc_depth(u8 depth)
623{
624 return ((depth > 1) ? (depth - 1) : depth);
625}
626
627int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
628 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
629{
630 int err, clk;
631 u8 n, clk_divider, mcu_cnt, div;
632 static const u8 depth[] = {
633 [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
634 [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
635 [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
636 [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
637 };
638
639 if (initial_mode) {
640
641 clk_divider = SD_CLK_DIVIDE_128;
642 card_clock = 30000000;
643 } else {
644 clk_divider = SD_CLK_DIVIDE_0;
645 }
646 err = rtsx_pci_write_register(pcr, SD_CFG1,
647 SD_CLK_DIVIDE_MASK, clk_divider);
648 if (err < 0)
649 return err;
650
651 card_clock /= 1000000;
652 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
653
654 clk = card_clock;
655 if (!initial_mode && double_clk)
656 clk = card_clock * 2;
657 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
658 clk, pcr->cur_clock);
659
660 if (clk == pcr->cur_clock)
661 return 0;
662
663 if (pcr->ops->conv_clk_and_div_n)
664 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
665 else
666 n = (u8)(clk - 4);
667 if ((clk <= 4) || (n > 396))
668 return -EINVAL;
669
670 mcu_cnt = (u8)(125/clk + 3);
671 if (mcu_cnt > 15)
672 mcu_cnt = 15;
673
674 div = CLK_DIV_1;
675 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
676 if (pcr->ops->conv_clk_and_div_n) {
677 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
678 DIV_N_TO_CLK) * 2;
679 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
680 CLK_TO_DIV_N);
681 } else {
682 n = (n + 4) * 2 - 4;
683 }
684 div++;
685 }
686
687 n = (n / 2);
688 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
689
690 ssc_depth = depth[ssc_depth];
691 if (double_clk)
692 ssc_depth = double_ssc_depth(ssc_depth);
693
694 if (ssc_depth) {
695 if (div == CLK_DIV_2) {
696 if (ssc_depth > 1)
697 ssc_depth -= 1;
698 else
699 ssc_depth = RTS5261_SSC_DEPTH_8M;
700 } else if (div == CLK_DIV_4) {
701 if (ssc_depth > 2)
702 ssc_depth -= 2;
703 else
704 ssc_depth = RTS5261_SSC_DEPTH_8M;
705 } else if (div == CLK_DIV_8) {
706 if (ssc_depth > 3)
707 ssc_depth -= 3;
708 else
709 ssc_depth = RTS5261_SSC_DEPTH_8M;
710 }
711 } else {
712 ssc_depth = 0;
713 }
714 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
715
716 rtsx_pci_init_cmd(pcr);
717 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
718 CLK_LOW_FREQ, CLK_LOW_FREQ);
719 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
720 0xFF, (div << 4) | mcu_cnt);
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
722 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
723 SSC_DEPTH_MASK, ssc_depth);
724 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
725 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
726 if (vpclk) {
727 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
728 PHASE_NOT_RESET, 0);
729 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
730 PHASE_NOT_RESET, 0);
731 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
732 PHASE_NOT_RESET, PHASE_NOT_RESET);
733 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
734 PHASE_NOT_RESET, PHASE_NOT_RESET);
735 }
736
737 err = rtsx_pci_send_cmd(pcr, 2000);
738 if (err < 0)
739 return err;
740
741
742 udelay(SSC_CLOCK_STABLE_WAIT);
743 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
744 if (err < 0)
745 return err;
746
747 pcr->cur_clock = clk;
748 return 0;
749
750}
751
752void rts5261_init_params(struct rtsx_pcr *pcr)
753{
754 struct rtsx_cr_option *option = &pcr->option;
755 struct rtsx_hw_param *hw_param = &pcr->hw_param;
756
757 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
758 pcr->num_slots = 1;
759 pcr->ops = &rts5261_pcr_ops;
760
761 pcr->flags = 0;
762 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
763 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
764 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
765 pcr->aspm_en = ASPM_L1_EN;
766 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 27, 16);
767 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
768
769 pcr->ic_version = rts5261_get_ic_version(pcr);
770 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
771 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
772
773 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
774
775 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
776 | LTR_L1SS_PWR_GATE_EN);
777 option->ltr_en = true;
778
779
780 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
781 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
782 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
783 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
784 option->ltr_l1off_sspwrgate = 0x7F;
785 option->ltr_l1off_snooze_sspwrgate = 0x78;
786 option->dev_aspm_mode = DEV_ASPM_DYNAMIC;
787
788 option->ocp_en = 1;
789 hw_param->interrupt_en |= SD_OC_INT_EN;
790 hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
791 option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
792}
793
