1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2013 - 2018 Intel Corporation. */ 3 4#ifndef _I40E_DCB_H_ 5#define _I40E_DCB_H_ 6 7#include "i40e_type.h" 8 9#define I40E_DCBX_STATUS_NOT_STARTED 0 10#define I40E_DCBX_STATUS_IN_PROGRESS 1 11#define I40E_DCBX_STATUS_DONE 2 12#define I40E_DCBX_STATUS_MULTIPLE_PEERS 3 13#define I40E_DCBX_STATUS_DISABLED 7 14 15#define I40E_TLV_TYPE_END 0 16#define I40E_TLV_TYPE_ORG 127 17 18#define I40E_IEEE_8021QAZ_OUI 0x0080C2 19#define I40E_IEEE_SUBTYPE_ETS_CFG 9 20#define I40E_IEEE_SUBTYPE_ETS_REC 10 21#define I40E_IEEE_SUBTYPE_PFC_CFG 11 22#define I40E_IEEE_SUBTYPE_APP_PRI 12 23 24#define I40E_CEE_DCBX_OUI 0x001b21 25#define I40E_CEE_DCBX_TYPE 2 26 27#define I40E_CEE_SUBTYPE_CTRL 1 28#define I40E_CEE_SUBTYPE_PG_CFG 2 29#define I40E_CEE_SUBTYPE_PFC_CFG 3 30#define I40E_CEE_SUBTYPE_APP_PRI 4 31 32#define I40E_CEE_MAX_FEAT_TYPE 3 33#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B 34#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x31 35#define I40E_LLDP_CURRENT_STATUS_OFFSET 1 36#define I40E_LLDP_CURRENT_STATUS_SIZE 1 37 38/* Defines for LLDP TLV header */ 39#define I40E_LLDP_TLV_LEN_SHIFT 0 40#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT) 41#define I40E_LLDP_TLV_TYPE_SHIFT 9 42#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT) 43#define I40E_LLDP_TLV_SUBTYPE_SHIFT 0 44#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT) 45#define I40E_LLDP_TLV_OUI_SHIFT 8 46#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT) 47 48/* Defines for IEEE ETS TLV */ 49#define I40E_IEEE_ETS_MAXTC_SHIFT 0 50#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT) 51#define I40E_IEEE_ETS_CBS_SHIFT 6 52#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT) 53#define I40E_IEEE_ETS_WILLING_SHIFT 7 54#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT) 55#define I40E_IEEE_ETS_PRIO_0_SHIFT 0 56#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT) 57#define I40E_IEEE_ETS_PRIO_1_SHIFT 4 58#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT) 59#define I40E_CEE_PGID_PRIO_0_SHIFT 0 60#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT) 61#define I40E_CEE_PGID_PRIO_1_SHIFT 4 62#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT) 63#define I40E_CEE_PGID_STRICT 15 64 65/* Defines for IEEE TSA types */ 66#define I40E_IEEE_TSA_STRICT 0 67#define I40E_IEEE_TSA_ETS 2 68 69/* Defines for IEEE PFC TLV */ 70#define I40E_IEEE_PFC_CAP_SHIFT 0 71#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT) 72#define I40E_IEEE_PFC_MBC_SHIFT 6 73#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT) 74#define I40E_IEEE_PFC_WILLING_SHIFT 7 75#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT) 76 77/* Defines for IEEE APP TLV */ 78#define I40E_IEEE_APP_SEL_SHIFT 0 79#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT) 80#define I40E_IEEE_APP_PRIO_SHIFT 5 81#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT) 82 83 84#pragma pack(1) 85 86/* IEEE 802.1AB LLDP Organization specific TLV */ 87struct i40e_lldp_org_tlv { 88 __be16 typelength; 89 __be32 ouisubtype; 90 u8 tlvinfo[1]; 91}; 92 93struct i40e_cee_tlv_hdr { 94 __be16 typelen; 95 u8 operver; 96 u8 maxver; 97}; 98 99struct i40e_cee_ctrl_tlv { 100 struct i40e_cee_tlv_hdr hdr; 101 __be32 seqno; 102 __be32 ackno; 103}; 104 105struct i40e_cee_feat_tlv { 106 struct i40e_cee_tlv_hdr hdr; 107 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */ 108#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80 109#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40 110#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20 111 u8 subtype; 112 u8 tlvinfo[1]; 113}; 114 115struct i40e_cee_app_prio { 116 __be16 protocol; 117 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */ 118#define I40E_CEE_APP_SELECTOR_MASK 0x03 119 __be16 lower_oui; 120 u8 prio_map; 121}; 122#pragma pack() 123 124i40e_status i40e_get_dcbx_status(struct i40e_hw *hw, 125 u16 *status); 126i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib, 127 struct i40e_dcbx_config *dcbcfg); 128i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type, 129 u8 bridgetype, 130 struct i40e_dcbx_config *dcbcfg); 131i40e_status i40e_get_dcb_config(struct i40e_hw *hw); 132i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change); 133#endif /* _I40E_DCB_H_ */ 134