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15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21#include <linux/slab.h>
22#include <linux/dma-mapping.h>
23#include <linux/delay.h>
24#include <linux/sched.h>
25#include <linux/skbuff.h>
26#include <linux/netdevice.h>
27#include <linux/firmware.h>
28#include <linux/etherdevice.h>
29#include <linux/if_arp.h>
30
31#include <net/ieee80211_radiotap.h>
32#include <net/mac80211.h>
33
34#include <asm/div64.h>
35
36#define DRV_NAME "iwl3945"
37
38#include "commands.h"
39#include "common.h"
40#include "3945.h"
41#include "iwl-spectrum.h"
42
43
44
45
46
47#define DRV_DESCRIPTION \
48"Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
49
50#ifdef CONFIG_IWLEGACY_DEBUG
51#define VD "d"
52#else
53#define VD
54#endif
55
56
57
58
59
60
61#define DRV_VERSION IWLWIFI_VERSION VD "s"
62#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
63#define DRV_AUTHOR "<ilw@linux.intel.com>"
64
65MODULE_DESCRIPTION(DRV_DESCRIPTION);
66MODULE_VERSION(DRV_VERSION);
67MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
68MODULE_LICENSE("GPL");
69
70
71struct il_mod_params il3945_mod_params = {
72 .sw_crypto = 1,
73 .restart_fw = 1,
74 .disable_hw_scan = 1,
75
76};
77
78
79
80
81
82
83
84
85
86
87
88
89__le32
90il3945_get_antenna_flags(const struct il_priv *il)
91{
92 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
93
94 switch (il3945_mod_params.antenna) {
95 case IL_ANTENNA_DIVERSITY:
96 return 0;
97
98 case IL_ANTENNA_MAIN:
99 if (eeprom->antenna_switch_type)
100 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
101 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
102
103 case IL_ANTENNA_AUX:
104 if (eeprom->antenna_switch_type)
105 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
106 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
107 }
108
109
110 IL_ERR("Bad antenna selector value (0x%x)\n",
111 il3945_mod_params.antenna);
112
113 return 0;
114}
115
116static int
117il3945_set_ccmp_dynamic_key_info(struct il_priv *il,
118 struct ieee80211_key_conf *keyconf, u8 sta_id)
119{
120 unsigned long flags;
121 __le16 key_flags = 0;
122 int ret;
123
124 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
125 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
126
127 if (sta_id == il->hw_params.bcast_id)
128 key_flags |= STA_KEY_MULTICAST_MSK;
129
130 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
131 keyconf->hw_key_idx = keyconf->keyidx;
132 key_flags &= ~STA_KEY_FLG_INVALID;
133
134 spin_lock_irqsave(&il->sta_lock, flags);
135 il->stations[sta_id].keyinfo.cipher = keyconf->cipher;
136 il->stations[sta_id].keyinfo.keylen = keyconf->keylen;
137 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen);
138
139 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen);
140
141 if ((il->stations[sta_id].sta.key.
142 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC)
143 il->stations[sta_id].sta.key.key_offset =
144 il_get_free_ucode_key_idx(il);
145
146
147
148 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
149 "no space for a new key");
150
151 il->stations[sta_id].sta.key.key_flags = key_flags;
152 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
153 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
154
155 D_INFO("hwcrypto: modify ucode station key info\n");
156
157 ret = il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC);
158
159 spin_unlock_irqrestore(&il->sta_lock, flags);
160
161 return ret;
162}
163
164static int
165il3945_set_tkip_dynamic_key_info(struct il_priv *il,
166 struct ieee80211_key_conf *keyconf, u8 sta_id)
167{
168 return -EOPNOTSUPP;
169}
170
171static int
172il3945_set_wep_dynamic_key_info(struct il_priv *il,
173 struct ieee80211_key_conf *keyconf, u8 sta_id)
174{
175 return -EOPNOTSUPP;
176}
177
178static int
179il3945_clear_sta_key_info(struct il_priv *il, u8 sta_id)
180{
181 unsigned long flags;
182 struct il_addsta_cmd sta_cmd;
183
184 spin_lock_irqsave(&il->sta_lock, flags);
185 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key));
186 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo));
187 il->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
188 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
189 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
190 memcpy(&sta_cmd, &il->stations[sta_id].sta,
191 sizeof(struct il_addsta_cmd));
192 spin_unlock_irqrestore(&il->sta_lock, flags);
193
194 D_INFO("hwcrypto: clear ucode station key info\n");
195 return il_send_add_sta(il, &sta_cmd, CMD_SYNC);
196}
197
198static int
199il3945_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf,
200 u8 sta_id)
201{
202 int ret = 0;
203
204 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
205
206 switch (keyconf->cipher) {
207 case WLAN_CIPHER_SUITE_CCMP:
208 ret = il3945_set_ccmp_dynamic_key_info(il, keyconf, sta_id);
209 break;
210 case WLAN_CIPHER_SUITE_TKIP:
211 ret = il3945_set_tkip_dynamic_key_info(il, keyconf, sta_id);
212 break;
213 case WLAN_CIPHER_SUITE_WEP40:
214 case WLAN_CIPHER_SUITE_WEP104:
215 ret = il3945_set_wep_dynamic_key_info(il, keyconf, sta_id);
216 break;
217 default:
218 IL_ERR("Unknown alg: %s alg=%x\n", __func__, keyconf->cipher);
219 ret = -EINVAL;
220 }
221
222 D_WEP("Set dynamic key: alg=%x len=%d idx=%d sta=%d ret=%d\n",
223 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret);
224
225 return ret;
226}
227
228static int
229il3945_remove_static_key(struct il_priv *il)
230{
231 int ret = -EOPNOTSUPP;
232
233 return ret;
234}
235
236static int
237il3945_set_static_key(struct il_priv *il, struct ieee80211_key_conf *key)
238{
239 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
240 key->cipher == WLAN_CIPHER_SUITE_WEP104)
241 return -EOPNOTSUPP;
242
243 IL_ERR("Static key invalid: cipher %x\n", key->cipher);
244 return -EINVAL;
245}
246
247static void
248il3945_clear_free_frames(struct il_priv *il)
249{
250 struct list_head *element;
251
252 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count);
253
254 while (!list_empty(&il->free_frames)) {
255 element = il->free_frames.next;
256 list_del(element);
257 kfree(list_entry(element, struct il3945_frame, list));
258 il->frames_count--;
259 }
260
261 if (il->frames_count) {
262 IL_WARN("%d frames still in use. Did we lose one?\n",
263 il->frames_count);
264 il->frames_count = 0;
265 }
266}
267
268static struct il3945_frame *
269il3945_get_free_frame(struct il_priv *il)
270{
271 struct il3945_frame *frame;
272 struct list_head *element;
273 if (list_empty(&il->free_frames)) {
274 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
275 if (!frame) {
276 IL_ERR("Could not allocate frame!\n");
277 return NULL;
278 }
279
280 il->frames_count++;
281 return frame;
282 }
283
284 element = il->free_frames.next;
285 list_del(element);
286 return list_entry(element, struct il3945_frame, list);
287}
288
289static void
290il3945_free_frame(struct il_priv *il, struct il3945_frame *frame)
291{
292 memset(frame, 0, sizeof(*frame));
293 list_add(&frame->list, &il->free_frames);
294}
295
296unsigned int
297il3945_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr,
298 int left)
299{
300
301 if (!il_is_associated(il) || !il->beacon_skb)
302 return 0;
303
304 if (il->beacon_skb->len > left)
305 return 0;
306
307 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len);
308
309 return il->beacon_skb->len;
310}
311
312static int
313il3945_send_beacon_cmd(struct il_priv *il)
314{
315 struct il3945_frame *frame;
316 unsigned int frame_size;
317 int rc;
318 u8 rate;
319
320 frame = il3945_get_free_frame(il);
321
322 if (!frame) {
323 IL_ERR("Could not obtain free frame buffer for beacon "
324 "command.\n");
325 return -ENOMEM;
326 }
327
328 rate = il_get_lowest_plcp(il);
329
330 frame_size = il3945_hw_get_beacon_cmd(il, frame, rate);
331
332 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]);
333
334 il3945_free_frame(il, frame);
335
336 return rc;
337}
338
339static void
340il3945_unset_hw_params(struct il_priv *il)
341{
342 if (il->_3945.shared_virt)
343 dma_free_coherent(&il->pci_dev->dev,
344 sizeof(struct il3945_shared),
345 il->_3945.shared_virt, il->_3945.shared_phys);
346}
347
348static void
349il3945_build_tx_cmd_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info,
350 struct il_device_cmd *cmd,
351 struct sk_buff *skb_frag, int sta_id)
352{
353 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
354 struct il_hw_key *keyinfo = &il->stations[sta_id].keyinfo;
355
356 tx_cmd->sec_ctl = 0;
357
358 switch (keyinfo->cipher) {
359 case WLAN_CIPHER_SUITE_CCMP:
360 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
361 memcpy(tx_cmd->key, keyinfo->key, keyinfo->keylen);
362 D_TX("tx_cmd with AES hwcrypto\n");
363 break;
364
365 case WLAN_CIPHER_SUITE_TKIP:
366 break;
367
368 case WLAN_CIPHER_SUITE_WEP104:
369 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
370
371 case WLAN_CIPHER_SUITE_WEP40:
372 tx_cmd->sec_ctl |=
373 TX_CMD_SEC_WEP | (info->control.hw_key->
374 hw_key_idx & TX_CMD_SEC_MSK) <<
375 TX_CMD_SEC_SHIFT;
376
377 memcpy(&tx_cmd->key[3], keyinfo->key, keyinfo->keylen);
378
379 D_TX("Configuring packet for WEP encryption " "with key %d\n",
380 info->control.hw_key->hw_key_idx);
381 break;
382
383 default:
384 IL_ERR("Unknown encode cipher %x\n", keyinfo->cipher);
385 break;
386 }
387}
388
389
390
391
392static void
393il3945_build_tx_cmd_basic(struct il_priv *il, struct il_device_cmd *cmd,
394 struct ieee80211_tx_info *info,
395 struct ieee80211_hdr *hdr, u8 std_id)
396{
397 struct il3945_tx_cmd *tx_cmd = (struct il3945_tx_cmd *)cmd->cmd.payload;
398 __le32 tx_flags = tx_cmd->tx_flags;
399 __le16 fc = hdr->frame_control;
400
401 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
402 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
403 tx_flags |= TX_CMD_FLG_ACK_MSK;
404 if (ieee80211_is_mgmt(fc))
405 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
406 if (ieee80211_is_probe_resp(fc) &&
407 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
408 tx_flags |= TX_CMD_FLG_TSF_MSK;
409 } else {
410 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
411 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
412 }
413
414 tx_cmd->sta_id = std_id;
415 if (ieee80211_has_morefrags(fc))
416 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
417
418 if (ieee80211_is_data_qos(fc)) {
419 u8 *qc = ieee80211_get_qos_ctl(hdr);
420 tx_cmd->tid_tspec = qc[0] & 0xf;
421 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
422 } else {
423 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
424 }
425
426 il_tx_cmd_protection(il, info, fc, &tx_flags);
427
428 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
429 if (ieee80211_is_mgmt(fc)) {
430 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
431 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
432 else
433 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
434 } else {
435 tx_cmd->timeout.pm_frame_timeout = 0;
436 }
437
438 tx_cmd->driver_txop = 0;
439 tx_cmd->tx_flags = tx_flags;
440 tx_cmd->next_frame_len = 0;
441}
442
443
444
445
446static int
447il3945_tx_skb(struct il_priv *il,
448 struct ieee80211_sta *sta,
449 struct sk_buff *skb)
450{
451 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
452 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
453 struct il3945_tx_cmd *tx_cmd;
454 struct il_tx_queue *txq = NULL;
455 struct il_queue *q = NULL;
456 struct il_device_cmd *out_cmd;
457 struct il_cmd_meta *out_meta;
458 dma_addr_t phys_addr;
459 dma_addr_t txcmd_phys;
460 int txq_id = skb_get_queue_mapping(skb);
461 u16 len, idx, hdr_len;
462 u16 firstlen, secondlen;
463 u8 sta_id;
464 u8 tid = 0;
465 __le16 fc;
466 u8 wait_write_ptr = 0;
467 unsigned long flags;
468
469 spin_lock_irqsave(&il->lock, flags);
470 if (il_is_rfkill(il)) {
471 D_DROP("Dropping - RF KILL\n");
472 goto drop_unlock;
473 }
474
475 if ((ieee80211_get_tx_rate(il->hw, info)->hw_value & 0xFF) ==
476 IL_INVALID_RATE) {
477 IL_ERR("ERROR: No TX rate available.\n");
478 goto drop_unlock;
479 }
480
481 fc = hdr->frame_control;
482
483#ifdef CONFIG_IWLEGACY_DEBUG
484 if (ieee80211_is_auth(fc))
485 D_TX("Sending AUTH frame\n");
486 else if (ieee80211_is_assoc_req(fc))
487 D_TX("Sending ASSOC frame\n");
488 else if (ieee80211_is_reassoc_req(fc))
489 D_TX("Sending REASSOC frame\n");
490#endif
491
492 spin_unlock_irqrestore(&il->lock, flags);
493
494 hdr_len = ieee80211_hdrlen(fc);
495
496
497 sta_id = il_sta_id_or_broadcast(il, sta);
498 if (sta_id == IL_INVALID_STATION) {
499 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1);
500 goto drop;
501 }
502
503 D_RATE("station Id %d\n", sta_id);
504
505 if (ieee80211_is_data_qos(fc)) {
506 u8 *qc = ieee80211_get_qos_ctl(hdr);
507 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
508 if (unlikely(tid >= MAX_TID_COUNT))
509 goto drop;
510 }
511
512
513 txq = &il->txq[txq_id];
514 q = &txq->q;
515
516 if ((il_queue_space(q) < q->high_mark))
517 goto drop;
518
519 spin_lock_irqsave(&il->lock, flags);
520
521 idx = il_get_cmd_idx(q, q->write_ptr, 0);
522
523 txq->skbs[q->write_ptr] = skb;
524
525
526 out_cmd = txq->cmd[idx];
527 out_meta = &txq->meta[idx];
528 tx_cmd = (struct il3945_tx_cmd *)out_cmd->cmd.payload;
529 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
530 memset(tx_cmd, 0, sizeof(*tx_cmd));
531
532
533
534
535
536
537
538 out_cmd->hdr.cmd = C_TX;
539 out_cmd->hdr.sequence =
540 cpu_to_le16((u16)
541 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr)));
542
543
544 memcpy(tx_cmd->hdr, hdr, hdr_len);
545
546 if (info->control.hw_key)
547 il3945_build_tx_cmd_hwcrypto(il, info, out_cmd, skb, sta_id);
548
549
550 il3945_build_tx_cmd_basic(il, out_cmd, info, hdr, sta_id);
551
552 il3945_hw_build_tx_cmd_rate(il, out_cmd, info, hdr, sta_id);
553
554
555 tx_cmd->len = cpu_to_le16((u16) skb->len);
556
557 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
558 tx_cmd->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
559
560
561
562
563
564
565
566
567
568
569 len =
570 sizeof(struct il3945_tx_cmd) + sizeof(struct il_cmd_header) +
571 hdr_len;
572 firstlen = (len + 3) & ~3;
573
574
575
576 txcmd_phys =
577 pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen,
578 PCI_DMA_TODEVICE);
579 if (unlikely(pci_dma_mapping_error(il->pci_dev, txcmd_phys)))
580 goto drop_unlock;
581
582
583
584 secondlen = skb->len - hdr_len;
585 if (secondlen > 0) {
586 phys_addr =
587 pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen,
588 PCI_DMA_TODEVICE);
589 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr)))
590 goto drop_unlock;
591 }
592
593
594
595 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0);
596 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
597 dma_unmap_len_set(out_meta, len, firstlen);
598 if (secondlen > 0)
599 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 0,
600 U32_PAD(secondlen));
601
602 if (!ieee80211_has_morefrags(hdr->frame_control)) {
603 txq->need_update = 1;
604 } else {
605 wait_write_ptr = 1;
606 txq->need_update = 0;
607 }
608
609 il_update_stats(il, true, fc, skb->len);
610
611 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence));
612 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
613 il_print_hex_dump(il, IL_DL_TX, tx_cmd, sizeof(*tx_cmd));
614 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr,
615 ieee80211_hdrlen(fc));
616
617
618 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
619 il_txq_update_write_ptr(il, txq);
620 spin_unlock_irqrestore(&il->lock, flags);
621
622 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
623 if (wait_write_ptr) {
624 spin_lock_irqsave(&il->lock, flags);
625 txq->need_update = 1;
626 il_txq_update_write_ptr(il, txq);
627 spin_unlock_irqrestore(&il->lock, flags);
628 }
629
630 il_stop_queue(il, txq);
631 }
632
633 return 0;
634
635drop_unlock:
636 spin_unlock_irqrestore(&il->lock, flags);
637drop:
638 return -1;
639}
640
641static int
642il3945_get_measurement(struct il_priv *il,
643 struct ieee80211_measurement_params *params, u8 type)
644{
645 struct il_spectrum_cmd spectrum;
646 struct il_rx_pkt *pkt;
647 struct il_host_cmd cmd = {
648 .id = C_SPECTRUM_MEASUREMENT,
649 .data = (void *)&spectrum,
650 .flags = CMD_WANT_SKB,
651 };
652 u32 add_time = le64_to_cpu(params->start_time);
653 int rc;
654 int spectrum_resp_status;
655 int duration = le16_to_cpu(params->duration);
656
657 if (il_is_associated(il))
658 add_time =
659 il_usecs_to_beacons(il,
660 le64_to_cpu(params->start_time) -
661 il->_3945.last_tsf,
662 le16_to_cpu(il->timing.beacon_interval));
663
664 memset(&spectrum, 0, sizeof(spectrum));
665
666 spectrum.channel_count = cpu_to_le16(1);
667 spectrum.flags =
668 RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
669 spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
670 cmd.len = sizeof(spectrum);
671 spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
672
673 if (il_is_associated(il))
674 spectrum.start_time =
675 il_add_beacon_time(il, il->_3945.last_beacon_time, add_time,
676 le16_to_cpu(il->timing.beacon_interval));
677 else
678 spectrum.start_time = 0;
679
680 spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
681 spectrum.channels[0].channel = params->channel;
682 spectrum.channels[0].type = type;
683 if (il->active.flags & RXON_FLG_BAND_24G_MSK)
684 spectrum.flags |=
685 RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
686 RXON_FLG_TGG_PROTECT_MSK;
687
688 rc = il_send_cmd_sync(il, &cmd);
689 if (rc)
690 return rc;
691
692 pkt = (struct il_rx_pkt *)cmd.reply_page;
693 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
694 IL_ERR("Bad return from N_RX_ON_ASSOC command\n");
695 rc = -EIO;
696 }
697
698 spectrum_resp_status = le16_to_cpu(pkt->u.spectrum.status);
699 switch (spectrum_resp_status) {
700 case 0:
701 if (pkt->u.spectrum.id != 0xff) {
702 D_INFO("Replaced existing measurement: %d\n",
703 pkt->u.spectrum.id);
704 il->measurement_status &= ~MEASUREMENT_READY;
705 }
706 il->measurement_status |= MEASUREMENT_ACTIVE;
707 rc = 0;
708 break;
709
710 case 1:
711 rc = -EAGAIN;
712 break;
713 }
714
715 il_free_pages(il, cmd.reply_page);
716
717 return rc;
718}
719
720static void
721il3945_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb)
722{
723 struct il_rx_pkt *pkt = rxb_addr(rxb);
724 struct il_alive_resp *palive;
725 struct delayed_work *pwork;
726
727 palive = &pkt->u.alive_frame;
728
729 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n",
730 palive->is_valid, palive->ver_type, palive->ver_subtype);
731
732 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
733 D_INFO("Initialization Alive received.\n");
734 memcpy(&il->card_alive_init, &pkt->u.alive_frame,
735 sizeof(struct il_alive_resp));
736 pwork = &il->init_alive_start;
737 } else {
738 D_INFO("Runtime Alive received.\n");
739 memcpy(&il->card_alive, &pkt->u.alive_frame,
740 sizeof(struct il_alive_resp));
741 pwork = &il->alive_start;
742 il3945_disable_events(il);
743 }
744
745
746
747 if (palive->is_valid == UCODE_VALID_OK)
748 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5));
749 else
750 IL_WARN("uCode did not respond OK.\n");
751}
752
753static void
754il3945_hdl_add_sta(struct il_priv *il, struct il_rx_buf *rxb)
755{
756#ifdef CONFIG_IWLEGACY_DEBUG
757 struct il_rx_pkt *pkt = rxb_addr(rxb);
758#endif
759
760 D_RX("Received C_ADD_STA: 0x%02X\n", pkt->u.status);
761}
762
763static void
764il3945_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb)
765{
766 struct il_rx_pkt *pkt = rxb_addr(rxb);
767 struct il3945_beacon_notif *beacon = &(pkt->u.beacon_status);
768#ifdef CONFIG_IWLEGACY_DEBUG
769 u8 rate = beacon->beacon_notify_hdr.rate;
770
771 D_RX("beacon status %x retries %d iss %d " "tsf %d %d rate %d\n",
772 le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
773 beacon->beacon_notify_hdr.failure_frame,
774 le32_to_cpu(beacon->ibss_mgr_status),
775 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate);
776#endif
777
778 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
779
780}
781
782
783
784static void
785il3945_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb)
786{
787 struct il_rx_pkt *pkt = rxb_addr(rxb);
788 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
789 unsigned long status = il->status;
790
791 IL_WARN("Card state received: HW:%s SW:%s\n",
792 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
793 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
794
795 _il_wr(il, CSR_UCODE_DRV_GP1_SET, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
796
797 if (flags & HW_CARD_DISABLED)
798 set_bit(S_RFKILL, &il->status);
799 else
800 clear_bit(S_RFKILL, &il->status);
801
802 il_scan_cancel(il);
803
804 if ((test_bit(S_RFKILL, &status) !=
805 test_bit(S_RFKILL, &il->status)))
806 wiphy_rfkill_set_hw_state(il->hw->wiphy,
807 test_bit(S_RFKILL, &il->status));
808 else
809 wake_up(&il->wait_command_queue);
810}
811
812
813
814
815
816
817
818
819
820
821static void
822il3945_setup_handlers(struct il_priv *il)
823{
824 il->handlers[N_ALIVE] = il3945_hdl_alive;
825 il->handlers[C_ADD_STA] = il3945_hdl_add_sta;
826 il->handlers[N_ERROR] = il_hdl_error;
827 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa;
828 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement;
829 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep;
830 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats;
831 il->handlers[N_BEACON] = il3945_hdl_beacon;
832
833
834
835
836
837
838 il->handlers[C_STATS] = il3945_hdl_c_stats;
839 il->handlers[N_STATS] = il3945_hdl_stats;
840
841 il_setup_rx_scan_handlers(il);
842 il->handlers[N_CARD_STATE] = il3945_hdl_card_state;
843
844
845 il3945_hw_handler_setup(il);
846}
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915static inline __le32
916il3945_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr)
917{
918 return cpu_to_le32((u32) dma_addr);
919}
920
921
922
923
924
925
926
927
928
929
930
931
932static void
933il3945_rx_queue_restock(struct il_priv *il)
934{
935 struct il_rx_queue *rxq = &il->rxq;
936 struct list_head *element;
937 struct il_rx_buf *rxb;
938 unsigned long flags;
939
940 spin_lock_irqsave(&rxq->lock, flags);
941 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
942
943 element = rxq->rx_free.next;
944 rxb = list_entry(element, struct il_rx_buf, list);
945 list_del(element);
946
947
948 rxq->bd[rxq->write] =
949 il3945_dma_addr2rbd_ptr(il, rxb->page_dma);
950 rxq->queue[rxq->write] = rxb;
951 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
952 rxq->free_count--;
953 }
954 spin_unlock_irqrestore(&rxq->lock, flags);
955
956
957 if (rxq->free_count <= RX_LOW_WATERMARK)
958 queue_work(il->workqueue, &il->rx_replenish);
959
960
961
962 if (rxq->write_actual != (rxq->write & ~0x7) ||
963 abs(rxq->write - rxq->read) > 7) {
964 spin_lock_irqsave(&rxq->lock, flags);
965 rxq->need_update = 1;
966 spin_unlock_irqrestore(&rxq->lock, flags);
967 il_rx_queue_update_write_ptr(il, rxq);
968 }
969}
970
971
972
973
974
975
976
977
978
979static void
980il3945_rx_allocate(struct il_priv *il, gfp_t priority)
981{
982 struct il_rx_queue *rxq = &il->rxq;
983 struct list_head *element;
984 struct il_rx_buf *rxb;
985 struct page *page;
986 dma_addr_t page_dma;
987 unsigned long flags;
988 gfp_t gfp_mask = priority;
989
990 while (1) {
991 spin_lock_irqsave(&rxq->lock, flags);
992 if (list_empty(&rxq->rx_used)) {
993 spin_unlock_irqrestore(&rxq->lock, flags);
994 return;
995 }
996 spin_unlock_irqrestore(&rxq->lock, flags);
997
998 if (rxq->free_count > RX_LOW_WATERMARK)
999 gfp_mask |= __GFP_NOWARN;
1000
1001 if (il->hw_params.rx_page_order > 0)
1002 gfp_mask |= __GFP_COMP;
1003
1004
1005 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
1006 if (!page) {
1007 if (net_ratelimit())
1008 D_INFO("Failed to allocate SKB buffer.\n");
1009 if (rxq->free_count <= RX_LOW_WATERMARK &&
1010 net_ratelimit())
1011 IL_ERR("Failed to allocate SKB buffer with %0x."
1012 "Only %u free buffers remaining.\n",
1013 priority, rxq->free_count);
1014
1015
1016
1017 break;
1018 }
1019
1020
1021 page_dma =
1022 pci_map_page(il->pci_dev, page, 0,
1023 PAGE_SIZE << il->hw_params.rx_page_order,
1024 PCI_DMA_FROMDEVICE);
1025
1026 if (unlikely(pci_dma_mapping_error(il->pci_dev, page_dma))) {
1027 __free_pages(page, il->hw_params.rx_page_order);
1028 break;
1029 }
1030
1031 spin_lock_irqsave(&rxq->lock, flags);
1032
1033 if (list_empty(&rxq->rx_used)) {
1034 spin_unlock_irqrestore(&rxq->lock, flags);
1035 pci_unmap_page(il->pci_dev, page_dma,
1036 PAGE_SIZE << il->hw_params.rx_page_order,
1037 PCI_DMA_FROMDEVICE);
1038 __free_pages(page, il->hw_params.rx_page_order);
1039 return;
1040 }
1041
1042 element = rxq->rx_used.next;
1043 rxb = list_entry(element, struct il_rx_buf, list);
1044 list_del(element);
1045
1046 rxb->page = page;
1047 rxb->page_dma = page_dma;
1048 list_add_tail(&rxb->list, &rxq->rx_free);
1049 rxq->free_count++;
1050 il->alloc_rxb_page++;
1051
1052 spin_unlock_irqrestore(&rxq->lock, flags);
1053 }
1054}
1055
1056void
1057il3945_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
1058{
1059 unsigned long flags;
1060 int i;
1061 spin_lock_irqsave(&rxq->lock, flags);
1062 INIT_LIST_HEAD(&rxq->rx_free);
1063 INIT_LIST_HEAD(&rxq->rx_used);
1064
1065 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
1066
1067
1068 if (rxq->pool[i].page != NULL) {
1069 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1070 PAGE_SIZE << il->hw_params.rx_page_order,
1071 PCI_DMA_FROMDEVICE);
1072 __il_free_pages(il, rxq->pool[i].page);
1073 rxq->pool[i].page = NULL;
1074 }
1075 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
1076 }
1077
1078
1079
1080 rxq->read = rxq->write = 0;
1081 rxq->write_actual = 0;
1082 rxq->free_count = 0;
1083 spin_unlock_irqrestore(&rxq->lock, flags);
1084}
1085
1086void
1087il3945_rx_replenish(void *data)
1088{
1089 struct il_priv *il = data;
1090 unsigned long flags;
1091
1092 il3945_rx_allocate(il, GFP_KERNEL);
1093
1094 spin_lock_irqsave(&il->lock, flags);
1095 il3945_rx_queue_restock(il);
1096 spin_unlock_irqrestore(&il->lock, flags);
1097}
1098
1099static void
1100il3945_rx_replenish_now(struct il_priv *il)
1101{
1102 il3945_rx_allocate(il, GFP_ATOMIC);
1103
1104 il3945_rx_queue_restock(il);
1105}
1106
1107
1108
1109
1110
1111
1112static void
1113il3945_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
1114{
1115 int i;
1116 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
1117 if (rxq->pool[i].page != NULL) {
1118 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
1119 PAGE_SIZE << il->hw_params.rx_page_order,
1120 PCI_DMA_FROMDEVICE);
1121 __il_free_pages(il, rxq->pool[i].page);
1122 rxq->pool[i].page = NULL;
1123 }
1124 }
1125
1126 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
1127 rxq->bd_dma);
1128 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
1129 rxq->rb_stts, rxq->rb_stts_dma);
1130 rxq->bd = NULL;
1131 rxq->rb_stts = NULL;
1132}
1133
1134
1135static u8 ratio2dB[100] = {
1136
1137 0, 0, 6, 10, 12, 14, 16, 17, 18, 19,
1138 20, 21, 22, 22, 23, 23, 24, 25, 26, 26,
1139 26, 26, 26, 27, 27, 28, 28, 28, 29, 29,
1140 29, 30, 30, 30, 31, 31, 31, 31, 32, 32,
1141 32, 32, 32, 33, 33, 33, 33, 33, 34, 34,
1142 34, 34, 34, 34, 35, 35, 35, 35, 35, 35,
1143 36, 36, 36, 36, 36, 36, 36, 37, 37, 37,
1144 37, 37, 37, 37, 37, 38, 38, 38, 38, 38,
1145 38, 38, 38, 38, 38, 39, 39, 39, 39, 39,
1146 39, 39, 39, 39, 39, 40, 40, 40, 40, 40
1147};
1148
1149
1150
1151
1152int
1153il3945_calc_db_from_ratio(int sig_ratio)
1154{
1155
1156 if (sig_ratio >= 1000)
1157 return 60;
1158
1159
1160
1161 if (sig_ratio >= 100)
1162 return 20 + (int)ratio2dB[sig_ratio / 10];
1163
1164
1165 if (sig_ratio < 1)
1166 return 0;
1167
1168
1169 return (int)ratio2dB[sig_ratio];
1170}
1171
1172
1173
1174
1175
1176
1177
1178
1179static void
1180il3945_rx_handle(struct il_priv *il)
1181{
1182 struct il_rx_buf *rxb;
1183 struct il_rx_pkt *pkt;
1184 struct il_rx_queue *rxq = &il->rxq;
1185 u32 r, i;
1186 int reclaim;
1187 unsigned long flags;
1188 u8 fill_rx = 0;
1189 u32 count = 8;
1190 int total_empty = 0;
1191
1192
1193
1194 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
1195 i = rxq->read;
1196
1197
1198 total_empty = r - rxq->write_actual;
1199 if (total_empty < 0)
1200 total_empty += RX_QUEUE_SIZE;
1201
1202 if (total_empty > (RX_QUEUE_SIZE / 2))
1203 fill_rx = 1;
1204
1205 if (i == r)
1206 D_RX("r = %d, i = %d\n", r, i);
1207
1208 while (i != r) {
1209 int len;
1210
1211 rxb = rxq->queue[i];
1212
1213
1214
1215
1216 BUG_ON(rxb == NULL);
1217
1218 rxq->queue[i] = NULL;
1219
1220 pci_unmap_page(il->pci_dev, rxb->page_dma,
1221 PAGE_SIZE << il->hw_params.rx_page_order,
1222 PCI_DMA_FROMDEVICE);
1223 pkt = rxb_addr(rxb);
1224
1225 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
1226 len += sizeof(u32);
1227
1228 reclaim = il_need_reclaim(il, pkt);
1229
1230
1231
1232
1233 if (il->handlers[pkt->hdr.cmd]) {
1234 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i,
1235 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1236 il->isr_stats.handlers[pkt->hdr.cmd]++;
1237 il->handlers[pkt->hdr.cmd] (il, rxb);
1238 } else {
1239
1240 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r,
1241 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1242 }
1243
1244
1245
1246
1247
1248
1249
1250
1251 if (reclaim) {
1252
1253
1254
1255 if (rxb->page)
1256 il_tx_cmd_complete(il, rxb);
1257 else
1258 IL_WARN("Claim null rxb?\n");
1259 }
1260
1261
1262
1263
1264 spin_lock_irqsave(&rxq->lock, flags);
1265 if (rxb->page != NULL) {
1266 rxb->page_dma =
1267 pci_map_page(il->pci_dev, rxb->page, 0,
1268 PAGE_SIZE << il->hw_params.
1269 rx_page_order, PCI_DMA_FROMDEVICE);
1270 if (unlikely(pci_dma_mapping_error(il->pci_dev,
1271 rxb->page_dma))) {
1272 __il_free_pages(il, rxb->page);
1273 rxb->page = NULL;
1274 list_add_tail(&rxb->list, &rxq->rx_used);
1275 } else {
1276 list_add_tail(&rxb->list, &rxq->rx_free);
1277 rxq->free_count++;
1278 }
1279 } else
1280 list_add_tail(&rxb->list, &rxq->rx_used);
1281
1282 spin_unlock_irqrestore(&rxq->lock, flags);
1283
1284 i = (i + 1) & RX_QUEUE_MASK;
1285
1286
1287 if (fill_rx) {
1288 count++;
1289 if (count >= 8) {
1290 rxq->read = i;
1291 il3945_rx_replenish_now(il);
1292 count = 0;
1293 }
1294 }
1295 }
1296
1297
1298 rxq->read = i;
1299 if (fill_rx)
1300 il3945_rx_replenish_now(il);
1301 else
1302 il3945_rx_queue_restock(il);
1303}
1304
1305
1306static inline void
1307il3945_synchronize_irq(struct il_priv *il)
1308{
1309
1310 synchronize_irq(il->pci_dev->irq);
1311 tasklet_kill(&il->irq_tasklet);
1312}
1313
1314static const char *
1315il3945_desc_lookup(int i)
1316{
1317 switch (i) {
1318 case 1:
1319 return "FAIL";
1320 case 2:
1321 return "BAD_PARAM";
1322 case 3:
1323 return "BAD_CHECKSUM";
1324 case 4:
1325 return "NMI_INTERRUPT";
1326 case 5:
1327 return "SYSASSERT";
1328 case 6:
1329 return "FATAL_ERROR";
1330 }
1331
1332 return "UNKNOWN";
1333}
1334
1335#define ERROR_START_OFFSET (1 * sizeof(u32))
1336#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1337
1338void
1339il3945_dump_nic_error_log(struct il_priv *il)
1340{
1341 u32 i;
1342 u32 desc, time, count, base, data1;
1343 u32 blink1, blink2, ilink1, ilink2;
1344
1345 base = le32_to_cpu(il->card_alive.error_event_table_ptr);
1346
1347 if (!il3945_hw_valid_rtc_data_addr(base)) {
1348 IL_ERR("Not valid error log pointer 0x%08X\n", base);
1349 return;
1350 }
1351
1352 count = il_read_targ_mem(il, base);
1353
1354 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1355 IL_ERR("Start IWL Error Log Dump:\n");
1356 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count);
1357 }
1358
1359 IL_ERR("Desc Time asrtPC blink2 "
1360 "ilink1 nmiPC Line\n");
1361 for (i = ERROR_START_OFFSET;
1362 i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
1363 i += ERROR_ELEM_SIZE) {
1364 desc = il_read_targ_mem(il, base + i);
1365 time = il_read_targ_mem(il, base + i + 1 * sizeof(u32));
1366 blink1 = il_read_targ_mem(il, base + i + 2 * sizeof(u32));
1367 blink2 = il_read_targ_mem(il, base + i + 3 * sizeof(u32));
1368 ilink1 = il_read_targ_mem(il, base + i + 4 * sizeof(u32));
1369 ilink2 = il_read_targ_mem(il, base + i + 5 * sizeof(u32));
1370 data1 = il_read_targ_mem(il, base + i + 6 * sizeof(u32));
1371
1372 IL_ERR("%-13s (0x%X) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
1373 il3945_desc_lookup(desc), desc, time, blink1, blink2,
1374 ilink1, ilink2, data1);
1375 }
1376}
1377
1378static void
1379il3945_irq_tasklet(struct il_priv *il)
1380{
1381 u32 inta, handled = 0;
1382 u32 inta_fh;
1383 unsigned long flags;
1384#ifdef CONFIG_IWLEGACY_DEBUG
1385 u32 inta_mask;
1386#endif
1387
1388 spin_lock_irqsave(&il->lock, flags);
1389
1390
1391
1392
1393 inta = _il_rd(il, CSR_INT);
1394 _il_wr(il, CSR_INT, inta);
1395
1396
1397
1398
1399 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1400 _il_wr(il, CSR_FH_INT_STATUS, inta_fh);
1401
1402#ifdef CONFIG_IWLEGACY_DEBUG
1403 if (il_get_debug_level(il) & IL_DL_ISR) {
1404
1405 inta_mask = _il_rd(il, CSR_INT_MASK);
1406 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta,
1407 inta_mask, inta_fh);
1408 }
1409#endif
1410
1411 spin_unlock_irqrestore(&il->lock, flags);
1412
1413
1414
1415
1416
1417 if (inta_fh & CSR39_FH_INT_RX_MASK)
1418 inta |= CSR_INT_BIT_FH_RX;
1419 if (inta_fh & CSR39_FH_INT_TX_MASK)
1420 inta |= CSR_INT_BIT_FH_TX;
1421
1422
1423 if (inta & CSR_INT_BIT_HW_ERR) {
1424 IL_ERR("Hardware error detected. Restarting.\n");
1425
1426
1427 il_disable_interrupts(il);
1428
1429 il->isr_stats.hw++;
1430 il_irq_handle_error(il);
1431
1432 handled |= CSR_INT_BIT_HW_ERR;
1433
1434 return;
1435 }
1436#ifdef CONFIG_IWLEGACY_DEBUG
1437 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1438
1439 if (inta & CSR_INT_BIT_SCD) {
1440 D_ISR("Scheduler finished to transmit "
1441 "the frame/frames.\n");
1442 il->isr_stats.sch++;
1443 }
1444
1445
1446 if (inta & CSR_INT_BIT_ALIVE) {
1447 D_ISR("Alive interrupt\n");
1448 il->isr_stats.alive++;
1449 }
1450 }
1451#endif
1452
1453 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1454
1455
1456 if (inta & CSR_INT_BIT_SW_ERR) {
1457 IL_ERR("Microcode SW error detected. " "Restarting 0x%X.\n",
1458 inta);
1459 il->isr_stats.sw++;
1460 il_irq_handle_error(il);
1461 handled |= CSR_INT_BIT_SW_ERR;
1462 }
1463
1464
1465 if (inta & CSR_INT_BIT_WAKEUP) {
1466 D_ISR("Wakeup interrupt\n");
1467 il_rx_queue_update_write_ptr(il, &il->rxq);
1468
1469 spin_lock_irqsave(&il->lock, flags);
1470 il_txq_update_write_ptr(il, &il->txq[0]);
1471 il_txq_update_write_ptr(il, &il->txq[1]);
1472 il_txq_update_write_ptr(il, &il->txq[2]);
1473 il_txq_update_write_ptr(il, &il->txq[3]);
1474 il_txq_update_write_ptr(il, &il->txq[4]);
1475 spin_unlock_irqrestore(&il->lock, flags);
1476
1477 il->isr_stats.wakeup++;
1478 handled |= CSR_INT_BIT_WAKEUP;
1479 }
1480
1481
1482
1483
1484 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1485 il3945_rx_handle(il);
1486 il->isr_stats.rx++;
1487 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1488 }
1489
1490 if (inta & CSR_INT_BIT_FH_TX) {
1491 D_ISR("Tx interrupt\n");
1492 il->isr_stats.tx++;
1493
1494 _il_wr(il, CSR_FH_INT_STATUS, (1 << 6));
1495 il_wr(il, FH39_TCSR_CREDIT(FH39_SRVC_CHNL), 0x0);
1496 handled |= CSR_INT_BIT_FH_TX;
1497 }
1498
1499 if (inta & ~handled) {
1500 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
1501 il->isr_stats.unhandled++;
1502 }
1503
1504 if (inta & ~il->inta_mask) {
1505 IL_WARN("Disabled INTA bits 0x%08x were pending\n",
1506 inta & ~il->inta_mask);
1507 IL_WARN(" with inta_fh = 0x%08x\n", inta_fh);
1508 }
1509
1510
1511
1512 if (test_bit(S_INT_ENABLED, &il->status))
1513 il_enable_interrupts(il);
1514
1515#ifdef CONFIG_IWLEGACY_DEBUG
1516 if (il_get_debug_level(il) & (IL_DL_ISR)) {
1517 inta = _il_rd(il, CSR_INT);
1518 inta_mask = _il_rd(il, CSR_INT_MASK);
1519 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
1520 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1521 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1522 }
1523#endif
1524}
1525
1526static int
1527il3945_get_channels_for_scan(struct il_priv *il, enum nl80211_band band,
1528 u8 is_active, u8 n_probes,
1529 struct il3945_scan_channel *scan_ch,
1530 struct ieee80211_vif *vif)
1531{
1532 struct ieee80211_channel *chan;
1533 const struct ieee80211_supported_band *sband;
1534 const struct il_channel_info *ch_info;
1535 u16 passive_dwell = 0;
1536 u16 active_dwell = 0;
1537 int added, i;
1538
1539 sband = il_get_hw_mode(il, band);
1540 if (!sband)
1541 return 0;
1542
1543 active_dwell = il_get_active_dwell_time(il, band, n_probes);
1544 passive_dwell = il_get_passive_dwell_time(il, band, vif);
1545
1546 if (passive_dwell <= active_dwell)
1547 passive_dwell = active_dwell + 1;
1548
1549 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
1550 chan = il->scan_request->channels[i];
1551
1552 if (chan->band != band)
1553 continue;
1554
1555 scan_ch->channel = chan->hw_value;
1556
1557 ch_info = il_get_channel_info(il, band, scan_ch->channel);
1558 if (!il_is_channel_valid(ch_info)) {
1559 D_SCAN("Channel %d is INVALID for this band.\n",
1560 scan_ch->channel);
1561 continue;
1562 }
1563
1564 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1565 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1566
1567
1568
1569 if (!is_active || il_is_channel_passive(ch_info) ||
1570 (chan->flags & IEEE80211_CHAN_NO_IR)) {
1571 scan_ch->type = 0;
1572 if (IL_UCODE_API(il->ucode_ver) == 1)
1573 scan_ch->active_dwell =
1574 cpu_to_le16(passive_dwell - 1);
1575 } else {
1576 scan_ch->type = 1;
1577 }
1578
1579
1580
1581
1582
1583 if (IL_UCODE_API(il->ucode_ver) >= 2) {
1584 if (n_probes)
1585 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1586 } else {
1587
1588
1589 if ((scan_ch->type & 1) && n_probes)
1590 scan_ch->type |= IL39_SCAN_PROBE_MASK(n_probes);
1591 }
1592
1593
1594 scan_ch->tpc.dsp_atten = 110;
1595
1596
1597
1598 if (band == NL80211_BAND_5GHZ)
1599 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1600 else {
1601 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1602
1603
1604
1605
1606 }
1607
1608 D_SCAN("Scanning %d [%s %d]\n", scan_ch->channel,
1609 (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
1610 (scan_ch->type & 1) ? active_dwell : passive_dwell);
1611
1612 scan_ch++;
1613 added++;
1614 }
1615
1616 D_SCAN("total channels to scan %d\n", added);
1617 return added;
1618}
1619
1620static void
1621il3945_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates)
1622{
1623 int i;
1624
1625 for (i = 0; i < RATE_COUNT_LEGACY; i++) {
1626 rates[i].bitrate = il3945_rates[i].ieee * 5;
1627 rates[i].hw_value = i;
1628 rates[i].hw_value_short = i;
1629 rates[i].flags = 0;
1630 if (i > IL39_LAST_OFDM_RATE || i < IL_FIRST_OFDM_RATE) {
1631
1632
1633
1634 rates[i].flags |=
1635 (il3945_rates[i].plcp ==
1636 10) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE;
1637 }
1638 }
1639}
1640
1641
1642
1643
1644
1645
1646
1647static void
1648il3945_dealloc_ucode_pci(struct il_priv *il)
1649{
1650 il_free_fw_desc(il->pci_dev, &il->ucode_code);
1651 il_free_fw_desc(il->pci_dev, &il->ucode_data);
1652 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup);
1653 il_free_fw_desc(il->pci_dev, &il->ucode_init);
1654 il_free_fw_desc(il->pci_dev, &il->ucode_init_data);
1655 il_free_fw_desc(il->pci_dev, &il->ucode_boot);
1656}
1657
1658
1659
1660
1661
1662static int
1663il3945_verify_inst_full(struct il_priv *il, __le32 * image, u32 len)
1664{
1665 u32 val;
1666 u32 save_len = len;
1667 int rc = 0;
1668 u32 errcnt;
1669
1670 D_INFO("ucode inst image size is %u\n", len);
1671
1672 il_wr(il, HBUS_TARG_MEM_RADDR, IL39_RTC_INST_LOWER_BOUND);
1673
1674 errcnt = 0;
1675 for (; len > 0; len -= sizeof(u32), image++) {
1676
1677
1678
1679 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1680 if (val != le32_to_cpu(*image)) {
1681 IL_ERR("uCode INST section is invalid at "
1682 "offset 0x%x, is 0x%x, s/b 0x%x\n",
1683 save_len - len, val, le32_to_cpu(*image));
1684 rc = -EIO;
1685 errcnt++;
1686 if (errcnt >= 20)
1687 break;
1688 }
1689 }
1690
1691 if (!errcnt)
1692 D_INFO("ucode image in INSTRUCTION memory is good\n");
1693
1694 return rc;
1695}
1696
1697
1698
1699
1700
1701
1702static int
1703il3945_verify_inst_sparse(struct il_priv *il, __le32 * image, u32 len)
1704{
1705 u32 val;
1706 int rc = 0;
1707 u32 errcnt = 0;
1708 u32 i;
1709
1710 D_INFO("ucode inst image size is %u\n", len);
1711
1712 for (i = 0; i < len; i += 100, image += 100 / sizeof(u32)) {
1713
1714
1715
1716 il_wr(il, HBUS_TARG_MEM_RADDR, i + IL39_RTC_INST_LOWER_BOUND);
1717 val = _il_rd(il, HBUS_TARG_MEM_RDAT);
1718 if (val != le32_to_cpu(*image)) {
1719#if 0
1720 IL_ERR("uCode INST section is invalid at "
1721 "offset 0x%x, is 0x%x, s/b 0x%x\n", i, val,
1722 *image);
1723#endif
1724 rc = -EIO;
1725 errcnt++;
1726 if (errcnt >= 3)
1727 break;
1728 }
1729 }
1730
1731 return rc;
1732}
1733
1734
1735
1736
1737
1738static int
1739il3945_verify_ucode(struct il_priv *il)
1740{
1741 __le32 *image;
1742 u32 len;
1743 int rc = 0;
1744
1745
1746 image = (__le32 *) il->ucode_boot.v_addr;
1747 len = il->ucode_boot.len;
1748 rc = il3945_verify_inst_sparse(il, image, len);
1749 if (rc == 0) {
1750 D_INFO("Bootstrap uCode is good in inst SRAM\n");
1751 return 0;
1752 }
1753
1754
1755 image = (__le32 *) il->ucode_init.v_addr;
1756 len = il->ucode_init.len;
1757 rc = il3945_verify_inst_sparse(il, image, len);
1758 if (rc == 0) {
1759 D_INFO("Initialize uCode is good in inst SRAM\n");
1760 return 0;
1761 }
1762
1763
1764 image = (__le32 *) il->ucode_code.v_addr;
1765 len = il->ucode_code.len;
1766 rc = il3945_verify_inst_sparse(il, image, len);
1767 if (rc == 0) {
1768 D_INFO("Runtime uCode is good in inst SRAM\n");
1769 return 0;
1770 }
1771
1772 IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1773
1774
1775
1776
1777 image = (__le32 *) il->ucode_boot.v_addr;
1778 len = il->ucode_boot.len;
1779 rc = il3945_verify_inst_full(il, image, len);
1780
1781 return rc;
1782}
1783
1784static void
1785il3945_nic_start(struct il_priv *il)
1786{
1787
1788 _il_wr(il, CSR_RESET, 0);
1789}
1790
1791#define IL3945_UCODE_GET(item) \
1792static u32 il3945_ucode_get_##item(const struct il_ucode_header *ucode)\
1793{ \
1794 return le32_to_cpu(ucode->v1.item); \
1795}
1796
1797static u32
1798il3945_ucode_get_header_size(u32 api_ver)
1799{
1800 return 24;
1801}
1802
1803static u8 *
1804il3945_ucode_get_data(const struct il_ucode_header *ucode)
1805{
1806 return (u8 *) ucode->v1.data;
1807}
1808
1809IL3945_UCODE_GET(inst_size);
1810IL3945_UCODE_GET(data_size);
1811IL3945_UCODE_GET(init_size);
1812IL3945_UCODE_GET(init_data_size);
1813IL3945_UCODE_GET(boot_size);
1814
1815
1816
1817
1818
1819
1820static int
1821il3945_read_ucode(struct il_priv *il)
1822{
1823 const struct il_ucode_header *ucode;
1824 int ret = -EINVAL, idx;
1825 const struct firmware *ucode_raw;
1826
1827 const char *name_pre = il->cfg->fw_name_pre;
1828 const unsigned int api_max = il->cfg->ucode_api_max;
1829 const unsigned int api_min = il->cfg->ucode_api_min;
1830 char buf[25];
1831 u8 *src;
1832 size_t len;
1833 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
1834
1835
1836
1837 for (idx = api_max; idx >= api_min; idx--) {
1838 sprintf(buf, "%s%u%s", name_pre, idx, ".ucode");
1839 ret = request_firmware(&ucode_raw, buf, &il->pci_dev->dev);
1840 if (ret < 0) {
1841 IL_ERR("%s firmware file req failed: %d\n", buf, ret);
1842 if (ret == -ENOENT)
1843 continue;
1844 else
1845 goto error;
1846 } else {
1847 if (idx < api_max)
1848 IL_ERR("Loaded firmware %s, "
1849 "which is deprecated. "
1850 " Please use API v%u instead.\n", buf,
1851 api_max);
1852 D_INFO("Got firmware '%s' file "
1853 "(%zd bytes) from disk\n", buf, ucode_raw->size);
1854 break;
1855 }
1856 }
1857
1858 if (ret < 0)
1859 goto error;
1860
1861
1862 if (ucode_raw->size < il3945_ucode_get_header_size(1)) {
1863 IL_ERR("File size way too small!\n");
1864 ret = -EINVAL;
1865 goto err_release;
1866 }
1867
1868
1869 ucode = (struct il_ucode_header *)ucode_raw->data;
1870
1871 il->ucode_ver = le32_to_cpu(ucode->ver);
1872 api_ver = IL_UCODE_API(il->ucode_ver);
1873 inst_size = il3945_ucode_get_inst_size(ucode);
1874 data_size = il3945_ucode_get_data_size(ucode);
1875 init_size = il3945_ucode_get_init_size(ucode);
1876 init_data_size = il3945_ucode_get_init_data_size(ucode);
1877 boot_size = il3945_ucode_get_boot_size(ucode);
1878 src = il3945_ucode_get_data(ucode);
1879
1880
1881
1882
1883
1884 if (api_ver < api_min || api_ver > api_max) {
1885 IL_ERR("Driver unable to support your firmware API. "
1886 "Driver supports v%u, firmware is v%u.\n", api_max,
1887 api_ver);
1888 il->ucode_ver = 0;
1889 ret = -EINVAL;
1890 goto err_release;
1891 }
1892 if (api_ver != api_max)
1893 IL_ERR("Firmware has old API version. Expected %u, "
1894 "got %u. New firmware can be obtained "
1895 "from http://www.intellinuxwireless.org.\n", api_max,
1896 api_ver);
1897
1898 IL_INFO("loaded firmware version %u.%u.%u.%u\n",
1899 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver),
1900 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver));
1901
1902 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version),
1903 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver),
1904 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver),
1905 IL_UCODE_SERIAL(il->ucode_ver));
1906
1907 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver);
1908 D_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
1909 D_INFO("f/w package hdr runtime data size = %u\n", data_size);
1910 D_INFO("f/w package hdr init inst size = %u\n", init_size);
1911 D_INFO("f/w package hdr init data size = %u\n", init_data_size);
1912 D_INFO("f/w package hdr boot inst size = %u\n", boot_size);
1913
1914
1915 if (ucode_raw->size !=
1916 il3945_ucode_get_header_size(api_ver) + inst_size + data_size +
1917 init_size + init_data_size + boot_size) {
1918
1919 D_INFO("uCode file size %zd does not match expected size\n",
1920 ucode_raw->size);
1921 ret = -EINVAL;
1922 goto err_release;
1923 }
1924
1925
1926 if (inst_size > IL39_MAX_INST_SIZE) {
1927 D_INFO("uCode instr len %d too large to fit in\n", inst_size);
1928 ret = -EINVAL;
1929 goto err_release;
1930 }
1931
1932 if (data_size > IL39_MAX_DATA_SIZE) {
1933 D_INFO("uCode data len %d too large to fit in\n", data_size);
1934 ret = -EINVAL;
1935 goto err_release;
1936 }
1937 if (init_size > IL39_MAX_INST_SIZE) {
1938 D_INFO("uCode init instr len %d too large to fit in\n",
1939 init_size);
1940 ret = -EINVAL;
1941 goto err_release;
1942 }
1943 if (init_data_size > IL39_MAX_DATA_SIZE) {
1944 D_INFO("uCode init data len %d too large to fit in\n",
1945 init_data_size);
1946 ret = -EINVAL;
1947 goto err_release;
1948 }
1949 if (boot_size > IL39_MAX_BSM_SIZE) {
1950 D_INFO("uCode boot instr len %d too large to fit in\n",
1951 boot_size);
1952 ret = -EINVAL;
1953 goto err_release;
1954 }
1955
1956
1957
1958
1959
1960
1961 il->ucode_code.len = inst_size;
1962 il_alloc_fw_desc(il->pci_dev, &il->ucode_code);
1963
1964 il->ucode_data.len = data_size;
1965 il_alloc_fw_desc(il->pci_dev, &il->ucode_data);
1966
1967 il->ucode_data_backup.len = data_size;
1968 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup);
1969
1970 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr ||
1971 !il->ucode_data_backup.v_addr)
1972 goto err_pci_alloc;
1973
1974
1975 if (init_size && init_data_size) {
1976 il->ucode_init.len = init_size;
1977 il_alloc_fw_desc(il->pci_dev, &il->ucode_init);
1978
1979 il->ucode_init_data.len = init_data_size;
1980 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data);
1981
1982 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr)
1983 goto err_pci_alloc;
1984 }
1985
1986
1987 if (boot_size) {
1988 il->ucode_boot.len = boot_size;
1989 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot);
1990
1991 if (!il->ucode_boot.v_addr)
1992 goto err_pci_alloc;
1993 }
1994
1995
1996
1997
1998 len = inst_size;
1999 D_INFO("Copying (but not loading) uCode instr len %zd\n", len);
2000 memcpy(il->ucode_code.v_addr, src, len);
2001 src += len;
2002
2003 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2004 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr);
2005
2006
2007
2008 len = data_size;
2009 D_INFO("Copying (but not loading) uCode data len %zd\n", len);
2010 memcpy(il->ucode_data.v_addr, src, len);
2011 memcpy(il->ucode_data_backup.v_addr, src, len);
2012 src += len;
2013
2014
2015 if (init_size) {
2016 len = init_size;
2017 D_INFO("Copying (but not loading) init instr len %zd\n", len);
2018 memcpy(il->ucode_init.v_addr, src, len);
2019 src += len;
2020 }
2021
2022
2023 if (init_data_size) {
2024 len = init_data_size;
2025 D_INFO("Copying (but not loading) init data len %zd\n", len);
2026 memcpy(il->ucode_init_data.v_addr, src, len);
2027 src += len;
2028 }
2029
2030
2031 len = boot_size;
2032 D_INFO("Copying (but not loading) boot instr len %zd\n", len);
2033 memcpy(il->ucode_boot.v_addr, src, len);
2034
2035
2036 release_firmware(ucode_raw);
2037 return 0;
2038
2039err_pci_alloc:
2040 IL_ERR("failed to allocate pci memory\n");
2041 ret = -ENOMEM;
2042 il3945_dealloc_ucode_pci(il);
2043
2044err_release:
2045 release_firmware(ucode_raw);
2046
2047error:
2048 return ret;
2049}
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060static int
2061il3945_set_ucode_ptrs(struct il_priv *il)
2062{
2063 dma_addr_t pinst;
2064 dma_addr_t pdata;
2065
2066
2067 pinst = il->ucode_code.p_addr;
2068 pdata = il->ucode_data_backup.p_addr;
2069
2070
2071 il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst);
2072 il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata);
2073 il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, il->ucode_data.len);
2074
2075
2076
2077 il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG,
2078 il->ucode_code.len | BSM_DRAM_INST_LOAD);
2079
2080 D_INFO("Runtime uCode pointers are set.\n");
2081
2082 return 0;
2083}
2084
2085
2086
2087
2088
2089
2090
2091
2092static void
2093il3945_init_alive_start(struct il_priv *il)
2094{
2095
2096 if (il->card_alive_init.is_valid != UCODE_VALID_OK) {
2097
2098
2099 D_INFO("Initialize Alive failed.\n");
2100 goto restart;
2101 }
2102
2103
2104
2105
2106 if (il3945_verify_ucode(il)) {
2107
2108
2109 D_INFO("Bad \"initialize\" uCode load.\n");
2110 goto restart;
2111 }
2112
2113
2114
2115
2116 D_INFO("Initialization Alive received.\n");
2117 if (il3945_set_ucode_ptrs(il)) {
2118
2119
2120 D_INFO("Couldn't set up uCode pointers.\n");
2121 goto restart;
2122 }
2123 return;
2124
2125restart:
2126 queue_work(il->workqueue, &il->restart);
2127}
2128
2129
2130
2131
2132
2133
2134static void
2135il3945_alive_start(struct il_priv *il)
2136{
2137 int thermal_spin = 0;
2138 u32 rfkill;
2139
2140 D_INFO("Runtime Alive received.\n");
2141
2142 if (il->card_alive.is_valid != UCODE_VALID_OK) {
2143
2144
2145 D_INFO("Alive failed.\n");
2146 goto restart;
2147 }
2148
2149
2150
2151
2152 if (il3945_verify_ucode(il)) {
2153
2154
2155 D_INFO("Bad runtime uCode load.\n");
2156 goto restart;
2157 }
2158
2159 rfkill = il_rd_prph(il, APMG_RFKILL_REG);
2160 D_INFO("RFKILL status: 0x%x\n", rfkill);
2161
2162 if (rfkill & 0x1) {
2163 clear_bit(S_RFKILL, &il->status);
2164
2165
2166 while (il3945_hw_get_temperature(il) == 0) {
2167 thermal_spin++;
2168 udelay(10);
2169 }
2170
2171 if (thermal_spin)
2172 D_INFO("Thermal calibration took %dus\n",
2173 thermal_spin * 10);
2174 } else
2175 set_bit(S_RFKILL, &il->status);
2176
2177
2178 set_bit(S_ALIVE, &il->status);
2179
2180
2181 il_setup_watchdog(il);
2182
2183 if (il_is_rfkill(il))
2184 return;
2185
2186 ieee80211_wake_queues(il->hw);
2187
2188 il->active_rate = RATES_MASK_3945;
2189
2190 il_power_update_mode(il, true);
2191
2192 if (il_is_associated(il)) {
2193 struct il3945_rxon_cmd *active_rxon =
2194 (struct il3945_rxon_cmd *)(&il->active);
2195
2196 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2197 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2198 } else {
2199
2200 il_connection_init_rx_config(il);
2201 }
2202
2203
2204 il_send_bt_config(il);
2205
2206 set_bit(S_READY, &il->status);
2207
2208
2209 il3945_commit_rxon(il);
2210
2211 il3945_reg_txpower_periodic(il);
2212
2213 D_INFO("ALIVE processing complete.\n");
2214 wake_up(&il->wait_command_queue);
2215
2216 return;
2217
2218restart:
2219 queue_work(il->workqueue, &il->restart);
2220}
2221
2222static void il3945_cancel_deferred_work(struct il_priv *il);
2223
2224static void
2225__il3945_down(struct il_priv *il)
2226{
2227 unsigned long flags;
2228 int exit_pending;
2229
2230 D_INFO(DRV_NAME " is going down\n");
2231
2232 il_scan_cancel_timeout(il, 200);
2233
2234 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status);
2235
2236
2237
2238 del_timer_sync(&il->watchdog);
2239
2240
2241 il_clear_ucode_stations(il);
2242 il_dealloc_bcast_stations(il);
2243 il_clear_driver_stations(il);
2244
2245
2246 wake_up_all(&il->wait_command_queue);
2247
2248
2249
2250 if (!exit_pending)
2251 clear_bit(S_EXIT_PENDING, &il->status);
2252
2253
2254 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2255
2256
2257 spin_lock_irqsave(&il->lock, flags);
2258 il_disable_interrupts(il);
2259 spin_unlock_irqrestore(&il->lock, flags);
2260 il3945_synchronize_irq(il);
2261
2262 if (il->mac80211_registered)
2263 ieee80211_stop_queues(il->hw);
2264
2265
2266
2267 if (!il_is_init(il)) {
2268 il->status =
2269 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2270 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2271 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2272 goto exit;
2273 }
2274
2275
2276
2277 il->status &=
2278 test_bit(S_RFKILL, &il->status) << S_RFKILL |
2279 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED |
2280 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR |
2281 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING;
2282
2283
2284
2285
2286
2287
2288 spin_lock_irq(&il->reg_lock);
2289
2290
2291 il3945_hw_txq_ctx_stop(il);
2292 il3945_hw_rxq_stop(il);
2293
2294 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2295 udelay(5);
2296
2297 _il_apm_stop(il);
2298
2299 spin_unlock_irq(&il->reg_lock);
2300
2301 il3945_hw_txq_ctx_free(il);
2302exit:
2303 memset(&il->card_alive, 0, sizeof(struct il_alive_resp));
2304 dev_kfree_skb(il->beacon_skb);
2305 il->beacon_skb = NULL;
2306
2307
2308 il3945_clear_free_frames(il);
2309}
2310
2311static void
2312il3945_down(struct il_priv *il)
2313{
2314 mutex_lock(&il->mutex);
2315 __il3945_down(il);
2316 mutex_unlock(&il->mutex);
2317
2318 il3945_cancel_deferred_work(il);
2319}
2320
2321#define MAX_HW_RESTARTS 5
2322
2323static int
2324il3945_alloc_bcast_station(struct il_priv *il)
2325{
2326 unsigned long flags;
2327 u8 sta_id;
2328
2329 spin_lock_irqsave(&il->sta_lock, flags);
2330 sta_id = il_prep_station(il, il_bcast_addr, false, NULL);
2331 if (sta_id == IL_INVALID_STATION) {
2332 IL_ERR("Unable to prepare broadcast station\n");
2333 spin_unlock_irqrestore(&il->sta_lock, flags);
2334
2335 return -EINVAL;
2336 }
2337
2338 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE;
2339 il->stations[sta_id].used |= IL_STA_BCAST;
2340 spin_unlock_irqrestore(&il->sta_lock, flags);
2341
2342 return 0;
2343}
2344
2345static int
2346__il3945_up(struct il_priv *il)
2347{
2348 int rc, i;
2349
2350 rc = il3945_alloc_bcast_station(il);
2351 if (rc)
2352 return rc;
2353
2354 if (test_bit(S_EXIT_PENDING, &il->status)) {
2355 IL_WARN("Exit pending; will not bring the NIC up\n");
2356 return -EIO;
2357 }
2358
2359 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) {
2360 IL_ERR("ucode not available for device bring up\n");
2361 return -EIO;
2362 }
2363
2364
2365 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2366 clear_bit(S_RFKILL, &il->status);
2367 else {
2368 set_bit(S_RFKILL, &il->status);
2369 return -ERFKILL;
2370 }
2371
2372 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2373
2374 rc = il3945_hw_nic_init(il);
2375 if (rc) {
2376 IL_ERR("Unable to int nic\n");
2377 return rc;
2378 }
2379
2380
2381 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2382 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2383
2384
2385 _il_wr(il, CSR_INT, 0xFFFFFFFF);
2386 il_enable_interrupts(il);
2387
2388
2389 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2390 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2391
2392
2393
2394
2395 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr,
2396 il->ucode_data.len);
2397
2398
2399 if (test_bit(S_RFKILL, &il->status))
2400 return 0;
2401
2402 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2403
2404
2405
2406
2407 rc = il->ops->load_ucode(il);
2408
2409 if (rc) {
2410 IL_ERR("Unable to set up bootstrap uCode: %d\n", rc);
2411 continue;
2412 }
2413
2414
2415 il3945_nic_start(il);
2416
2417 D_INFO(DRV_NAME " is coming up\n");
2418
2419 return 0;
2420 }
2421
2422 set_bit(S_EXIT_PENDING, &il->status);
2423 __il3945_down(il);
2424 clear_bit(S_EXIT_PENDING, &il->status);
2425
2426
2427
2428 IL_ERR("Unable to initialize device after %d attempts.\n", i);
2429 return -EIO;
2430}
2431
2432
2433
2434
2435
2436
2437
2438static void
2439il3945_bg_init_alive_start(struct work_struct *data)
2440{
2441 struct il_priv *il =
2442 container_of(data, struct il_priv, init_alive_start.work);
2443
2444 mutex_lock(&il->mutex);
2445 if (test_bit(S_EXIT_PENDING, &il->status))
2446 goto out;
2447
2448 il3945_init_alive_start(il);
2449out:
2450 mutex_unlock(&il->mutex);
2451}
2452
2453static void
2454il3945_bg_alive_start(struct work_struct *data)
2455{
2456 struct il_priv *il =
2457 container_of(data, struct il_priv, alive_start.work);
2458
2459 mutex_lock(&il->mutex);
2460 if (test_bit(S_EXIT_PENDING, &il->status) || il->txq == NULL)
2461 goto out;
2462
2463 il3945_alive_start(il);
2464out:
2465 mutex_unlock(&il->mutex);
2466}
2467
2468
2469
2470
2471
2472
2473
2474static void
2475il3945_rfkill_poll(struct work_struct *data)
2476{
2477 struct il_priv *il =
2478 container_of(data, struct il_priv, _3945.rfkill_poll.work);
2479 bool old_rfkill = test_bit(S_RFKILL, &il->status);
2480 bool new_rfkill =
2481 !(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
2482
2483 if (new_rfkill != old_rfkill) {
2484 if (new_rfkill)
2485 set_bit(S_RFKILL, &il->status);
2486 else
2487 clear_bit(S_RFKILL, &il->status);
2488
2489 wiphy_rfkill_set_hw_state(il->hw->wiphy, new_rfkill);
2490
2491 D_RF_KILL("RF_KILL bit toggled to %s.\n",
2492 new_rfkill ? "disable radio" : "enable radio");
2493 }
2494
2495
2496
2497 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2498 round_jiffies_relative(2 * HZ));
2499
2500}
2501
2502int
2503il3945_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
2504{
2505 struct il_host_cmd cmd = {
2506 .id = C_SCAN,
2507 .len = sizeof(struct il3945_scan_cmd),
2508 .flags = CMD_SIZE_HUGE,
2509 };
2510 struct il3945_scan_cmd *scan;
2511 u8 n_probes = 0;
2512 enum nl80211_band band;
2513 bool is_active = false;
2514 int ret;
2515 u16 len;
2516
2517 lockdep_assert_held(&il->mutex);
2518
2519 if (!il->scan_cmd) {
2520 il->scan_cmd =
2521 kmalloc(sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE,
2522 GFP_KERNEL);
2523 if (!il->scan_cmd) {
2524 D_SCAN("Fail to allocate scan memory\n");
2525 return -ENOMEM;
2526 }
2527 }
2528 scan = il->scan_cmd;
2529 memset(scan, 0, sizeof(struct il3945_scan_cmd) + IL_MAX_SCAN_SIZE);
2530
2531 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
2532 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
2533
2534 if (il_is_associated(il)) {
2535 u16 interval;
2536 u32 extra;
2537 u32 suspend_time = 100;
2538 u32 scan_suspend_time = 100;
2539
2540 D_INFO("Scanning while associated...\n");
2541
2542 interval = vif->bss_conf.beacon_int;
2543
2544 scan->suspend_time = 0;
2545 scan->max_out_time = cpu_to_le32(200 * 1024);
2546 if (!interval)
2547 interval = suspend_time;
2548
2549
2550
2551
2552
2553
2554
2555 extra = (suspend_time / interval) << 24;
2556 scan_suspend_time =
2557 0xFF0FFFFF & (extra | ((suspend_time % interval) * 1024));
2558
2559 scan->suspend_time = cpu_to_le32(scan_suspend_time);
2560 D_SCAN("suspend_time 0x%X beacon interval %d\n",
2561 scan_suspend_time, interval);
2562 }
2563
2564 if (il->scan_request->n_ssids) {
2565 int i, p = 0;
2566 D_SCAN("Kicking off active scan\n");
2567 for (i = 0; i < il->scan_request->n_ssids; i++) {
2568
2569 if (!il->scan_request->ssids[i].ssid_len)
2570 continue;
2571 scan->direct_scan[p].id = WLAN_EID_SSID;
2572 scan->direct_scan[p].len =
2573 il->scan_request->ssids[i].ssid_len;
2574 memcpy(scan->direct_scan[p].ssid,
2575 il->scan_request->ssids[i].ssid,
2576 il->scan_request->ssids[i].ssid_len);
2577 n_probes++;
2578 p++;
2579 }
2580 is_active = true;
2581 } else
2582 D_SCAN("Kicking off passive scan.\n");
2583
2584
2585
2586 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
2587 scan->tx_cmd.sta_id = il->hw_params.bcast_id;
2588 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2589
2590
2591
2592 switch (il->scan_band) {
2593 case NL80211_BAND_2GHZ:
2594 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
2595 scan->tx_cmd.rate = RATE_1M_PLCP;
2596 band = NL80211_BAND_2GHZ;
2597 break;
2598 case NL80211_BAND_5GHZ:
2599 scan->tx_cmd.rate = RATE_6M_PLCP;
2600 band = NL80211_BAND_5GHZ;
2601 break;
2602 default:
2603 IL_WARN("Invalid scan band\n");
2604 return -EIO;
2605 }
2606
2607
2608
2609
2610
2611
2612 scan->good_CRC_th =
2613 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER;
2614
2615 len =
2616 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data,
2617 vif->addr, il->scan_request->ie,
2618 il->scan_request->ie_len,
2619 IL_MAX_SCAN_SIZE - sizeof(*scan));
2620 scan->tx_cmd.len = cpu_to_le16(len);
2621
2622
2623 scan->flags |= il3945_get_antenna_flags(il);
2624
2625 scan->channel_count =
2626 il3945_get_channels_for_scan(il, band, is_active, n_probes,
2627 (void *)&scan->data[len], vif);
2628 if (scan->channel_count == 0) {
2629 D_SCAN("channel count %d\n", scan->channel_count);
2630 return -EIO;
2631 }
2632
2633 cmd.len +=
2634 le16_to_cpu(scan->tx_cmd.len) +
2635 scan->channel_count * sizeof(struct il3945_scan_channel);
2636 cmd.data = scan;
2637 scan->len = cpu_to_le16(cmd.len);
2638
2639 set_bit(S_SCAN_HW, &il->status);
2640 ret = il_send_cmd_sync(il, &cmd);
2641 if (ret)
2642 clear_bit(S_SCAN_HW, &il->status);
2643 return ret;
2644}
2645
2646void
2647il3945_post_scan(struct il_priv *il)
2648{
2649
2650
2651
2652
2653 if (memcmp(&il->staging, &il->active, sizeof(il->staging)))
2654 il3945_commit_rxon(il);
2655}
2656
2657static void
2658il3945_bg_restart(struct work_struct *data)
2659{
2660 struct il_priv *il = container_of(data, struct il_priv, restart);
2661
2662 if (test_bit(S_EXIT_PENDING, &il->status))
2663 return;
2664
2665 if (test_and_clear_bit(S_FW_ERROR, &il->status)) {
2666 mutex_lock(&il->mutex);
2667 il->is_open = 0;
2668 mutex_unlock(&il->mutex);
2669 il3945_down(il);
2670 ieee80211_restart_hw(il->hw);
2671 } else {
2672 il3945_down(il);
2673
2674 mutex_lock(&il->mutex);
2675 if (test_bit(S_EXIT_PENDING, &il->status)) {
2676 mutex_unlock(&il->mutex);
2677 return;
2678 }
2679
2680 __il3945_up(il);
2681 mutex_unlock(&il->mutex);
2682 }
2683}
2684
2685static void
2686il3945_bg_rx_replenish(struct work_struct *data)
2687{
2688 struct il_priv *il = container_of(data, struct il_priv, rx_replenish);
2689
2690 mutex_lock(&il->mutex);
2691 if (test_bit(S_EXIT_PENDING, &il->status))
2692 goto out;
2693
2694 il3945_rx_replenish(il);
2695out:
2696 mutex_unlock(&il->mutex);
2697}
2698
2699void
2700il3945_post_associate(struct il_priv *il)
2701{
2702 int rc = 0;
2703
2704 if (!il->vif || !il->is_open)
2705 return;
2706
2707 D_ASSOC("Associated as %d to: %pM\n", il->vif->bss_conf.aid,
2708 il->active.bssid_addr);
2709
2710 if (test_bit(S_EXIT_PENDING, &il->status))
2711 return;
2712
2713 il_scan_cancel_timeout(il, 200);
2714
2715 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2716 il3945_commit_rxon(il);
2717
2718 rc = il_send_rxon_timing(il);
2719 if (rc)
2720 IL_WARN("C_RXON_TIMING failed - " "Attempting to continue.\n");
2721
2722 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2723
2724 il->staging.assoc_id = cpu_to_le16(il->vif->bss_conf.aid);
2725
2726 D_ASSOC("assoc id %d beacon interval %d\n", il->vif->bss_conf.aid,
2727 il->vif->bss_conf.beacon_int);
2728
2729 if (il->vif->bss_conf.use_short_preamble)
2730 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2731 else
2732 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2733
2734 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2735 if (il->vif->bss_conf.use_short_slot)
2736 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2737 else
2738 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2739 }
2740
2741 il3945_commit_rxon(il);
2742
2743 switch (il->vif->type) {
2744 case NL80211_IFTYPE_STATION:
2745 il3945_rate_scale_init(il->hw, IL_AP_ID);
2746 break;
2747 case NL80211_IFTYPE_ADHOC:
2748 il3945_send_beacon_cmd(il);
2749 break;
2750 default:
2751 IL_ERR("%s Should not be called in %d mode\n", __func__,
2752 il->vif->type);
2753 break;
2754 }
2755}
2756
2757
2758
2759
2760
2761
2762
2763#define UCODE_READY_TIMEOUT (2 * HZ)
2764
2765static int
2766il3945_mac_start(struct ieee80211_hw *hw)
2767{
2768 struct il_priv *il = hw->priv;
2769 int ret;
2770
2771
2772 mutex_lock(&il->mutex);
2773 D_MAC80211("enter\n");
2774
2775
2776
2777
2778 if (!il->ucode_code.len) {
2779 ret = il3945_read_ucode(il);
2780 if (ret) {
2781 IL_ERR("Could not read microcode: %d\n", ret);
2782 mutex_unlock(&il->mutex);
2783 goto out_release_irq;
2784 }
2785 }
2786
2787 ret = __il3945_up(il);
2788
2789 mutex_unlock(&il->mutex);
2790
2791 if (ret)
2792 goto out_release_irq;
2793
2794 D_INFO("Start UP work.\n");
2795
2796
2797
2798 ret = wait_event_timeout(il->wait_command_queue,
2799 test_bit(S_READY, &il->status),
2800 UCODE_READY_TIMEOUT);
2801 if (!ret) {
2802 if (!test_bit(S_READY, &il->status)) {
2803 IL_ERR("Wait for START_ALIVE timeout after %dms.\n",
2804 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2805 ret = -ETIMEDOUT;
2806 goto out_release_irq;
2807 }
2808 }
2809
2810
2811
2812 cancel_delayed_work(&il->_3945.rfkill_poll);
2813
2814 il->is_open = 1;
2815 D_MAC80211("leave\n");
2816 return 0;
2817
2818out_release_irq:
2819 il->is_open = 0;
2820 D_MAC80211("leave - failed\n");
2821 return ret;
2822}
2823
2824static void
2825il3945_mac_stop(struct ieee80211_hw *hw)
2826{
2827 struct il_priv *il = hw->priv;
2828
2829 D_MAC80211("enter\n");
2830
2831 if (!il->is_open) {
2832 D_MAC80211("leave - skip\n");
2833 return;
2834 }
2835
2836 il->is_open = 0;
2837
2838 il3945_down(il);
2839
2840 flush_workqueue(il->workqueue);
2841
2842
2843 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll,
2844 round_jiffies_relative(2 * HZ));
2845
2846 D_MAC80211("leave\n");
2847}
2848
2849static void
2850il3945_mac_tx(struct ieee80211_hw *hw,
2851 struct ieee80211_tx_control *control,
2852 struct sk_buff *skb)
2853{
2854 struct il_priv *il = hw->priv;
2855
2856 D_MAC80211("enter\n");
2857
2858 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2859 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2860
2861 if (il3945_tx_skb(il, control->sta, skb))
2862 dev_kfree_skb_any(skb);
2863
2864 D_MAC80211("leave\n");
2865}
2866
2867void
2868il3945_config_ap(struct il_priv *il)
2869{
2870 struct ieee80211_vif *vif = il->vif;
2871 int rc = 0;
2872
2873 if (test_bit(S_EXIT_PENDING, &il->status))
2874 return;
2875
2876
2877 if (!(il_is_associated(il))) {
2878
2879
2880 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2881 il3945_commit_rxon(il);
2882
2883
2884 rc = il_send_rxon_timing(il);
2885 if (rc)
2886 IL_WARN("C_RXON_TIMING failed - "
2887 "Attempting to continue.\n");
2888
2889 il->staging.assoc_id = 0;
2890
2891 if (vif->bss_conf.use_short_preamble)
2892 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2893 else
2894 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2895
2896 if (il->staging.flags & RXON_FLG_BAND_24G_MSK) {
2897 if (vif->bss_conf.use_short_slot)
2898 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
2899 else
2900 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2901 }
2902
2903 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2904 il3945_commit_rxon(il);
2905 }
2906 il3945_send_beacon_cmd(il);
2907}
2908
2909static int
2910il3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2911 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2912 struct ieee80211_key_conf *key)
2913{
2914 struct il_priv *il = hw->priv;
2915 int ret = 0;
2916 u8 sta_id = IL_INVALID_STATION;
2917 u8 static_key;
2918
2919 D_MAC80211("enter\n");
2920
2921 if (il3945_mod_params.sw_crypto) {
2922 D_MAC80211("leave - hwcrypto disabled\n");
2923 return -EOPNOTSUPP;
2924 }
2925
2926
2927
2928
2929
2930 if (vif->type == NL80211_IFTYPE_ADHOC &&
2931 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2932 D_MAC80211("leave - IBSS RSN\n");
2933 return -EOPNOTSUPP;
2934 }
2935
2936 static_key = !il_is_associated(il);
2937
2938 if (!static_key) {
2939 sta_id = il_sta_id_or_broadcast(il, sta);
2940 if (sta_id == IL_INVALID_STATION) {
2941 D_MAC80211("leave - station not found\n");
2942 return -EINVAL;
2943 }
2944 }
2945
2946 mutex_lock(&il->mutex);
2947 il_scan_cancel_timeout(il, 100);
2948
2949 switch (cmd) {
2950 case SET_KEY:
2951 if (static_key)
2952 ret = il3945_set_static_key(il, key);
2953 else
2954 ret = il3945_set_dynamic_key(il, key, sta_id);
2955 D_MAC80211("enable hwcrypto key\n");
2956 break;
2957 case DISABLE_KEY:
2958 if (static_key)
2959 ret = il3945_remove_static_key(il);
2960 else
2961 ret = il3945_clear_sta_key_info(il, sta_id);
2962 D_MAC80211("disable hwcrypto key\n");
2963 break;
2964 default:
2965 ret = -EINVAL;
2966 }
2967
2968 D_MAC80211("leave ret %d\n", ret);
2969 mutex_unlock(&il->mutex);
2970
2971 return ret;
2972}
2973
2974static int
2975il3945_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2976 struct ieee80211_sta *sta)
2977{
2978 struct il_priv *il = hw->priv;
2979 struct il3945_sta_priv *sta_priv = (void *)sta->drv_priv;
2980 int ret;
2981 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
2982 u8 sta_id;
2983
2984 mutex_lock(&il->mutex);
2985 D_INFO("station %pM\n", sta->addr);
2986 sta_priv->common.sta_id = IL_INVALID_STATION;
2987
2988 ret = il_add_station_common(il, sta->addr, is_ap, sta, &sta_id);
2989 if (ret) {
2990 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret);
2991
2992 mutex_unlock(&il->mutex);
2993 return ret;
2994 }
2995
2996 sta_priv->common.sta_id = sta_id;
2997
2998
2999 D_INFO("Initializing rate scaling for station %pM\n", sta->addr);
3000 il3945_rs_rate_init(il, sta, sta_id);
3001 mutex_unlock(&il->mutex);
3002
3003 return 0;
3004}
3005
3006static void
3007il3945_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
3008 unsigned int *total_flags, u64 multicast)
3009{
3010 struct il_priv *il = hw->priv;
3011 __le32 filter_or = 0, filter_nand = 0;
3012
3013#define CHK(test, flag) do { \
3014 if (*total_flags & (test)) \
3015 filter_or |= (flag); \
3016 else \
3017 filter_nand |= (flag); \
3018 } while (0)
3019
3020 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags,
3021 *total_flags);
3022
3023 CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK);
3024 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3025 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3026
3027#undef CHK
3028
3029 mutex_lock(&il->mutex);
3030
3031 il->staging.filter_flags &= ~filter_nand;
3032 il->staging.filter_flags |= filter_or;
3033
3034
3035
3036
3037
3038
3039
3040 mutex_unlock(&il->mutex);
3041
3042
3043
3044
3045
3046
3047
3048 *total_flags &=
3049 FIF_OTHER_BSS | FIF_ALLMULTI |
3050 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3051}
3052
3053
3054
3055
3056
3057
3058
3059#ifdef CONFIG_IWLEGACY_DEBUG
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072static ssize_t
3073il3945_show_debug_level(struct device *d, struct device_attribute *attr,
3074 char *buf)
3075{
3076 struct il_priv *il = dev_get_drvdata(d);
3077 return sprintf(buf, "0x%08X\n", il_get_debug_level(il));
3078}
3079
3080static ssize_t
3081il3945_store_debug_level(struct device *d, struct device_attribute *attr,
3082 const char *buf, size_t count)
3083{
3084 struct il_priv *il = dev_get_drvdata(d);
3085 unsigned long val;
3086 int ret;
3087
3088 ret = kstrtoul(buf, 0, &val);
3089 if (ret)
3090 IL_INFO("%s is not in hex or decimal form.\n", buf);
3091 else
3092 il->debug_level = val;
3093
3094 return strnlen(buf, count);
3095}
3096
3097static DEVICE_ATTR(debug_level, 0644, il3945_show_debug_level,
3098 il3945_store_debug_level);
3099
3100#endif
3101
3102static ssize_t
3103il3945_show_temperature(struct device *d, struct device_attribute *attr,
3104 char *buf)
3105{
3106 struct il_priv *il = dev_get_drvdata(d);
3107
3108 if (!il_is_alive(il))
3109 return -EAGAIN;
3110
3111 return sprintf(buf, "%d\n", il3945_hw_get_temperature(il));
3112}
3113
3114static DEVICE_ATTR(temperature, 0444, il3945_show_temperature, NULL);
3115
3116static ssize_t
3117il3945_show_tx_power(struct device *d, struct device_attribute *attr, char *buf)
3118{
3119 struct il_priv *il = dev_get_drvdata(d);
3120 return sprintf(buf, "%d\n", il->tx_power_user_lmt);
3121}
3122
3123static ssize_t
3124il3945_store_tx_power(struct device *d, struct device_attribute *attr,
3125 const char *buf, size_t count)
3126{
3127 struct il_priv *il = dev_get_drvdata(d);
3128 char *p = (char *)buf;
3129 u32 val;
3130
3131 val = simple_strtoul(p, &p, 10);
3132 if (p == buf)
3133 IL_INFO(": %s is not in decimal form.\n", buf);
3134 else
3135 il3945_hw_reg_set_txpower(il, val);
3136
3137 return count;
3138}
3139
3140static DEVICE_ATTR(tx_power, 0644, il3945_show_tx_power, il3945_store_tx_power);
3141
3142static ssize_t
3143il3945_show_flags(struct device *d, struct device_attribute *attr, char *buf)
3144{
3145 struct il_priv *il = dev_get_drvdata(d);
3146
3147 return sprintf(buf, "0x%04X\n", il->active.flags);
3148}
3149
3150static ssize_t
3151il3945_store_flags(struct device *d, struct device_attribute *attr,
3152 const char *buf, size_t count)
3153{
3154 struct il_priv *il = dev_get_drvdata(d);
3155 u32 flags = simple_strtoul(buf, NULL, 0);
3156
3157 mutex_lock(&il->mutex);
3158 if (le32_to_cpu(il->staging.flags) != flags) {
3159
3160 if (il_scan_cancel_timeout(il, 100))
3161 IL_WARN("Could not cancel scan.\n");
3162 else {
3163 D_INFO("Committing rxon.flags = 0x%04X\n", flags);
3164 il->staging.flags = cpu_to_le32(flags);
3165 il3945_commit_rxon(il);
3166 }
3167 }
3168 mutex_unlock(&il->mutex);
3169
3170 return count;
3171}
3172
3173static DEVICE_ATTR(flags, 0644, il3945_show_flags, il3945_store_flags);
3174
3175static ssize_t
3176il3945_show_filter_flags(struct device *d, struct device_attribute *attr,
3177 char *buf)
3178{
3179 struct il_priv *il = dev_get_drvdata(d);
3180
3181 return sprintf(buf, "0x%04X\n", le32_to_cpu(il->active.filter_flags));
3182}
3183
3184static ssize_t
3185il3945_store_filter_flags(struct device *d, struct device_attribute *attr,
3186 const char *buf, size_t count)
3187{
3188 struct il_priv *il = dev_get_drvdata(d);
3189 u32 filter_flags = simple_strtoul(buf, NULL, 0);
3190
3191 mutex_lock(&il->mutex);
3192 if (le32_to_cpu(il->staging.filter_flags) != filter_flags) {
3193
3194 if (il_scan_cancel_timeout(il, 100))
3195 IL_WARN("Could not cancel scan.\n");
3196 else {
3197 D_INFO("Committing rxon.filter_flags = " "0x%04X\n",
3198 filter_flags);
3199 il->staging.filter_flags = cpu_to_le32(filter_flags);
3200 il3945_commit_rxon(il);
3201 }
3202 }
3203 mutex_unlock(&il->mutex);
3204
3205 return count;
3206}
3207
3208static DEVICE_ATTR(filter_flags, 0644, il3945_show_filter_flags,
3209 il3945_store_filter_flags);
3210
3211static ssize_t
3212il3945_show_measurement(struct device *d, struct device_attribute *attr,
3213 char *buf)
3214{
3215 struct il_priv *il = dev_get_drvdata(d);
3216 struct il_spectrum_notification measure_report;
3217 u32 size = sizeof(measure_report), len = 0, ofs = 0;
3218 u8 *data = (u8 *) &measure_report;
3219 unsigned long flags;
3220
3221 spin_lock_irqsave(&il->lock, flags);
3222 if (!(il->measurement_status & MEASUREMENT_READY)) {
3223 spin_unlock_irqrestore(&il->lock, flags);
3224 return 0;
3225 }
3226 memcpy(&measure_report, &il->measure_report, size);
3227 il->measurement_status = 0;
3228 spin_unlock_irqrestore(&il->lock, flags);
3229
3230 while (size && PAGE_SIZE - len) {
3231 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3232 PAGE_SIZE - len, true);
3233 len = strlen(buf);
3234 if (PAGE_SIZE - len)
3235 buf[len++] = '\n';
3236
3237 ofs += 16;
3238 size -= min(size, 16U);
3239 }
3240
3241 return len;
3242}
3243
3244static ssize_t
3245il3945_store_measurement(struct device *d, struct device_attribute *attr,
3246 const char *buf, size_t count)
3247{
3248 struct il_priv *il = dev_get_drvdata(d);
3249 struct ieee80211_measurement_params params = {
3250 .channel = le16_to_cpu(il->active.channel),
3251 .start_time = cpu_to_le64(il->_3945.last_tsf),
3252 .duration = cpu_to_le16(1),
3253 };
3254 u8 type = IL_MEASURE_BASIC;
3255 u8 buffer[32];
3256 u8 channel;
3257
3258 if (count) {
3259 char *p = buffer;
3260 strlcpy(buffer, buf, sizeof(buffer));
3261 channel = simple_strtoul(p, NULL, 0);
3262 if (channel)
3263 params.channel = channel;
3264
3265 p = buffer;
3266 while (*p && *p != ' ')
3267 p++;
3268 if (*p)
3269 type = simple_strtoul(p + 1, NULL, 0);
3270 }
3271
3272 D_INFO("Invoking measurement of type %d on " "channel %d (for '%s')\n",
3273 type, params.channel, buf);
3274 il3945_get_measurement(il, ¶ms, type);
3275
3276 return count;
3277}
3278
3279static DEVICE_ATTR(measurement, 0600, il3945_show_measurement,
3280 il3945_store_measurement);
3281
3282static ssize_t
3283il3945_store_retry_rate(struct device *d, struct device_attribute *attr,
3284 const char *buf, size_t count)
3285{
3286 struct il_priv *il = dev_get_drvdata(d);
3287
3288 il->retry_rate = simple_strtoul(buf, NULL, 0);
3289 if (il->retry_rate <= 0)
3290 il->retry_rate = 1;
3291
3292 return count;
3293}
3294
3295static ssize_t
3296il3945_show_retry_rate(struct device *d, struct device_attribute *attr,
3297 char *buf)
3298{
3299 struct il_priv *il = dev_get_drvdata(d);
3300 return sprintf(buf, "%d", il->retry_rate);
3301}
3302
3303static DEVICE_ATTR(retry_rate, 0600, il3945_show_retry_rate,
3304 il3945_store_retry_rate);
3305
3306static ssize_t
3307il3945_show_channels(struct device *d, struct device_attribute *attr, char *buf)
3308{
3309
3310 return 0;
3311}
3312
3313static DEVICE_ATTR(channels, 0400, il3945_show_channels, NULL);
3314
3315static ssize_t
3316il3945_show_antenna(struct device *d, struct device_attribute *attr, char *buf)
3317{
3318 struct il_priv *il = dev_get_drvdata(d);
3319
3320 if (!il_is_alive(il))
3321 return -EAGAIN;
3322
3323 return sprintf(buf, "%d\n", il3945_mod_params.antenna);
3324}
3325
3326static ssize_t
3327il3945_store_antenna(struct device *d, struct device_attribute *attr,
3328 const char *buf, size_t count)
3329{
3330 struct il_priv *il __maybe_unused = dev_get_drvdata(d);
3331 int ant;
3332
3333 if (count == 0)
3334 return 0;
3335
3336 if (sscanf(buf, "%1i", &ant) != 1) {
3337 D_INFO("not in hex or decimal form.\n");
3338 return count;
3339 }
3340
3341 if (ant >= 0 && ant <= 2) {
3342 D_INFO("Setting antenna select to %d.\n", ant);
3343 il3945_mod_params.antenna = (enum il3945_antenna)ant;
3344 } else
3345 D_INFO("Bad antenna select value %d.\n", ant);
3346
3347 return count;
3348}
3349
3350static DEVICE_ATTR(antenna, 0644, il3945_show_antenna, il3945_store_antenna);
3351
3352static ssize_t
3353il3945_show_status(struct device *d, struct device_attribute *attr, char *buf)
3354{
3355 struct il_priv *il = dev_get_drvdata(d);
3356 if (!il_is_alive(il))
3357 return -EAGAIN;
3358 return sprintf(buf, "0x%08x\n", (int)il->status);
3359}
3360
3361static DEVICE_ATTR(status, 0444, il3945_show_status, NULL);
3362
3363static ssize_t
3364il3945_dump_error_log(struct device *d, struct device_attribute *attr,
3365 const char *buf, size_t count)
3366{
3367 struct il_priv *il = dev_get_drvdata(d);
3368 char *p = (char *)buf;
3369
3370 if (p[0] == '1')
3371 il3945_dump_nic_error_log(il);
3372
3373 return strnlen(buf, count);
3374}
3375
3376static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log);
3377
3378
3379
3380
3381
3382
3383
3384static void
3385il3945_setup_deferred_work(struct il_priv *il)
3386{
3387 il->workqueue = create_singlethread_workqueue(DRV_NAME);
3388
3389 init_waitqueue_head(&il->wait_command_queue);
3390
3391 INIT_WORK(&il->restart, il3945_bg_restart);
3392 INIT_WORK(&il->rx_replenish, il3945_bg_rx_replenish);
3393 INIT_DELAYED_WORK(&il->init_alive_start, il3945_bg_init_alive_start);
3394 INIT_DELAYED_WORK(&il->alive_start, il3945_bg_alive_start);
3395 INIT_DELAYED_WORK(&il->_3945.rfkill_poll, il3945_rfkill_poll);
3396
3397 il_setup_scan_deferred_work(il);
3398
3399 il3945_hw_setup_deferred_work(il);
3400
3401 timer_setup(&il->watchdog, il_bg_watchdog, 0);
3402
3403 tasklet_init(&il->irq_tasklet,
3404 (void (*)(unsigned long))il3945_irq_tasklet,
3405 (unsigned long)il);
3406}
3407
3408static void
3409il3945_cancel_deferred_work(struct il_priv *il)
3410{
3411 il3945_hw_cancel_deferred_work(il);
3412
3413 cancel_delayed_work_sync(&il->init_alive_start);
3414 cancel_delayed_work(&il->alive_start);
3415
3416 il_cancel_scan_deferred_work(il);
3417}
3418
3419static struct attribute *il3945_sysfs_entries[] = {
3420 &dev_attr_antenna.attr,
3421 &dev_attr_channels.attr,
3422 &dev_attr_dump_errors.attr,
3423 &dev_attr_flags.attr,
3424 &dev_attr_filter_flags.attr,
3425 &dev_attr_measurement.attr,
3426 &dev_attr_retry_rate.attr,
3427 &dev_attr_status.attr,
3428 &dev_attr_temperature.attr,
3429 &dev_attr_tx_power.attr,
3430#ifdef CONFIG_IWLEGACY_DEBUG
3431 &dev_attr_debug_level.attr,
3432#endif
3433 NULL
3434};
3435
3436static const struct attribute_group il3945_attribute_group = {
3437 .name = NULL,
3438 .attrs = il3945_sysfs_entries,
3439};
3440
3441static struct ieee80211_ops il3945_mac_ops __ro_after_init = {
3442 .tx = il3945_mac_tx,
3443 .start = il3945_mac_start,
3444 .stop = il3945_mac_stop,
3445 .add_interface = il_mac_add_interface,
3446 .remove_interface = il_mac_remove_interface,
3447 .change_interface = il_mac_change_interface,
3448 .config = il_mac_config,
3449 .configure_filter = il3945_configure_filter,
3450 .set_key = il3945_mac_set_key,
3451 .conf_tx = il_mac_conf_tx,
3452 .reset_tsf = il_mac_reset_tsf,
3453 .bss_info_changed = il_mac_bss_info_changed,
3454 .hw_scan = il_mac_hw_scan,
3455 .sta_add = il3945_mac_sta_add,
3456 .sta_remove = il_mac_sta_remove,
3457 .tx_last_beacon = il_mac_tx_last_beacon,
3458 .flush = il_mac_flush,
3459};
3460
3461static int
3462il3945_init_drv(struct il_priv *il)
3463{
3464 int ret;
3465 struct il3945_eeprom *eeprom = (struct il3945_eeprom *)il->eeprom;
3466
3467 il->retry_rate = 1;
3468 il->beacon_skb = NULL;
3469
3470 spin_lock_init(&il->sta_lock);
3471 spin_lock_init(&il->hcmd_lock);
3472
3473 INIT_LIST_HEAD(&il->free_frames);
3474
3475 mutex_init(&il->mutex);
3476
3477 il->ieee_channels = NULL;
3478 il->ieee_rates = NULL;
3479 il->band = NL80211_BAND_2GHZ;
3480
3481 il->iw_mode = NL80211_IFTYPE_STATION;
3482 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF;
3483
3484
3485 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD;
3486
3487 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3488 IL_WARN("Unsupported EEPROM version: 0x%04X\n",
3489 eeprom->version);
3490 ret = -EINVAL;
3491 goto err;
3492 }
3493 ret = il_init_channel_map(il);
3494 if (ret) {
3495 IL_ERR("initializing regulatory failed: %d\n", ret);
3496 goto err;
3497 }
3498
3499
3500 if (il3945_txpower_set_from_eeprom(il)) {
3501 ret = -EIO;
3502 goto err_free_channel_map;
3503 }
3504
3505 ret = il_init_geos(il);
3506 if (ret) {
3507 IL_ERR("initializing geos failed: %d\n", ret);
3508 goto err_free_channel_map;
3509 }
3510 il3945_init_hw_rates(il, il->ieee_rates);
3511
3512 return 0;
3513
3514err_free_channel_map:
3515 il_free_channel_map(il);
3516err:
3517 return ret;
3518}
3519
3520#define IL3945_MAX_PROBE_REQUEST 200
3521
3522static int
3523il3945_setup_mac(struct il_priv *il)
3524{
3525 int ret;
3526 struct ieee80211_hw *hw = il->hw;
3527
3528 hw->rate_control_algorithm = "iwl-3945-rs";
3529 hw->sta_data_size = sizeof(struct il3945_sta_priv);
3530 hw->vif_data_size = sizeof(struct il_vif_priv);
3531
3532
3533 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3534 ieee80211_hw_set(hw, SUPPORTS_PS);
3535 ieee80211_hw_set(hw, SIGNAL_DBM);
3536 ieee80211_hw_set(hw, SPECTRUM_MGMT);
3537
3538 hw->wiphy->interface_modes =
3539 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
3540
3541 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
3542 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG |
3543 REGULATORY_DISABLE_BEACON_HINTS;
3544
3545 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3546
3547 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX_3945;
3548
3549 hw->wiphy->max_scan_ie_len = IL3945_MAX_PROBE_REQUEST - 24 - 2;
3550
3551
3552 hw->queues = 4;
3553
3554 if (il->bands[NL80211_BAND_2GHZ].n_channels)
3555 il->hw->wiphy->bands[NL80211_BAND_2GHZ] =
3556 &il->bands[NL80211_BAND_2GHZ];
3557
3558 if (il->bands[NL80211_BAND_5GHZ].n_channels)
3559 il->hw->wiphy->bands[NL80211_BAND_5GHZ] =
3560 &il->bands[NL80211_BAND_5GHZ];
3561
3562 il_leds_init(il);
3563
3564 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
3565
3566 ret = ieee80211_register_hw(il->hw);
3567 if (ret) {
3568 IL_ERR("Failed to register hw (error %d)\n", ret);
3569 return ret;
3570 }
3571 il->mac80211_registered = 1;
3572
3573 return 0;
3574}
3575
3576static int
3577il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3578{
3579 int err = 0;
3580 struct il_priv *il;
3581 struct ieee80211_hw *hw;
3582 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data);
3583 struct il3945_eeprom *eeprom;
3584 unsigned long flags;
3585
3586
3587
3588
3589
3590 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il3945_mac_ops);
3591 if (!hw) {
3592 err = -ENOMEM;
3593 goto out;
3594 }
3595 il = hw->priv;
3596 il->hw = hw;
3597 SET_IEEE80211_DEV(hw, &pdev->dev);
3598
3599 il->cmd_queue = IL39_CMD_QUEUE_NUM;
3600
3601 D_INFO("*** LOAD DRIVER ***\n");
3602 il->cfg = cfg;
3603 il->ops = &il3945_ops;
3604#ifdef CONFIG_IWLEGACY_DEBUGFS
3605 il->debugfs_ops = &il3945_debugfs_ops;
3606#endif
3607 il->pci_dev = pdev;
3608 il->inta_mask = CSR_INI_SET_MASK;
3609
3610
3611
3612
3613 pci_disable_link_state(pdev,
3614 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3615 PCIE_LINK_STATE_CLKPM);
3616
3617 if (pci_enable_device(pdev)) {
3618 err = -ENODEV;
3619 goto out_ieee80211_free_hw;
3620 }
3621
3622 pci_set_master(pdev);
3623
3624 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3625 if (!err)
3626 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3627 if (err) {
3628 IL_WARN("No suitable DMA available.\n");
3629 goto out_pci_disable_device;
3630 }
3631
3632 pci_set_drvdata(pdev, il);
3633 err = pci_request_regions(pdev, DRV_NAME);
3634 if (err)
3635 goto out_pci_disable_device;
3636
3637
3638
3639
3640 il->hw_base = pci_ioremap_bar(pdev, 0);
3641 if (!il->hw_base) {
3642 err = -ENODEV;
3643 goto out_pci_release_regions;
3644 }
3645
3646 D_INFO("pci_resource_len = 0x%08llx\n",
3647 (unsigned long long)pci_resource_len(pdev, 0));
3648 D_INFO("pci_resource_base = %p\n", il->hw_base);
3649
3650
3651
3652 pci_write_config_byte(pdev, 0x41, 0x00);
3653
3654
3655
3656
3657 spin_lock_init(&il->reg_lock);
3658 spin_lock_init(&il->lock);
3659
3660
3661
3662
3663
3664
3665 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3666
3667
3668
3669
3670
3671
3672 err = il_eeprom_init(il);
3673 if (err) {
3674 IL_ERR("Unable to init EEPROM\n");
3675 goto out_iounmap;
3676 }
3677
3678 eeprom = (struct il3945_eeprom *)il->eeprom;
3679 D_INFO("MAC address: %pM\n", eeprom->mac_address);
3680 SET_IEEE80211_PERM_ADDR(il->hw, eeprom->mac_address);
3681
3682
3683
3684
3685
3686 err = il3945_hw_set_hw_params(il);
3687 if (err) {
3688 IL_ERR("failed to set hw settings\n");
3689 goto out_eeprom_free;
3690 }
3691
3692
3693
3694
3695
3696 err = il3945_init_drv(il);
3697 if (err) {
3698 IL_ERR("initializing driver failed\n");
3699 goto out_unset_hw_params;
3700 }
3701
3702 IL_INFO("Detected Intel Wireless WiFi Link %s\n", il->cfg->name);
3703
3704
3705
3706
3707
3708 spin_lock_irqsave(&il->lock, flags);
3709 il_disable_interrupts(il);
3710 spin_unlock_irqrestore(&il->lock, flags);
3711
3712 pci_enable_msi(il->pci_dev);
3713
3714 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il);
3715 if (err) {
3716 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq);
3717 goto out_disable_msi;
3718 }
3719
3720 err = sysfs_create_group(&pdev->dev.kobj, &il3945_attribute_group);
3721 if (err) {
3722 IL_ERR("failed to create sysfs device attributes\n");
3723 goto out_release_irq;
3724 }
3725
3726 il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]);
3727 il3945_setup_deferred_work(il);
3728 il3945_setup_handlers(il);
3729 il_power_initialize(il);
3730
3731
3732
3733
3734
3735 il_enable_interrupts(il);
3736
3737 err = il3945_setup_mac(il);
3738 if (err)
3739 goto out_remove_sysfs;
3740
3741 il_dbgfs_register(il, DRV_NAME);
3742
3743
3744 queue_delayed_work(il->workqueue, &il->_3945.rfkill_poll, 2 * HZ);
3745
3746 return 0;
3747
3748out_remove_sysfs:
3749 destroy_workqueue(il->workqueue);
3750 il->workqueue = NULL;
3751 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3752out_release_irq:
3753 free_irq(il->pci_dev->irq, il);
3754out_disable_msi:
3755 pci_disable_msi(il->pci_dev);
3756 il_free_geos(il);
3757 il_free_channel_map(il);
3758out_unset_hw_params:
3759 il3945_unset_hw_params(il);
3760out_eeprom_free:
3761 il_eeprom_free(il);
3762out_iounmap:
3763 iounmap(il->hw_base);
3764out_pci_release_regions:
3765 pci_release_regions(pdev);
3766out_pci_disable_device:
3767 pci_disable_device(pdev);
3768out_ieee80211_free_hw:
3769 ieee80211_free_hw(il->hw);
3770out:
3771 return err;
3772}
3773
3774static void
3775il3945_pci_remove(struct pci_dev *pdev)
3776{
3777 struct il_priv *il = pci_get_drvdata(pdev);
3778 unsigned long flags;
3779
3780 if (!il)
3781 return;
3782
3783 D_INFO("*** UNLOAD DRIVER ***\n");
3784
3785 il_dbgfs_unregister(il);
3786
3787 set_bit(S_EXIT_PENDING, &il->status);
3788
3789 il_leds_exit(il);
3790
3791 if (il->mac80211_registered) {
3792 ieee80211_unregister_hw(il->hw);
3793 il->mac80211_registered = 0;
3794 } else {
3795 il3945_down(il);
3796 }
3797
3798
3799
3800
3801
3802
3803
3804
3805 il_apm_stop(il);
3806
3807
3808
3809
3810 spin_lock_irqsave(&il->lock, flags);
3811 il_disable_interrupts(il);
3812 spin_unlock_irqrestore(&il->lock, flags);
3813
3814 il3945_synchronize_irq(il);
3815
3816 sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group);
3817
3818 cancel_delayed_work_sync(&il->_3945.rfkill_poll);
3819
3820 il3945_dealloc_ucode_pci(il);
3821
3822 if (il->rxq.bd)
3823 il3945_rx_queue_free(il, &il->rxq);
3824 il3945_hw_txq_ctx_free(il);
3825
3826 il3945_unset_hw_params(il);
3827
3828
3829 flush_workqueue(il->workqueue);
3830
3831
3832
3833
3834 destroy_workqueue(il->workqueue);
3835 il->workqueue = NULL;
3836
3837 free_irq(pdev->irq, il);
3838 pci_disable_msi(pdev);
3839
3840 iounmap(il->hw_base);
3841 pci_release_regions(pdev);
3842 pci_disable_device(pdev);
3843
3844 il_free_channel_map(il);
3845 il_free_geos(il);
3846 kfree(il->scan_cmd);
3847 dev_kfree_skb(il->beacon_skb);
3848 ieee80211_free_hw(il->hw);
3849}
3850
3851
3852
3853
3854
3855
3856
3857static struct pci_driver il3945_driver = {
3858 .name = DRV_NAME,
3859 .id_table = il3945_hw_card_ids,
3860 .probe = il3945_pci_probe,
3861 .remove = il3945_pci_remove,
3862 .driver.pm = IL_LEGACY_PM_OPS,
3863};
3864
3865static int __init
3866il3945_init(void)
3867{
3868
3869 int ret;
3870 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3871 pr_info(DRV_COPYRIGHT "\n");
3872
3873
3874
3875
3876
3877 if (il3945_mod_params.disable_hw_scan) {
3878 pr_info("hw_scan is disabled\n");
3879 il3945_mac_ops.hw_scan = NULL;
3880 }
3881
3882 ret = il3945_rate_control_register();
3883 if (ret) {
3884 pr_err("Unable to register rate control algorithm: %d\n", ret);
3885 return ret;
3886 }
3887
3888 ret = pci_register_driver(&il3945_driver);
3889 if (ret) {
3890 pr_err("Unable to initialize PCI module\n");
3891 goto error_register;
3892 }
3893
3894 return ret;
3895
3896error_register:
3897 il3945_rate_control_unregister();
3898 return ret;
3899}
3900
3901static void __exit
3902il3945_exit(void)
3903{
3904 pci_unregister_driver(&il3945_driver);
3905 il3945_rate_control_unregister();
3906}
3907
3908MODULE_FIRMWARE(IL3945_MODULE_FIRMWARE(IL3945_UCODE_API_MAX));
3909
3910module_param_named(antenna, il3945_mod_params.antenna, int, 0444);
3911MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3912module_param_named(swcrypto, il3945_mod_params.sw_crypto, int, 0444);
3913MODULE_PARM_DESC(swcrypto, "using software crypto (default 1 [software])");
3914module_param_named(disable_hw_scan, il3945_mod_params.disable_hw_scan, int,
3915 0444);
3916MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 1)");
3917#ifdef CONFIG_IWLEGACY_DEBUG
3918module_param_named(debug, il_debug_level, uint, 0644);
3919MODULE_PARM_DESC(debug, "debug output mask");
3920#endif
3921module_param_named(fw_restart, il3945_mod_params.restart_fw, int, 0444);
3922MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
3923
3924module_exit(il3945_exit);
3925module_init(il3945_init);
3926