1
2
3#ifndef __MT7603_H
4#define __MT7603_H
5
6#include <linux/interrupt.h>
7#include <linux/ktime.h>
8#include "../mt76.h"
9#include "regs.h"
10
11#define MT7603_MAX_INTERFACES 4
12#define MT7603_WTBL_SIZE 128
13#define MT7603_WTBL_RESERVED (MT7603_WTBL_SIZE - 1)
14#define MT7603_WTBL_STA (MT7603_WTBL_RESERVED - MT7603_MAX_INTERFACES)
15
16#define MT7603_RATE_RETRY 2
17
18#define MT7603_RX_RING_SIZE 128
19
20#define MT7603_FIRMWARE_E1 "mt7603_e1.bin"
21#define MT7603_FIRMWARE_E2 "mt7603_e2.bin"
22#define MT7628_FIRMWARE_E1 "mt7628_e1.bin"
23#define MT7628_FIRMWARE_E2 "mt7628_e2.bin"
24
25#define MT7603_EEPROM_SIZE 1024
26
27#define MT_AGG_SIZE_LIMIT(_n) (((_n) + 1) * 4)
28
29#define MT7603_PRE_TBTT_TIME 5000
30
31#define MT7603_WATCHDOG_TIME 100
32#define MT7603_WATCHDOG_TIMEOUT 10
33
34#define MT7603_EDCCA_BLOCK_TH 10
35
36#define MT7603_CFEND_RATE_DEFAULT 0x69
37#define MT7603_CFEND_RATE_11B 0x03
38
39struct mt7603_vif;
40struct mt7603_sta;
41
42enum {
43 MT7603_REV_E1 = 0x00,
44 MT7603_REV_E2 = 0x10,
45 MT7628_REV_E1 = 0x8a00,
46};
47
48enum mt7603_bw {
49 MT_BW_20,
50 MT_BW_40,
51 MT_BW_80,
52};
53
54struct mt7603_rate_set {
55 struct ieee80211_tx_rate probe_rate;
56 struct ieee80211_tx_rate rates[4];
57};
58
59struct mt7603_sta {
60 struct mt76_wcid wcid;
61
62 struct mt7603_vif *vif;
63
64 struct list_head poll_list;
65 u32 tx_airtime_ac[4];
66
67 struct sk_buff_head psq;
68
69 struct ieee80211_tx_rate rates[4];
70
71 struct mt7603_rate_set rateset[2];
72 u32 rate_set_tsf;
73
74 u8 rate_count;
75 u8 n_rates;
76
77 u8 rate_probe;
78 u8 smps;
79
80 u8 ps;
81};
82
83struct mt7603_vif {
84 struct mt7603_sta sta;
85
86 u8 idx;
87};
88
89enum mt7603_reset_cause {
90 RESET_CAUSE_TX_HANG,
91 RESET_CAUSE_TX_BUSY,
92 RESET_CAUSE_RX_BUSY,
93 RESET_CAUSE_BEACON_STUCK,
94 RESET_CAUSE_RX_PSE_BUSY,
95 RESET_CAUSE_MCU_HANG,
96 RESET_CAUSE_RESET_FAILED,
97 __RESET_CAUSE_MAX
98};
99
100struct mt7603_dev {
101 struct mt76_dev mt76;
102
103 const struct mt76_bus_ops *bus_ops;
104
105 u32 rxfilter;
106
107 u8 vif_mask;
108
109 struct list_head sta_poll_list;
110 spinlock_t sta_poll_lock;
111
112 struct mt7603_sta global_sta;
113
114 u32 agc0, agc3;
115 u32 false_cca_ofdm, false_cca_cck;
116 unsigned long last_cca_adj;
117
118 __le32 rx_ampdu_ts;
119 u8 rssi_offset[3];
120
121 u8 slottime;
122 s16 coverage_class;
123
124 s8 tx_power_limit;
125
126 ktime_t ed_time;
127
128 spinlock_t ps_lock;
129
130 u8 mac_work_count;
131
132 u8 mcu_running;
133
134 u8 ed_monitor_enabled;
135 u8 ed_monitor;
136 s8 ed_trigger;
137 u8 ed_strict_mode;
138 u8 ed_strong_signal;
139
140 s8 sensitivity;
141
142 u8 beacon_check;
143 u8 tx_hang_check;
144 u8 tx_dma_check;
145 u8 rx_dma_check;
146 u8 rx_pse_check;
147 u8 mcu_hang;
148
149 enum mt7603_reset_cause cur_reset_cause;
150
151 u16 tx_dma_idx[4];
152 u16 rx_dma_idx;
153
154 u32 reset_test;
155
156 unsigned int reset_cause[__RESET_CAUSE_MAX];
157};
158
159extern const struct mt76_driver_ops mt7603_drv_ops;
160extern const struct ieee80211_ops mt7603_ops;
161extern struct pci_driver mt7603_pci_driver;
162extern struct platform_driver mt76_wmac_driver;
163
164static inline bool is_mt7603(struct mt7603_dev *dev)
165{
166 return mt76xx_chip(dev) == 0x7603;
167}
168
169static inline bool is_mt7628(struct mt7603_dev *dev)
170{
171 return mt76xx_chip(dev) == 0x7628;
172}
173
174
175#define MT_RATE_DRIVER_DATA_OFFSET 4
176
177u32 mt7603_reg_map(struct mt7603_dev *dev, u32 addr);
178
179irqreturn_t mt7603_irq_handler(int irq, void *dev_instance);
180
181int mt7603_register_device(struct mt7603_dev *dev);
182void mt7603_unregister_device(struct mt7603_dev *dev);
183int mt7603_eeprom_init(struct mt7603_dev *dev);
184int mt7603_dma_init(struct mt7603_dev *dev);
185void mt7603_dma_cleanup(struct mt7603_dev *dev);
186int mt7603_mcu_init(struct mt7603_dev *dev);
187void mt7603_init_debugfs(struct mt7603_dev *dev);
188
189static inline void mt7603_irq_enable(struct mt7603_dev *dev, u32 mask)
190{
191 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, 0, mask);
192}
193
194static inline void mt7603_irq_disable(struct mt7603_dev *dev, u32 mask)
195{
196 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
197}
198
199void mt7603_mac_reset_counters(struct mt7603_dev *dev);
200void mt7603_mac_dma_start(struct mt7603_dev *dev);
201void mt7603_mac_start(struct mt7603_dev *dev);
202void mt7603_mac_stop(struct mt7603_dev *dev);
203void mt7603_mac_work(struct work_struct *work);
204void mt7603_mac_set_timing(struct mt7603_dev *dev);
205void mt7603_beacon_set_timer(struct mt7603_dev *dev, int idx, int intval);
206int mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb);
207void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data);
208void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid);
209void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
210 int ba_size);
211void mt7603_mac_sta_poll(struct mt7603_dev *dev);
212
213void mt7603_pse_client_reset(struct mt7603_dev *dev);
214
215int mt7603_mcu_set_channel(struct mt7603_dev *dev);
216int mt7603_mcu_set_eeprom(struct mt7603_dev *dev);
217void mt7603_mcu_exit(struct mt7603_dev *dev);
218
219void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
220 const u8 *mac_addr);
221void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx);
222void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta);
223void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
224 struct ieee80211_tx_rate *probe_rate,
225 struct ieee80211_tx_rate *rates);
226int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
227 struct ieee80211_key_conf *key);
228void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
229 bool enabled);
230void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
231 bool enabled);
232void mt7603_filter_tx(struct mt7603_dev *dev, int idx, bool abort);
233
234int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
235 enum mt76_txq_id qid, struct mt76_wcid *wcid,
236 struct ieee80211_sta *sta,
237 struct mt76_tx_info *tx_info);
238
239void mt7603_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
240 struct mt76_queue_entry *e);
241
242void mt7603_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
243 struct sk_buff *skb);
244void mt7603_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
245void mt7603_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps);
246int mt7603_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
247 struct ieee80211_sta *sta);
248void mt7603_sta_assoc(struct mt76_dev *mdev, struct ieee80211_vif *vif,
249 struct ieee80211_sta *sta);
250void mt7603_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
251 struct ieee80211_sta *sta);
252
253void mt7603_pre_tbtt_tasklet(unsigned long arg);
254
255void mt7603_update_channel(struct mt76_dev *mdev);
256
257void mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val);
258void mt7603_cca_stats_reset(struct mt7603_dev *dev);
259
260void mt7603_init_edcca(struct mt7603_dev *dev);
261#endif
262
