1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#ifndef __RTL8723E_PWRSEQCMD_H__ 5#define __RTL8723E_PWRSEQCMD_H__ 6 7#include "wifi.h" 8/*--------------------------------------------- 9 * 3 The value of cmd: 4 bits 10 *--------------------------------------------- 11 */ 12#define PWR_CMD_READ 0x00 13#define PWR_CMD_WRITE 0x01 14#define PWR_CMD_POLLING 0x02 15#define PWR_CMD_DELAY 0x03 16#define PWR_CMD_END 0x04 17 18/* define the base address of each block */ 19#define PWR_BASEADDR_MAC 0x00 20#define PWR_BASEADDR_USB 0x01 21#define PWR_BASEADDR_PCIE 0x02 22#define PWR_BASEADDR_SDIO 0x03 23 24#define PWR_INTF_SDIO_MSK BIT(0) 25#define PWR_INTF_USB_MSK BIT(1) 26#define PWR_INTF_PCI_MSK BIT(2) 27#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 28 29#define PWR_FAB_TSMC_MSK BIT(0) 30#define PWR_FAB_UMC_MSK BIT(1) 31#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) 32 33#define PWR_CUT_TESTCHIP_MSK BIT(0) 34#define PWR_CUT_A_MSK BIT(1) 35#define PWR_CUT_B_MSK BIT(2) 36#define PWR_CUT_C_MSK BIT(3) 37#define PWR_CUT_D_MSK BIT(4) 38#define PWR_CUT_E_MSK BIT(5) 39#define PWR_CUT_F_MSK BIT(6) 40#define PWR_CUT_G_MSK BIT(7) 41#define PWR_CUT_ALL_MSK 0xFF 42 43enum pwrseq_delay_unit { 44 PWRSEQ_DELAY_US, 45 PWRSEQ_DELAY_MS, 46}; 47 48struct wlan_pwr_cfg { 49 u16 offset; 50 u8 cut_msk; 51 u8 fab_msk:4; 52 u8 interface_msk:4; 53 u8 base:4; 54 u8 cmd:4; 55 u8 msk; 56 u8 value; 57}; 58 59#define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset) 60#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk) 61#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk) 62#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk) 63#define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base) 64#define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd) 65#define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk) 66#define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value) 67 68bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, 69 u8 fab_version, u8 interface_type, 70 struct wlan_pwr_cfg pwrcfgcmd[]); 71 72#endif 73