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7#include <linux/clk.h>
8#include <linux/clk/tegra.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/mailbox_client.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/phy/phy.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h>
17#include <linux/reset.h>
18#include <linux/slab.h>
19
20#include <soc/tegra/fuse.h>
21
22#include "xusb.h"
23
24#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
26#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
27#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
28#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
29
30#define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
31#define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
32
33#define XUSB_PADCTL_USB2_PAD_MUX 0x004
34#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16
35#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
36#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
37#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18
38#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
39#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
40
41#define XUSB_PADCTL_USB2_PORT_CAP 0x008
42#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
47
48#define XUSB_PADCTL_SS_PORT_MAP 0x014
49#define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
50#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
51#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
52#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
53#define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
54
55#define XUSB_PADCTL_ELPG_PROGRAM1 0x024
56#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
57#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
58#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
59#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
60#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \
61 (1 << (1 + (x) * 3))
62#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
63
64#define XUSB_PADCTL_USB3_PAD_MUX 0x028
65#define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
66#define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
67
68#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
69#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)
70#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)
71
72#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
73#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
74#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
75#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
76#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
77
78#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
79#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
80#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
81#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
82#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
83#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
84
85#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
86#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26
87#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
88#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
89#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
90#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
91#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
92#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
93
94#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
95#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
96#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3
97#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
98#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
99#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
100#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
101#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
102
103#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
104#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
105#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19
106#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
107#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
108#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
109#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
110#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
111
112#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
113#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
114#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
115#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
116#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
117#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
118#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
119#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
120#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
121#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
122#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
123#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
124#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
125#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
126#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
127#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
128
129#define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
130#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
131#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
132
133#define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
134#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8
135#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
136#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
137#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
138
139#define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
140#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
141#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12
142#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
143#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
144#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5
145#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
146#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
147
148#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
149
150#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
151#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20
152#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
153#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
154#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
155#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16
156#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
157#define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
158#define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
159#define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
160#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
161#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
162#define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
163
164#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
165#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4
166#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
167#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
168#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
169#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
170#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
171
172#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
173#define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)
174#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
175#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12
176#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
177#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
178#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
179#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
180#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4
181#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
182
183#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
184#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16
185#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
186#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
187
188#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
189#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
190#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
191#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
192#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
193
194#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
195#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20
196#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
197#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
198#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
199#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
200
201#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
202
203#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
204
205#define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
206
207#define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
208
209#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
210
211#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
212
213#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
214#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
215#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
216#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
217
218#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
219#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
220#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
221#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
222
223#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
224#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
225
226#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
227#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16
228#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
229#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
230
231#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
232#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
233
234#define XUSB_PADCTL_USB2_VBUS_ID 0xc60
235#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)
236#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18
237#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
238#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
239
240struct tegra210_xusb_fuse_calibration {
241 u32 hs_curr_level[4];
242 u32 hs_term_range_adj;
243 u32 rpd_ctrl;
244};
245
246struct tegra210_xusb_padctl {
247 struct tegra_xusb_padctl base;
248
249 struct tegra210_xusb_fuse_calibration fuse;
250};
251
252static inline struct tegra210_xusb_padctl *
253to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
254{
255 return container_of(padctl, struct tegra210_xusb_padctl, base);
256}
257
258
259static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
260{
261 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
262 unsigned long timeout;
263 u32 value;
264 int err;
265
266 if (pcie->enable > 0) {
267 pcie->enable++;
268 return 0;
269 }
270
271 err = clk_prepare_enable(pcie->pll);
272 if (err < 0)
273 return err;
274
275 err = reset_control_deassert(pcie->rst);
276 if (err < 0)
277 goto disable;
278
279 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
280 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
281 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
282 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
283 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
284 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
285
286 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
287 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
288 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
289 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
290 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
291 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
292
293 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
294 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
295 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
296
297 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
298 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
299 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
300
301 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
302 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
303 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
304
305 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
306 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
307 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
308 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
309 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
310 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
311 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
312 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
313 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
314
315 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
316 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
317 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
318 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
319 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
320 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
321 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
322 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
323
324 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
325 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
326 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
327
328 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
329 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
330 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
331 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
332
333 usleep_range(10, 20);
334
335 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
336 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
337 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
338
339 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
340 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
341 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
342
343 timeout = jiffies + msecs_to_jiffies(100);
344
345 while (time_before(jiffies, timeout)) {
346 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
347 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
348 break;
349
350 usleep_range(10, 20);
351 }
352
353 if (time_after_eq(jiffies, timeout)) {
354 err = -ETIMEDOUT;
355 goto reset;
356 }
357
358 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
359 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
360 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
361
362 timeout = jiffies + msecs_to_jiffies(100);
363
364 while (time_before(jiffies, timeout)) {
365 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
366 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
367 break;
368
369 usleep_range(10, 20);
370 }
371
372 if (time_after_eq(jiffies, timeout)) {
373 err = -ETIMEDOUT;
374 goto reset;
375 }
376
377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
378 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
379 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
380
381 timeout = jiffies + msecs_to_jiffies(100);
382
383 while (time_before(jiffies, timeout)) {
384 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
385 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
386 break;
387
388 usleep_range(10, 20);
389 }
390
391 if (time_after_eq(jiffies, timeout)) {
392 err = -ETIMEDOUT;
393 goto reset;
394 }
395
396 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
397 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
398 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
399 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
400
401 timeout = jiffies + msecs_to_jiffies(100);
402
403 while (time_before(jiffies, timeout)) {
404 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
405 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
406 break;
407
408 usleep_range(10, 20);
409 }
410
411 if (time_after_eq(jiffies, timeout)) {
412 err = -ETIMEDOUT;
413 goto reset;
414 }
415
416 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
417 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
418 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
419
420 timeout = jiffies + msecs_to_jiffies(100);
421
422 while (time_before(jiffies, timeout)) {
423 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
424 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
425 break;
426
427 usleep_range(10, 20);
428 }
429
430 if (time_after_eq(jiffies, timeout)) {
431 err = -ETIMEDOUT;
432 goto reset;
433 }
434
435 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
436 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
437 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
438
439 tegra210_xusb_pll_hw_control_enable();
440
441 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
442 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
443 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
444
445 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
446 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
447 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
448
449 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
450 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
451 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
452
453 usleep_range(10, 20);
454
455 tegra210_xusb_pll_hw_sequence_start();
456
457 pcie->enable++;
458
459 return 0;
460
461reset:
462 reset_control_assert(pcie->rst);
463disable:
464 clk_disable_unprepare(pcie->pll);
465 return err;
466}
467
468static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
469{
470 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
471
472 mutex_lock(&padctl->lock);
473
474 if (WARN_ON(pcie->enable == 0))
475 goto unlock;
476
477 if (--pcie->enable > 0)
478 goto unlock;
479
480 reset_control_assert(pcie->rst);
481 clk_disable_unprepare(pcie->pll);
482
483unlock:
484 mutex_unlock(&padctl->lock);
485}
486
487
488static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
489{
490 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
491 unsigned long timeout;
492 u32 value;
493 int err;
494
495 if (sata->enable > 0) {
496 sata->enable++;
497 return 0;
498 }
499
500 err = clk_prepare_enable(sata->pll);
501 if (err < 0)
502 return err;
503
504 err = reset_control_deassert(sata->rst);
505 if (err < 0)
506 goto disable;
507
508 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
509 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
510 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
511 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
512 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
513 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
514
515 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
516 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
517 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
518 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
519 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
520 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
521
522 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
523 value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
524 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
525
526 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
527 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
528 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
529
530 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
531 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
532 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
533
534 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
535 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
536 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
537 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
538 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
539 value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
540
541 if (usb)
542 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
543 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
544 else
545 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<
546 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
547
548 value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN;
549 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
550
551 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
552 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
553 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
554 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
555 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
556
557 if (usb)
558 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
559 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
560 else
561 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<
562 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
563
564 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
565
566 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
567 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
568 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
569
570 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
571 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
572 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
573 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
574
575 usleep_range(10, 20);
576
577 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
578 value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
579 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
580
581 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
582 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
583 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
584
585 timeout = jiffies + msecs_to_jiffies(100);
586
587 while (time_before(jiffies, timeout)) {
588 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
589 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
590 break;
591
592 usleep_range(10, 20);
593 }
594
595 if (time_after_eq(jiffies, timeout)) {
596 err = -ETIMEDOUT;
597 goto reset;
598 }
599
600 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
601 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
602 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
603
604 timeout = jiffies + msecs_to_jiffies(100);
605
606 while (time_before(jiffies, timeout)) {
607 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
608 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
609 break;
610
611 usleep_range(10, 20);
612 }
613
614 if (time_after_eq(jiffies, timeout)) {
615 err = -ETIMEDOUT;
616 goto reset;
617 }
618
619 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
620 value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
621 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
622
623 timeout = jiffies + msecs_to_jiffies(100);
624
625 while (time_before(jiffies, timeout)) {
626 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
627 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
628 break;
629
630 usleep_range(10, 20);
631 }
632
633 if (time_after_eq(jiffies, timeout)) {
634 err = -ETIMEDOUT;
635 goto reset;
636 }
637
638 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
639 value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
640 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
641 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
642
643 timeout = jiffies + msecs_to_jiffies(100);
644
645 while (time_before(jiffies, timeout)) {
646 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
647 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
648 break;
649
650 usleep_range(10, 20);
651 }
652
653 if (time_after_eq(jiffies, timeout)) {
654 err = -ETIMEDOUT;
655 goto reset;
656 }
657
658 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
659 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
660 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
661
662 timeout = jiffies + msecs_to_jiffies(100);
663
664 while (time_before(jiffies, timeout)) {
665 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
666 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
667 break;
668
669 usleep_range(10, 20);
670 }
671
672 if (time_after_eq(jiffies, timeout)) {
673 err = -ETIMEDOUT;
674 goto reset;
675 }
676
677 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
678 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
679 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
680
681 tegra210_sata_pll_hw_control_enable();
682
683 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
684 value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
685 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
686
687 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
688 value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
689 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
690
691 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
692 value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
693 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
694
695 usleep_range(10, 20);
696
697 tegra210_sata_pll_hw_sequence_start();
698
699 sata->enable++;
700
701 return 0;
702
703reset:
704 reset_control_assert(sata->rst);
705disable:
706 clk_disable_unprepare(sata->pll);
707 return err;
708}
709
710static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
711{
712 struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
713
714 mutex_lock(&padctl->lock);
715
716 if (WARN_ON(sata->enable == 0))
717 goto unlock;
718
719 if (--sata->enable > 0)
720 goto unlock;
721
722 reset_control_assert(sata->rst);
723 clk_disable_unprepare(sata->pll);
724
725unlock:
726 mutex_unlock(&padctl->lock);
727}
728
729static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
730{
731 u32 value;
732
733 mutex_lock(&padctl->lock);
734
735 if (padctl->enable++ > 0)
736 goto out;
737
738 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
739 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
740 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
741
742 usleep_range(100, 200);
743
744 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
745 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
746 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
747
748 usleep_range(100, 200);
749
750 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
751 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
752 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
753
754out:
755 mutex_unlock(&padctl->lock);
756 return 0;
757}
758
759static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
760{
761 u32 value;
762
763 mutex_lock(&padctl->lock);
764
765 if (WARN_ON(padctl->enable == 0))
766 goto out;
767
768 if (--padctl->enable > 0)
769 goto out;
770
771 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
772 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
773 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
774
775 usleep_range(100, 200);
776
777 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
778 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
779 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
780
781 usleep_range(100, 200);
782
783 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
784 value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
785 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
786
787out:
788 mutex_unlock(&padctl->lock);
789 return 0;
790}
791
792static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
793 unsigned int index, bool idle)
794{
795 u32 value;
796
797 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
798
799 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
800 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
801 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE);
802
803 if (idle)
804 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
805 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
806 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE;
807 else
808 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
809 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
810 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE);
811
812 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
813
814 return 0;
815}
816
817static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
818 unsigned int index, bool enable)
819{
820 struct tegra_xusb_port *port;
821 struct tegra_xusb_lane *lane;
822 u32 value, offset;
823
824 port = tegra_xusb_find_port(padctl, "usb3", index);
825 if (!port)
826 return -ENODEV;
827
828 lane = port->lane;
829
830 if (lane->pad == padctl->pcie)
831 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);
832 else
833 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;
834
835 value = padctl_readl(padctl, offset);
836
837 value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<
838 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
839 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
840 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD);
841
842 if (!enable) {
843 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<
844 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
845 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
846 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD;
847 }
848
849 padctl_writel(padctl, value, offset);
850
851 return 0;
852}
853
854#define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \
855 { \
856 .name = _name, \
857 .offset = _offset, \
858 .shift = _shift, \
859 .mask = _mask, \
860 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \
861 .funcs = tegra210_##_type##_functions, \
862 }
863
864static const char *tegra210_usb2_functions[] = {
865 "snps",
866 "xusb",
867 "uart"
868};
869
870static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = {
871 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2),
872 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2),
873 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2),
874 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2),
875};
876
877static struct tegra_xusb_lane *
878tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
879 unsigned int index)
880{
881 struct tegra_xusb_usb2_lane *usb2;
882 int err;
883
884 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
885 if (!usb2)
886 return ERR_PTR(-ENOMEM);
887
888 INIT_LIST_HEAD(&usb2->base.list);
889 usb2->base.soc = &pad->soc->lanes[index];
890 usb2->base.index = index;
891 usb2->base.pad = pad;
892 usb2->base.np = np;
893
894 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
895 if (err < 0) {
896 kfree(usb2);
897 return ERR_PTR(err);
898 }
899
900 return &usb2->base;
901}
902
903static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane)
904{
905 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
906
907 kfree(usb2);
908}
909
910static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = {
911 .probe = tegra210_usb2_lane_probe,
912 .remove = tegra210_usb2_lane_remove,
913};
914
915static int tegra210_usb2_phy_init(struct phy *phy)
916{
917 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
918 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
919 u32 value;
920
921 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
922 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
923 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);
924 value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<
925 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
926 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
927
928 return tegra210_xusb_padctl_enable(padctl);
929}
930
931static int tegra210_usb2_phy_exit(struct phy *phy)
932{
933 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
934
935 return tegra210_xusb_padctl_disable(lane->pad->padctl);
936}
937
938static int tegra210_usb2_phy_power_on(struct phy *phy)
939{
940 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
941 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
942 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
943 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
944 struct tegra210_xusb_padctl *priv;
945 struct tegra_xusb_usb2_port *port;
946 unsigned int index = lane->index;
947 u32 value;
948 int err;
949
950 port = tegra_xusb_find_usb2_port(padctl, index);
951 if (!port) {
952 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
953 return -ENODEV;
954 }
955
956 priv = to_tegra210_xusb_padctl(padctl);
957
958 if (port->usb3_port_fake != -1) {
959 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
960 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
961 port->usb3_port_fake);
962 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
963 port->usb3_port_fake, index);
964 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
965
966 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
967 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
968 port->usb3_port_fake);
969 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
970
971 usleep_range(100, 200);
972
973 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
974 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
975 port->usb3_port_fake);
976 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
977
978 usleep_range(100, 200);
979
980 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
981 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
982 port->usb3_port_fake);
983 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
984 }
985
986 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
987 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
988 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
989 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<
990 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));
991 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
992 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);
993
994 if (tegra_sku_info.revision < TEGRA_REVISION_A02)
995 value |=
996 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL <<
997 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT);
998
999 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1000
1001 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1002 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
1003 if (port->mode == USB_DR_MODE_UNKNOWN)
1004 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
1005 else if (port->mode == USB_DR_MODE_PERIPHERAL)
1006 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
1007 else if (port->mode == USB_DR_MODE_HOST)
1008 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
1009 else if (port->mode == USB_DR_MODE_OTG)
1010 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
1011 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
1012
1013 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1014 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
1015 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |
1016 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
1017 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
1018 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
1019 value |= (priv->fuse.hs_curr_level[index] +
1020 usb2->hs_curr_level_offset) <<
1021 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
1022 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1023
1024 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1025 value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
1026 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
1027 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK <<
1028 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) |
1029 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
1030 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD |
1031 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD);
1032 value |= (priv->fuse.hs_term_range_adj <<
1033 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
1034 (priv->fuse.rpd_ctrl <<
1035 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT);
1036 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1037
1038 value = padctl_readl(padctl,
1039 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1040 value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
1041 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);
1042 if (port->mode == USB_DR_MODE_HOST)
1043 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
1044 else
1045 value |=
1046 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL <<
1047 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT;
1048 padctl_writel(padctl, value,
1049 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1050
1051 err = regulator_enable(port->supply);
1052 if (err)
1053 return err;
1054
1055 mutex_lock(&padctl->lock);
1056
1057 if (pad->enable > 0) {
1058 pad->enable++;
1059 mutex_unlock(&padctl->lock);
1060 return 0;
1061 }
1062
1063 err = clk_prepare_enable(pad->clk);
1064 if (err)
1065 goto disable_regulator;
1066
1067 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1068 value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
1069 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1070 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
1071 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
1072 value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
1073 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1074 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
1075 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
1076 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1077
1078 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1079 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1080 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1081
1082 udelay(1);
1083
1084 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1085 value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
1086 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1087
1088 udelay(50);
1089
1090 clk_disable_unprepare(pad->clk);
1091
1092 pad->enable++;
1093 mutex_unlock(&padctl->lock);
1094
1095 return 0;
1096
1097disable_regulator:
1098 regulator_disable(port->supply);
1099 mutex_unlock(&padctl->lock);
1100 return err;
1101}
1102
1103static int tegra210_usb2_phy_power_off(struct phy *phy)
1104{
1105 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1106 struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
1107 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1108 struct tegra_xusb_usb2_port *port;
1109 u32 value;
1110
1111 port = tegra_xusb_find_usb2_port(padctl, lane->index);
1112 if (!port) {
1113 dev_err(&phy->dev, "no port found for USB2 lane %u\n",
1114 lane->index);
1115 return -ENODEV;
1116 }
1117
1118 mutex_lock(&padctl->lock);
1119
1120 if (port->usb3_port_fake != -1) {
1121 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1122 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1123 port->usb3_port_fake);
1124 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1125
1126 usleep_range(100, 200);
1127
1128 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1129 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1130 port->usb3_port_fake);
1131 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1132
1133 usleep_range(250, 350);
1134
1135 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1136 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1137 port->usb3_port_fake);
1138 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1139
1140 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1141 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
1142 XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED);
1143 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1144 }
1145
1146 if (WARN_ON(pad->enable == 0))
1147 goto out;
1148
1149 if (--pad->enable > 0)
1150 goto out;
1151
1152 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1153 value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1154 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1155
1156out:
1157 regulator_disable(port->supply);
1158 mutex_unlock(&padctl->lock);
1159 return 0;
1160}
1161
1162static const struct phy_ops tegra210_usb2_phy_ops = {
1163 .init = tegra210_usb2_phy_init,
1164 .exit = tegra210_usb2_phy_exit,
1165 .power_on = tegra210_usb2_phy_power_on,
1166 .power_off = tegra210_usb2_phy_power_off,
1167 .owner = THIS_MODULE,
1168};
1169
1170static struct tegra_xusb_pad *
1171tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1172 const struct tegra_xusb_pad_soc *soc,
1173 struct device_node *np)
1174{
1175 struct tegra_xusb_usb2_pad *usb2;
1176 struct tegra_xusb_pad *pad;
1177 int err;
1178
1179 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1180 if (!usb2)
1181 return ERR_PTR(-ENOMEM);
1182
1183 pad = &usb2->base;
1184 pad->ops = &tegra210_usb2_lane_ops;
1185 pad->soc = soc;
1186
1187 err = tegra_xusb_pad_init(pad, padctl, np);
1188 if (err < 0) {
1189 kfree(usb2);
1190 goto out;
1191 }
1192
1193 usb2->clk = devm_clk_get(&pad->dev, "trk");
1194 if (IS_ERR(usb2->clk)) {
1195 err = PTR_ERR(usb2->clk);
1196 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1197 goto unregister;
1198 }
1199
1200 err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops);
1201 if (err < 0)
1202 goto unregister;
1203
1204 dev_set_drvdata(&pad->dev, pad);
1205
1206 return pad;
1207
1208unregister:
1209 device_unregister(&pad->dev);
1210out:
1211 return ERR_PTR(err);
1212}
1213
1214static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad)
1215{
1216 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1217
1218 kfree(usb2);
1219}
1220
1221static const struct tegra_xusb_pad_ops tegra210_usb2_ops = {
1222 .probe = tegra210_usb2_pad_probe,
1223 .remove = tegra210_usb2_pad_remove,
1224};
1225
1226static const struct tegra_xusb_pad_soc tegra210_usb2_pad = {
1227 .name = "usb2",
1228 .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes),
1229 .lanes = tegra210_usb2_lanes,
1230 .ops = &tegra210_usb2_ops,
1231};
1232
1233static const char *tegra210_hsic_functions[] = {
1234 "snps",
1235 "xusb",
1236};
1237
1238static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = {
1239 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1240};
1241
1242static struct tegra_xusb_lane *
1243tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1244 unsigned int index)
1245{
1246 struct tegra_xusb_hsic_lane *hsic;
1247 int err;
1248
1249 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1250 if (!hsic)
1251 return ERR_PTR(-ENOMEM);
1252
1253 INIT_LIST_HEAD(&hsic->base.list);
1254 hsic->base.soc = &pad->soc->lanes[index];
1255 hsic->base.index = index;
1256 hsic->base.pad = pad;
1257 hsic->base.np = np;
1258
1259 err = tegra_xusb_lane_parse_dt(&hsic->base, np);
1260 if (err < 0) {
1261 kfree(hsic);
1262 return ERR_PTR(err);
1263 }
1264
1265 return &hsic->base;
1266}
1267
1268static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane)
1269{
1270 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1271
1272 kfree(hsic);
1273}
1274
1275static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = {
1276 .probe = tegra210_hsic_lane_probe,
1277 .remove = tegra210_hsic_lane_remove,
1278};
1279
1280static int tegra210_hsic_phy_init(struct phy *phy)
1281{
1282 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1283 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1284 u32 value;
1285
1286 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1287 value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<
1288 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT);
1289 value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<
1290 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;
1291 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1292
1293 return tegra210_xusb_padctl_enable(padctl);
1294}
1295
1296static int tegra210_hsic_phy_exit(struct phy *phy)
1297{
1298 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1299
1300 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1301}
1302
1303static int tegra210_hsic_phy_power_on(struct phy *phy)
1304{
1305 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1306 struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1307 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1308 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1309 unsigned int index = lane->index;
1310 u32 value;
1311 int err;
1312
1313 err = regulator_enable(pad->supply);
1314 if (err)
1315 return err;
1316
1317 padctl_writel(padctl, hsic->strobe_trim,
1318 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);
1319
1320 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1321 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<
1322 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1323 value |= (hsic->tx_rtune_p <<
1324 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1325 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1326
1327 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1328 value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
1329 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1330 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<
1331 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));
1332 value |= (hsic->rx_strobe_trim <<
1333 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1334 (hsic->rx_data_trim <<
1335 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);
1336 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1337
1338 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1339 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
1340 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
1341 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE |
1342 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1343 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1344 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1345 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1346 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1347 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1348 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1349 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1350 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE);
1351 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1352 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
1353 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE;
1354 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1355
1356 err = clk_prepare_enable(pad->clk);
1357 if (err)
1358 goto disable;
1359
1360 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1361 value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<
1362 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1363 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK <<
1364 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT));
1365 value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<
1366 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1367 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL <<
1368 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT);
1369 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1370
1371 udelay(1);
1372
1373 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1374 value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;
1375 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1376
1377 udelay(50);
1378
1379 clk_disable_unprepare(pad->clk);
1380
1381 return 0;
1382
1383disable:
1384 regulator_disable(pad->supply);
1385 return err;
1386}
1387
1388static int tegra210_hsic_phy_power_off(struct phy *phy)
1389{
1390 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1391 struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1392 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1393 unsigned int index = lane->index;
1394 u32 value;
1395
1396 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1397 value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1398 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1399 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1400 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1401 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1402 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1403 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1404 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1405 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE;
1406 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1407
1408 regulator_disable(pad->supply);
1409
1410 return 0;
1411}
1412
1413static const struct phy_ops tegra210_hsic_phy_ops = {
1414 .init = tegra210_hsic_phy_init,
1415 .exit = tegra210_hsic_phy_exit,
1416 .power_on = tegra210_hsic_phy_power_on,
1417 .power_off = tegra210_hsic_phy_power_off,
1418 .owner = THIS_MODULE,
1419};
1420
1421static struct tegra_xusb_pad *
1422tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
1423 const struct tegra_xusb_pad_soc *soc,
1424 struct device_node *np)
1425{
1426 struct tegra_xusb_hsic_pad *hsic;
1427 struct tegra_xusb_pad *pad;
1428 int err;
1429
1430 hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1431 if (!hsic)
1432 return ERR_PTR(-ENOMEM);
1433
1434 pad = &hsic->base;
1435 pad->ops = &tegra210_hsic_lane_ops;
1436 pad->soc = soc;
1437
1438 err = tegra_xusb_pad_init(pad, padctl, np);
1439 if (err < 0) {
1440 kfree(hsic);
1441 goto out;
1442 }
1443
1444 hsic->clk = devm_clk_get(&pad->dev, "trk");
1445 if (IS_ERR(hsic->clk)) {
1446 err = PTR_ERR(hsic->clk);
1447 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1448 goto unregister;
1449 }
1450
1451 err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops);
1452 if (err < 0)
1453 goto unregister;
1454
1455 dev_set_drvdata(&pad->dev, pad);
1456
1457 return pad;
1458
1459unregister:
1460 device_unregister(&pad->dev);
1461out:
1462 return ERR_PTR(err);
1463}
1464
1465static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad)
1466{
1467 struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);
1468
1469 kfree(hsic);
1470}
1471
1472static const struct tegra_xusb_pad_ops tegra210_hsic_ops = {
1473 .probe = tegra210_hsic_pad_probe,
1474 .remove = tegra210_hsic_pad_remove,
1475};
1476
1477static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
1478 .name = "hsic",
1479 .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes),
1480 .lanes = tegra210_hsic_lanes,
1481 .ops = &tegra210_hsic_ops,
1482};
1483
1484static const char *tegra210_pcie_functions[] = {
1485 "pcie-x1",
1486 "usb3-ss",
1487 "sata",
1488 "pcie-x4",
1489};
1490
1491static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
1492 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1493 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1494 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1495 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1496 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1497 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1498 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1499};
1500
1501static struct tegra_xusb_lane *
1502tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1503 unsigned int index)
1504{
1505 struct tegra_xusb_pcie_lane *pcie;
1506 int err;
1507
1508 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1509 if (!pcie)
1510 return ERR_PTR(-ENOMEM);
1511
1512 INIT_LIST_HEAD(&pcie->base.list);
1513 pcie->base.soc = &pad->soc->lanes[index];
1514 pcie->base.index = index;
1515 pcie->base.pad = pad;
1516 pcie->base.np = np;
1517
1518 err = tegra_xusb_lane_parse_dt(&pcie->base, np);
1519 if (err < 0) {
1520 kfree(pcie);
1521 return ERR_PTR(err);
1522 }
1523
1524 return &pcie->base;
1525}
1526
1527static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
1528{
1529 struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
1530
1531 kfree(pcie);
1532}
1533
1534static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
1535 .probe = tegra210_pcie_lane_probe,
1536 .remove = tegra210_pcie_lane_remove,
1537};
1538
1539static int tegra210_pcie_phy_init(struct phy *phy)
1540{
1541 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1542
1543 return tegra210_xusb_padctl_enable(lane->pad->padctl);
1544}
1545
1546static int tegra210_pcie_phy_exit(struct phy *phy)
1547{
1548 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1549
1550 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1551}
1552
1553static int tegra210_pcie_phy_power_on(struct phy *phy)
1554{
1555 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1556 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1557 u32 value;
1558 int err;
1559
1560 mutex_lock(&padctl->lock);
1561
1562 err = tegra210_pex_uphy_enable(padctl);
1563 if (err < 0)
1564 goto unlock;
1565
1566 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1567 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1568 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1569
1570unlock:
1571 mutex_unlock(&padctl->lock);
1572 return err;
1573}
1574
1575static int tegra210_pcie_phy_power_off(struct phy *phy)
1576{
1577 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1578 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1579 u32 value;
1580
1581 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1582 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1583 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1584
1585 tegra210_pex_uphy_disable(padctl);
1586
1587 return 0;
1588}
1589
1590static const struct phy_ops tegra210_pcie_phy_ops = {
1591 .init = tegra210_pcie_phy_init,
1592 .exit = tegra210_pcie_phy_exit,
1593 .power_on = tegra210_pcie_phy_power_on,
1594 .power_off = tegra210_pcie_phy_power_off,
1595 .owner = THIS_MODULE,
1596};
1597
1598static struct tegra_xusb_pad *
1599tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
1600 const struct tegra_xusb_pad_soc *soc,
1601 struct device_node *np)
1602{
1603 struct tegra_xusb_pcie_pad *pcie;
1604 struct tegra_xusb_pad *pad;
1605 int err;
1606
1607 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1608 if (!pcie)
1609 return ERR_PTR(-ENOMEM);
1610
1611 pad = &pcie->base;
1612 pad->ops = &tegra210_pcie_lane_ops;
1613 pad->soc = soc;
1614
1615 err = tegra_xusb_pad_init(pad, padctl, np);
1616 if (err < 0) {
1617 kfree(pcie);
1618 goto out;
1619 }
1620
1621 pcie->pll = devm_clk_get(&pad->dev, "pll");
1622 if (IS_ERR(pcie->pll)) {
1623 err = PTR_ERR(pcie->pll);
1624 dev_err(&pad->dev, "failed to get PLL: %d\n", err);
1625 goto unregister;
1626 }
1627
1628 pcie->rst = devm_reset_control_get(&pad->dev, "phy");
1629 if (IS_ERR(pcie->rst)) {
1630 err = PTR_ERR(pcie->rst);
1631 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err);
1632 goto unregister;
1633 }
1634
1635 err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops);
1636 if (err < 0)
1637 goto unregister;
1638
1639 dev_set_drvdata(&pad->dev, pad);
1640
1641 return pad;
1642
1643unregister:
1644 device_unregister(&pad->dev);
1645out:
1646 return ERR_PTR(err);
1647}
1648
1649static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad)
1650{
1651 struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
1652
1653 kfree(pcie);
1654}
1655
1656static const struct tegra_xusb_pad_ops tegra210_pcie_ops = {
1657 .probe = tegra210_pcie_pad_probe,
1658 .remove = tegra210_pcie_pad_remove,
1659};
1660
1661static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {
1662 .name = "pcie",
1663 .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes),
1664 .lanes = tegra210_pcie_lanes,
1665 .ops = &tegra210_pcie_ops,
1666};
1667
1668static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {
1669 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1670};
1671
1672static struct tegra_xusb_lane *
1673tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1674 unsigned int index)
1675{
1676 struct tegra_xusb_sata_lane *sata;
1677 int err;
1678
1679 sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1680 if (!sata)
1681 return ERR_PTR(-ENOMEM);
1682
1683 INIT_LIST_HEAD(&sata->base.list);
1684 sata->base.soc = &pad->soc->lanes[index];
1685 sata->base.index = index;
1686 sata->base.pad = pad;
1687 sata->base.np = np;
1688
1689 err = tegra_xusb_lane_parse_dt(&sata->base, np);
1690 if (err < 0) {
1691 kfree(sata);
1692 return ERR_PTR(err);
1693 }
1694
1695 return &sata->base;
1696}
1697
1698static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
1699{
1700 struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);
1701
1702 kfree(sata);
1703}
1704
1705static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
1706 .probe = tegra210_sata_lane_probe,
1707 .remove = tegra210_sata_lane_remove,
1708};
1709
1710static int tegra210_sata_phy_init(struct phy *phy)
1711{
1712 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1713
1714 return tegra210_xusb_padctl_enable(lane->pad->padctl);
1715}
1716
1717static int tegra210_sata_phy_exit(struct phy *phy)
1718{
1719 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1720
1721 return tegra210_xusb_padctl_disable(lane->pad->padctl);
1722}
1723
1724static int tegra210_sata_phy_power_on(struct phy *phy)
1725{
1726 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1727 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1728 u32 value;
1729 int err;
1730
1731 mutex_lock(&padctl->lock);
1732
1733 err = tegra210_sata_uphy_enable(padctl, false);
1734 if (err < 0)
1735 goto unlock;
1736
1737 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1738 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1739 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1740
1741unlock:
1742 mutex_unlock(&padctl->lock);
1743 return err;
1744}
1745
1746static int tegra210_sata_phy_power_off(struct phy *phy)
1747{
1748 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1749 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1750 u32 value;
1751
1752 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1753 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1754 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1755
1756 tegra210_sata_uphy_disable(lane->pad->padctl);
1757
1758 return 0;
1759}
1760
1761static const struct phy_ops tegra210_sata_phy_ops = {
1762 .init = tegra210_sata_phy_init,
1763 .exit = tegra210_sata_phy_exit,
1764 .power_on = tegra210_sata_phy_power_on,
1765 .power_off = tegra210_sata_phy_power_off,
1766 .owner = THIS_MODULE,
1767};
1768
1769static struct tegra_xusb_pad *
1770tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
1771 const struct tegra_xusb_pad_soc *soc,
1772 struct device_node *np)
1773{
1774 struct tegra_xusb_sata_pad *sata;
1775 struct tegra_xusb_pad *pad;
1776 int err;
1777
1778 sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1779 if (!sata)
1780 return ERR_PTR(-ENOMEM);
1781
1782 pad = &sata->base;
1783 pad->ops = &tegra210_sata_lane_ops;
1784 pad->soc = soc;
1785
1786 err = tegra_xusb_pad_init(pad, padctl, np);
1787 if (err < 0) {
1788 kfree(sata);
1789 goto out;
1790 }
1791
1792 sata->rst = devm_reset_control_get(&pad->dev, "phy");
1793 if (IS_ERR(sata->rst)) {
1794 err = PTR_ERR(sata->rst);
1795 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err);
1796 goto unregister;
1797 }
1798
1799 err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops);
1800 if (err < 0)
1801 goto unregister;
1802
1803 dev_set_drvdata(&pad->dev, pad);
1804
1805 return pad;
1806
1807unregister:
1808 device_unregister(&pad->dev);
1809out:
1810 return ERR_PTR(err);
1811}
1812
1813static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad)
1814{
1815 struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);
1816
1817 kfree(sata);
1818}
1819
1820static const struct tegra_xusb_pad_ops tegra210_sata_ops = {
1821 .probe = tegra210_sata_pad_probe,
1822 .remove = tegra210_sata_pad_remove,
1823};
1824
1825static const struct tegra_xusb_pad_soc tegra210_sata_pad = {
1826 .name = "sata",
1827 .num_lanes = ARRAY_SIZE(tegra210_sata_lanes),
1828 .lanes = tegra210_sata_lanes,
1829 .ops = &tegra210_sata_ops,
1830};
1831
1832static const struct tegra_xusb_pad_soc * const tegra210_pads[] = {
1833 &tegra210_usb2_pad,
1834 &tegra210_hsic_pad,
1835 &tegra210_pcie_pad,
1836 &tegra210_sata_pad,
1837};
1838
1839static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)
1840{
1841 return 0;
1842}
1843
1844static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)
1845{
1846}
1847
1848static struct tegra_xusb_lane *
1849tegra210_usb2_port_map(struct tegra_xusb_port *port)
1850{
1851 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1852}
1853
1854static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = {
1855 .enable = tegra210_usb2_port_enable,
1856 .disable = tegra210_usb2_port_disable,
1857 .map = tegra210_usb2_port_map,
1858};
1859
1860static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)
1861{
1862 return 0;
1863}
1864
1865static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)
1866{
1867}
1868
1869static struct tegra_xusb_lane *
1870tegra210_hsic_port_map(struct tegra_xusb_port *port)
1871{
1872 return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
1873}
1874
1875static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {
1876 .enable = tegra210_hsic_port_enable,
1877 .disable = tegra210_hsic_port_disable,
1878 .map = tegra210_hsic_port_map,
1879};
1880
1881static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
1882{
1883 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
1884 struct tegra_xusb_padctl *padctl = port->padctl;
1885 struct tegra_xusb_lane *lane = usb3->base.lane;
1886 unsigned int index = port->index;
1887 u32 value;
1888 int err;
1889
1890 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1891
1892 if (!usb3->internal)
1893 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1894 else
1895 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1896
1897 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
1898 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
1899 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1900
1901
1902
1903
1904
1905
1906 err = regulator_enable(usb3->supply);
1907 if (err < 0)
1908 return err;
1909
1910 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
1911 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
1912 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
1913 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
1914 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
1915 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
1916
1917 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
1918 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
1919 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
1920 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
1921 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
1922 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
1923
1924 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
1925 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
1926
1927 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
1928 value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
1929 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
1930 value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
1931 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
1932 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
1933
1934 padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
1935 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
1936
1937 if (lane->pad == padctl->sata)
1938 err = tegra210_sata_uphy_enable(padctl, true);
1939 else
1940 err = tegra210_pex_uphy_enable(padctl);
1941
1942 if (err) {
1943 dev_err(&port->dev, "%s: failed to enable UPHY: %d\n",
1944 __func__, err);
1945 return err;
1946 }
1947
1948 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1949 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
1950 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1951
1952 usleep_range(100, 200);
1953
1954 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1955 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
1956 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1957
1958 usleep_range(100, 200);
1959
1960 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1961 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
1962 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1963
1964 return 0;
1965}
1966
1967static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
1968{
1969 struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
1970 struct tegra_xusb_padctl *padctl = port->padctl;
1971 struct tegra_xusb_lane *lane = port->lane;
1972 unsigned int index = port->index;
1973 u32 value;
1974
1975 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1976 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
1977 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1978
1979 usleep_range(100, 200);
1980
1981 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1982 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
1983 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1984
1985 usleep_range(250, 350);
1986
1987 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1988 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
1989 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1990
1991 if (lane->pad == padctl->sata)
1992 tegra210_sata_uphy_disable(padctl);
1993 else
1994 tegra210_pex_uphy_disable(padctl);
1995
1996 regulator_disable(usb3->supply);
1997
1998 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1999 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2000 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);
2001 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2002}
2003
2004static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
2005 { 0, "pcie", 6 },
2006 { 1, "pcie", 5 },
2007 { 2, "pcie", 0 },
2008 { 2, "pcie", 3 },
2009 { 3, "pcie", 4 },
2010 { 3, "pcie", 4 },
2011 { 0, NULL, 0 }
2012};
2013
2014static struct tegra_xusb_lane *
2015tegra210_usb3_port_map(struct tegra_xusb_port *port)
2016{
2017 return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");
2018}
2019
2020static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
2021 .enable = tegra210_usb3_port_enable,
2022 .disable = tegra210_usb3_port_disable,
2023 .map = tegra210_usb3_port_map,
2024};
2025
2026static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
2027 bool status)
2028{
2029 u32 value;
2030
2031 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
2032
2033 value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
2034
2035 if (status) {
2036 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
2037 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
2038 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
2039 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
2040 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
2041 } else {
2042 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
2043 }
2044
2045 padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
2046
2047 return 0;
2048}
2049
2050static int tegra210_utmi_port_reset(struct phy *phy)
2051{
2052 struct tegra_xusb_padctl *padctl;
2053 struct tegra_xusb_lane *lane;
2054 u32 value;
2055
2056 lane = phy_get_drvdata(phy);
2057 padctl = lane->pad->padctl;
2058
2059 value = padctl_readl(padctl,
2060 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));
2061
2062 if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||
2063 (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {
2064 tegra210_xusb_padctl_vbus_override(padctl, false);
2065 tegra210_xusb_padctl_vbus_override(padctl, true);
2066 return 1;
2067 }
2068
2069 return 0;
2070}
2071
2072static int
2073tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
2074{
2075 unsigned int i;
2076 u32 value;
2077 int err;
2078
2079 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
2080 if (err < 0)
2081 return err;
2082
2083 for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {
2084 fuse->hs_curr_level[i] =
2085 (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
2086 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;
2087 }
2088
2089 fuse->hs_term_range_adj =
2090 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
2091 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
2092
2093 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
2094 if (err < 0)
2095 return err;
2096
2097 fuse->rpd_ctrl =
2098 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &
2099 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK;
2100
2101 return 0;
2102}
2103
2104static struct tegra_xusb_padctl *
2105tegra210_xusb_padctl_probe(struct device *dev,
2106 const struct tegra_xusb_padctl_soc *soc)
2107{
2108 struct tegra210_xusb_padctl *padctl;
2109 int err;
2110
2111 padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
2112 if (!padctl)
2113 return ERR_PTR(-ENOMEM);
2114
2115 padctl->base.dev = dev;
2116 padctl->base.soc = soc;
2117
2118 err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
2119 if (err < 0)
2120 return ERR_PTR(err);
2121
2122 return &padctl->base;
2123}
2124
2125static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
2126{
2127}
2128
2129static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
2130 .probe = tegra210_xusb_padctl_probe,
2131 .remove = tegra210_xusb_padctl_remove,
2132 .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
2133 .hsic_set_idle = tegra210_hsic_set_idle,
2134 .vbus_override = tegra210_xusb_padctl_vbus_override,
2135 .utmi_port_reset = tegra210_utmi_port_reset,
2136};
2137
2138static const char * const tegra210_xusb_padctl_supply_names[] = {
2139 "avdd-pll-utmip",
2140 "avdd-pll-uerefe",
2141 "dvdd-pex-pll",
2142 "hvdd-pex-pll-e",
2143};
2144
2145const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
2146 .num_pads = ARRAY_SIZE(tegra210_pads),
2147 .pads = tegra210_pads,
2148 .ports = {
2149 .usb2 = {
2150 .ops = &tegra210_usb2_port_ops,
2151 .count = 4,
2152 },
2153 .hsic = {
2154 .ops = &tegra210_hsic_port_ops,
2155 .count = 1,
2156 },
2157 .usb3 = {
2158 .ops = &tegra210_usb3_port_ops,
2159 .count = 4,
2160 },
2161 },
2162 .ops = &tegra210_xusb_padctl_ops,
2163 .supply_names = tegra210_xusb_padctl_supply_names,
2164 .num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
2165 .need_fake_usb3_port = true,
2166};
2167EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
2168
2169MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2170MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");
2171MODULE_LICENSE("GPL v2");
2172