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41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44#include "pm80xx_hwi.h"
45
46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47module_param(logging_level, ulong, 0644);
48MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49
50static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51module_param(link_rate, ulong, 0644);
52MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
57
58static struct scsi_transport_template *pm8001_stt;
59
60
61
62
63
64static const struct pm8001_chip_info pm8001_chips[] = {
65 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
66 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
67 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
68 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
69 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
70 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
71 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
72 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
75 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
76};
77static int pm8001_id;
78
79LIST_HEAD(hba_list);
80
81struct workqueue_struct *pm8001_wq;
82
83
84
85
86static struct scsi_host_template pm8001_sht = {
87 .module = THIS_MODULE,
88 .name = DRV_NAME,
89 .queuecommand = sas_queuecommand,
90 .target_alloc = sas_target_alloc,
91 .slave_configure = sas_slave_configure,
92 .scan_finished = pm8001_scan_finished,
93 .scan_start = pm8001_scan_start,
94 .change_queue_depth = sas_change_queue_depth,
95 .bios_param = sas_bios_param,
96 .can_queue = 1,
97 .this_id = -1,
98 .sg_tablesize = SG_ALL,
99 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
100 .eh_device_reset_handler = sas_eh_device_reset_handler,
101 .eh_target_reset_handler = sas_eh_target_reset_handler,
102 .target_destroy = sas_target_destroy,
103 .ioctl = sas_ioctl,
104 .shost_attrs = pm8001_host_attrs,
105 .track_queue_depth = 1,
106};
107
108
109
110
111static struct sas_domain_function_template pm8001_transport_ops = {
112 .lldd_dev_found = pm8001_dev_found,
113 .lldd_dev_gone = pm8001_dev_gone,
114
115 .lldd_execute_task = pm8001_queue_command,
116 .lldd_control_phy = pm8001_phy_control,
117
118 .lldd_abort_task = pm8001_abort_task,
119 .lldd_abort_task_set = pm8001_abort_task_set,
120 .lldd_clear_aca = pm8001_clear_aca,
121 .lldd_clear_task_set = pm8001_clear_task_set,
122 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
123 .lldd_lu_reset = pm8001_lu_reset,
124 .lldd_query_task = pm8001_query_task,
125};
126
127
128
129
130
131
132static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
133{
134 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
135 struct asd_sas_phy *sas_phy = &phy->sas_phy;
136 phy->phy_state = PHY_LINK_DISABLE;
137 phy->pm8001_ha = pm8001_ha;
138 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
139 sas_phy->class = SAS;
140 sas_phy->iproto = SAS_PROTOCOL_ALL;
141 sas_phy->tproto = 0;
142 sas_phy->type = PHY_TYPE_PHYSICAL;
143 sas_phy->role = PHY_ROLE_INITIATOR;
144 sas_phy->oob_mode = OOB_NOT_CONNECTED;
145 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
146 sas_phy->id = phy_id;
147 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
148 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
149 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
150 sas_phy->lldd_phy = phy;
151}
152
153
154
155
156
157
158static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
159{
160 int i;
161
162 if (!pm8001_ha)
163 return;
164
165 for (i = 0; i < USI_MAX_MEMCNT; i++) {
166 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
167 dma_free_coherent(&pm8001_ha->pdev->dev,
168 (pm8001_ha->memoryMap.region[i].total_len +
169 pm8001_ha->memoryMap.region[i].alignment),
170 pm8001_ha->memoryMap.region[i].virt_ptr,
171 pm8001_ha->memoryMap.region[i].phys_addr);
172 }
173 }
174 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
175 flush_workqueue(pm8001_wq);
176 kfree(pm8001_ha->tags);
177 kfree(pm8001_ha);
178}
179
180#ifdef PM8001_USE_TASKLET
181
182
183
184
185
186
187static void pm8001_tasklet(unsigned long opaque)
188{
189 struct pm8001_hba_info *pm8001_ha;
190 struct isr_param *irq_vector;
191
192 irq_vector = (struct isr_param *)opaque;
193 pm8001_ha = irq_vector->drv_inst;
194 if (unlikely(!pm8001_ha))
195 BUG_ON(1);
196 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
197}
198#endif
199
200
201
202
203
204
205
206
207static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
208{
209 struct isr_param *irq_vector;
210 struct pm8001_hba_info *pm8001_ha;
211 irqreturn_t ret = IRQ_HANDLED;
212 irq_vector = (struct isr_param *)opaque;
213 pm8001_ha = irq_vector->drv_inst;
214
215 if (unlikely(!pm8001_ha))
216 return IRQ_NONE;
217 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
218 return IRQ_NONE;
219#ifdef PM8001_USE_TASKLET
220 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
221#else
222 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
223#endif
224 return ret;
225}
226
227
228
229
230
231
232static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
233{
234 struct pm8001_hba_info *pm8001_ha;
235 irqreturn_t ret = IRQ_HANDLED;
236 struct sas_ha_struct *sha = dev_id;
237 pm8001_ha = sha->lldd_ha;
238 if (unlikely(!pm8001_ha))
239 return IRQ_NONE;
240 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
241 return IRQ_NONE;
242
243#ifdef PM8001_USE_TASKLET
244 tasklet_schedule(&pm8001_ha->tasklet[0]);
245#else
246 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
247#endif
248 return ret;
249}
250
251
252
253
254
255
256static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
257 const struct pci_device_id *ent)
258{
259 int i;
260 spin_lock_init(&pm8001_ha->lock);
261 spin_lock_init(&pm8001_ha->bitmap_lock);
262 PM8001_INIT_DBG(pm8001_ha,
263 pm8001_printk("pm8001_alloc: PHY:%x\n",
264 pm8001_ha->chip->n_phy));
265 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
266 pm8001_phy_init(pm8001_ha, i);
267 pm8001_ha->port[i].wide_port_phymap = 0;
268 pm8001_ha->port[i].port_attached = 0;
269 pm8001_ha->port[i].port_state = 0;
270 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
271 }
272
273 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
274 if (!pm8001_ha->tags)
275 goto err_out;
276
277 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
278 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
279 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
280 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
281
282
283 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
284 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
285 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
286 pm8001_ha->memoryMap.region[IOP].alignment = 32;
287
288 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
289
290 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
291 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
292 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
293 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
294
295 if ((ent->driver_data) != chip_8001) {
296
297 pm8001_ha->memoryMap.region[IB+i].num_elements =
298 PM8001_MPI_QUEUE;
299 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
300 pm8001_ha->memoryMap.region[IB+i].total_len =
301 PM8001_MPI_QUEUE * 128;
302 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
303 } else {
304 pm8001_ha->memoryMap.region[IB+i].num_elements =
305 PM8001_MPI_QUEUE;
306 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
307 pm8001_ha->memoryMap.region[IB+i].total_len =
308 PM8001_MPI_QUEUE * 64;
309 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
310 }
311 }
312
313 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
314
315 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
316 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
317 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
318 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
319
320 if (ent->driver_data != chip_8001) {
321
322 pm8001_ha->memoryMap.region[OB+i].num_elements =
323 PM8001_MPI_QUEUE;
324 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
325 pm8001_ha->memoryMap.region[OB+i].total_len =
326 PM8001_MPI_QUEUE * 128;
327 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
328 } else {
329
330 pm8001_ha->memoryMap.region[OB+i].num_elements =
331 PM8001_MPI_QUEUE;
332 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
333 pm8001_ha->memoryMap.region[OB+i].total_len =
334 PM8001_MPI_QUEUE * 64;
335 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
336 }
337
338 }
339
340 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
341 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
342 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
343
344 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
345 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
346 sizeof(struct pm8001_device);
347 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
348 sizeof(struct pm8001_device);
349
350
351 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
352 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
353 sizeof(struct pm8001_ccb_info);
354 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
355 sizeof(struct pm8001_ccb_info);
356
357
358 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
359
360 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
361 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
362 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
363 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
364 for (i = 0; i < USI_MAX_MEMCNT; i++) {
365 if (pm8001_mem_alloc(pm8001_ha->pdev,
366 &pm8001_ha->memoryMap.region[i].virt_ptr,
367 &pm8001_ha->memoryMap.region[i].phys_addr,
368 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
369 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
370 pm8001_ha->memoryMap.region[i].total_len,
371 pm8001_ha->memoryMap.region[i].alignment) != 0) {
372 PM8001_FAIL_DBG(pm8001_ha,
373 pm8001_printk("Mem%d alloc failed\n",
374 i));
375 goto err_out;
376 }
377 }
378
379 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
380 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
381 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
382 pm8001_ha->devices[i].id = i;
383 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
384 pm8001_ha->devices[i].running_req = 0;
385 }
386 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
387 for (i = 0; i < PM8001_MAX_CCB; i++) {
388 pm8001_ha->ccb_info[i].ccb_dma_handle =
389 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
390 i * sizeof(struct pm8001_ccb_info);
391 pm8001_ha->ccb_info[i].task = NULL;
392 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
393 pm8001_ha->ccb_info[i].device = NULL;
394 ++pm8001_ha->tags_num;
395 }
396 pm8001_ha->flags = PM8001F_INIT_TIME;
397
398 pm8001_tag_init(pm8001_ha);
399 return 0;
400err_out:
401 return 1;
402}
403
404
405
406
407
408
409static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
410{
411 u32 bar;
412 u32 logicalBar = 0;
413 struct pci_dev *pdev;
414
415 pdev = pm8001_ha->pdev;
416
417 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
418
419
420
421
422
423
424
425
426 if ((bar == 1) || (bar == 3))
427 continue;
428 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
429 pm8001_ha->io_mem[logicalBar].membase =
430 pci_resource_start(pdev, bar);
431 pm8001_ha->io_mem[logicalBar].memsize =
432 pci_resource_len(pdev, bar);
433 pm8001_ha->io_mem[logicalBar].memvirtaddr =
434 ioremap(pm8001_ha->io_mem[logicalBar].membase,
435 pm8001_ha->io_mem[logicalBar].memsize);
436 PM8001_INIT_DBG(pm8001_ha,
437 pm8001_printk("PCI: bar %d, logicalBar %d ",
438 bar, logicalBar));
439 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
440 "base addr %llx virt_addr=%llx len=%d\n",
441 (u64)pm8001_ha->io_mem[logicalBar].membase,
442 (u64)(unsigned long)
443 pm8001_ha->io_mem[logicalBar].memvirtaddr,
444 pm8001_ha->io_mem[logicalBar].memsize));
445 } else {
446 pm8001_ha->io_mem[logicalBar].membase = 0;
447 pm8001_ha->io_mem[logicalBar].memsize = 0;
448 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
449 }
450 logicalBar++;
451 }
452 return 0;
453}
454
455
456
457
458
459
460
461static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
462 const struct pci_device_id *ent,
463 struct Scsi_Host *shost)
464
465{
466 struct pm8001_hba_info *pm8001_ha;
467 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
468 int j;
469
470 pm8001_ha = sha->lldd_ha;
471 if (!pm8001_ha)
472 return NULL;
473
474 pm8001_ha->pdev = pdev;
475 pm8001_ha->dev = &pdev->dev;
476 pm8001_ha->chip_id = ent->driver_data;
477 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
478 pm8001_ha->irq = pdev->irq;
479 pm8001_ha->sas = sha;
480 pm8001_ha->shost = shost;
481 pm8001_ha->id = pm8001_id++;
482 pm8001_ha->logging_level = logging_level;
483 if (link_rate >= 1 && link_rate <= 15)
484 pm8001_ha->link_rate = (link_rate << 8);
485 else {
486 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
487 LINKRATE_60 | LINKRATE_120;
488 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
489 "Setting link rate to default value\n"));
490 }
491 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
492
493 if (pm8001_ha->chip_id != chip_8001)
494 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
495 else
496 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
497
498#ifdef PM8001_USE_TASKLET
499
500 if ((!pdev->msix_cap || !pci_msi_enabled())
501 || (pm8001_ha->chip_id == chip_8001))
502 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
503 (unsigned long)&(pm8001_ha->irq_vector[0]));
504 else
505 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
506 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
507 (unsigned long)&(pm8001_ha->irq_vector[j]));
508#endif
509 pm8001_ioremap(pm8001_ha);
510 if (!pm8001_alloc(pm8001_ha, ent))
511 return pm8001_ha;
512 pm8001_free(pm8001_ha);
513 return NULL;
514}
515
516
517
518
519
520static int pci_go_44(struct pci_dev *pdev)
521{
522 int rc;
523
524 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
525 if (rc) {
526 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
527 if (rc)
528 dev_printk(KERN_ERR, &pdev->dev,
529 "32-bit DMA enable failed\n");
530 }
531 return rc;
532}
533
534
535
536
537
538
539static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
540 const struct pm8001_chip_info *chip_info)
541{
542 int phy_nr, port_nr;
543 struct asd_sas_phy **arr_phy;
544 struct asd_sas_port **arr_port;
545 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546
547 phy_nr = chip_info->n_phy;
548 port_nr = phy_nr;
549 memset(sha, 0x00, sizeof(*sha));
550 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
551 if (!arr_phy)
552 goto exit;
553 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
554 if (!arr_port)
555 goto exit_free2;
556
557 sha->sas_phy = arr_phy;
558 sha->sas_port = arr_port;
559 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
560 if (!sha->lldd_ha)
561 goto exit_free1;
562
563 shost->transportt = pm8001_stt;
564 shost->max_id = PM8001_MAX_DEVICES;
565 shost->max_lun = 8;
566 shost->max_channel = 0;
567 shost->unique_id = pm8001_id;
568 shost->max_cmd_len = 16;
569 shost->can_queue = PM8001_CAN_QUEUE;
570 shost->cmd_per_lun = 32;
571 return 0;
572exit_free1:
573 kfree(arr_port);
574exit_free2:
575 kfree(arr_phy);
576exit:
577 return -1;
578}
579
580
581
582
583
584
585static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
586 const struct pm8001_chip_info *chip_info)
587{
588 int i = 0;
589 struct pm8001_hba_info *pm8001_ha;
590 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591
592 pm8001_ha = sha->lldd_ha;
593 for (i = 0; i < chip_info->n_phy; i++) {
594 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
595 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
596 sha->sas_phy[i]->sas_addr =
597 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
598 }
599 sha->sas_ha_name = DRV_NAME;
600 sha->dev = pm8001_ha->dev;
601 sha->strict_wide_ports = 1;
602 sha->lldd_module = THIS_MODULE;
603 sha->sas_addr = &pm8001_ha->sas_addr[0];
604 sha->num_phys = chip_info->n_phy;
605 sha->core.shost = shost;
606}
607
608
609
610
611
612
613
614
615static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
616{
617 u8 i, j;
618 u8 sas_add[8];
619#ifdef PM8001_READ_VPD
620
621
622
623
624 DECLARE_COMPLETION_ONSTACK(completion);
625 struct pm8001_ioctl_payload payload;
626 u16 deviceid;
627 int rc;
628
629 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
630 pm8001_ha->nvmd_completion = &completion;
631
632 if (pm8001_ha->chip_id == chip_8001) {
633 if (deviceid == 0x8081 || deviceid == 0x0042) {
634 payload.minor_function = 4;
635 payload.length = 4096;
636 } else {
637 payload.minor_function = 0;
638 payload.length = 128;
639 }
640 } else if ((pm8001_ha->chip_id == chip_8070 ||
641 pm8001_ha->chip_id == chip_8072) &&
642 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
643 payload.minor_function = 4;
644 payload.length = 4096;
645 } else {
646 payload.minor_function = 1;
647 payload.length = 4096;
648 }
649 payload.offset = 0;
650 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
651 if (!payload.func_specific) {
652 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
653 return;
654 }
655 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
656 if (rc) {
657 kfree(payload.func_specific);
658 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
659 return;
660 }
661 wait_for_completion(&completion);
662
663 for (i = 0, j = 0; i <= 7; i++, j++) {
664 if (pm8001_ha->chip_id == chip_8001) {
665 if (deviceid == 0x8081)
666 pm8001_ha->sas_addr[j] =
667 payload.func_specific[0x704 + i];
668 else if (deviceid == 0x0042)
669 pm8001_ha->sas_addr[j] =
670 payload.func_specific[0x010 + i];
671 } else if ((pm8001_ha->chip_id == chip_8070 ||
672 pm8001_ha->chip_id == chip_8072) &&
673 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
674 pm8001_ha->sas_addr[j] =
675 payload.func_specific[0x010 + i];
676 } else
677 pm8001_ha->sas_addr[j] =
678 payload.func_specific[0x804 + i];
679 }
680 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
681 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
682 if (i && ((i % 4) == 0))
683 sas_add[7] = sas_add[7] + 4;
684 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
685 sas_add, SAS_ADDR_SIZE);
686 PM8001_INIT_DBG(pm8001_ha,
687 pm8001_printk("phy %d sas_addr = %016llx\n", i,
688 pm8001_ha->phy[i].dev_sas_addr));
689 }
690 kfree(payload.func_specific);
691#else
692 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
693 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
694 pm8001_ha->phy[i].dev_sas_addr =
695 cpu_to_be64((u64)
696 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
697 }
698 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
699 SAS_ADDR_SIZE);
700#endif
701}
702
703
704
705
706
707static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
708{
709
710#ifdef PM8001_READ_VPD
711
712 DECLARE_COMPLETION_ONSTACK(completion);
713 struct pm8001_ioctl_payload payload;
714 int rc;
715
716 pm8001_ha->nvmd_completion = &completion;
717
718 payload.minor_function = 6;
719 payload.offset = 0;
720 payload.length = 4096;
721 payload.func_specific = kzalloc(4096, GFP_KERNEL);
722 if (!payload.func_specific)
723 return -ENOMEM;
724
725 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
726 if (rc) {
727 kfree(payload.func_specific);
728 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
729 return -ENOMEM;
730 }
731 wait_for_completion(&completion);
732 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
733 kfree(payload.func_specific);
734#endif
735 return 0;
736}
737
738struct pm8001_mpi3_phy_pg_trx_config {
739 u32 LaneLosCfg;
740 u32 LanePgaCfg1;
741 u32 LanePisoCfg1;
742 u32 LanePisoCfg2;
743 u32 LanePisoCfg3;
744 u32 LanePisoCfg4;
745 u32 LanePisoCfg5;
746 u32 LanePisoCfg6;
747 u32 LaneBctCtrl;
748};
749
750
751
752
753
754
755static
756void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
757 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
758{
759 phycfg->LaneLosCfg = 0x00000132;
760 phycfg->LanePgaCfg1 = 0x00203949;
761 phycfg->LanePisoCfg1 = 0x000000FF;
762 phycfg->LanePisoCfg2 = 0xFF000001;
763 phycfg->LanePisoCfg3 = 0xE7011300;
764 phycfg->LanePisoCfg4 = 0x631C40C0;
765 phycfg->LanePisoCfg5 = 0xF8102036;
766 phycfg->LanePisoCfg6 = 0xF74A1000;
767 phycfg->LaneBctCtrl = 0x00FB33F8;
768}
769
770
771
772
773
774
775static
776void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
777 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
778{
779 phycfg->LaneLosCfg = 0x00000132;
780 phycfg->LanePgaCfg1 = 0x00203949;
781 phycfg->LanePisoCfg1 = 0x000000FF;
782 phycfg->LanePisoCfg2 = 0xFF000001;
783 phycfg->LanePisoCfg3 = 0xE7011300;
784 phycfg->LanePisoCfg4 = 0x63349140;
785 phycfg->LanePisoCfg5 = 0xF8102036;
786 phycfg->LanePisoCfg6 = 0xF80D9300;
787 phycfg->LaneBctCtrl = 0x00FB33F8;
788}
789
790
791
792
793
794
795static
796void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
797{
798 switch (pm8001_ha->pdev->subsystem_device) {
799 case 0x0070:
800 case 0x0072:
801 *phymask = 0x0000;
802 break;
803
804 case 0x0071:
805 case 0x0073:
806 *phymask = 0xFFFF;
807 break;
808
809 case 0x0080:
810 *phymask = 0x00F0;
811 break;
812
813 case 0x0081:
814 *phymask = 0x0FF0;
815 break;
816
817 case 0x0082:
818 *phymask = 0xFF00;
819 break;
820
821 default:
822 PM8001_INIT_DBG(pm8001_ha,
823 pm8001_printk("Unknown subsystem device=0x%.04x",
824 pm8001_ha->pdev->subsystem_device));
825 }
826}
827
828
829
830
831
832static
833int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
834{
835 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
836 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
837 int phymask = 0;
838 int i = 0;
839
840 memset(&phycfg_int, 0, sizeof(phycfg_int));
841 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
842
843 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
844 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
845 pm8001_get_phy_mask(pm8001_ha, &phymask);
846
847 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
848 if (phymask & (1 << i)) {
849 pm8001_set_phy_profile_single(pm8001_ha, i,
850 sizeof(phycfg_int) / sizeof(u32),
851 (u32 *)&phycfg_int);
852
853 } else {
854 pm8001_set_phy_profile_single(pm8001_ha, i,
855 sizeof(phycfg_ext) / sizeof(u32),
856 (u32 *)&phycfg_ext);
857 }
858 }
859
860 return 0;
861}
862
863
864
865
866
867static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
868{
869 switch (pm8001_ha->pdev->subsystem_vendor) {
870 case PCI_VENDOR_ID_ATTO:
871 if (pm8001_ha->pdev->device == 0x0042)
872 return 0;
873 else
874 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
875
876 case PCI_VENDOR_ID_ADAPTEC2:
877 case 0:
878 return 0;
879
880 default:
881 return pm8001_get_phy_settings_info(pm8001_ha);
882 }
883}
884
885#ifdef PM8001_USE_MSIX
886
887
888
889
890
891static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
892{
893 u32 i = 0, j = 0;
894 u32 number_of_intr;
895 int flag = 0;
896 int rc;
897
898
899 if (pm8001_ha->chip_id == chip_8001) {
900 number_of_intr = 1;
901 } else {
902 number_of_intr = PM8001_MAX_MSIX_VEC;
903 flag &= ~IRQF_SHARED;
904 }
905
906 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
907 number_of_intr, PCI_IRQ_MSIX);
908 if (rc < 0)
909 return rc;
910 pm8001_ha->number_of_intr = number_of_intr;
911
912 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
913 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
914 rc, pm8001_ha->number_of_intr));
915
916 for (i = 0; i < number_of_intr; i++) {
917 snprintf(pm8001_ha->intr_drvname[i],
918 sizeof(pm8001_ha->intr_drvname[0]),
919 "%s-%d", pm8001_ha->name, i);
920 pm8001_ha->irq_vector[i].irq_id = i;
921 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
922
923 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
924 pm8001_interrupt_handler_msix, flag,
925 pm8001_ha->intr_drvname[i],
926 &(pm8001_ha->irq_vector[i]));
927 if (rc) {
928 for (j = 0; j < i; j++) {
929 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
930 &(pm8001_ha->irq_vector[i]));
931 }
932 pci_free_irq_vectors(pm8001_ha->pdev);
933 break;
934 }
935 }
936
937 return rc;
938}
939#endif
940
941
942
943
944
945static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
946{
947 struct pci_dev *pdev;
948 int rc;
949
950 pdev = pm8001_ha->pdev;
951
952#ifdef PM8001_USE_MSIX
953 if (pdev->msix_cap && pci_msi_enabled())
954 return pm8001_setup_msix(pm8001_ha);
955 else {
956 PM8001_INIT_DBG(pm8001_ha,
957 pm8001_printk("MSIX not supported!!!\n"));
958 goto intx;
959 }
960#endif
961
962intx:
963
964 pm8001_ha->irq_vector[0].irq_id = 0;
965 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
966 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
967 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
968 return rc;
969}
970
971
972
973
974
975
976
977
978
979
980static int pm8001_pci_probe(struct pci_dev *pdev,
981 const struct pci_device_id *ent)
982{
983 unsigned int rc;
984 u32 pci_reg;
985 u8 i = 0;
986 struct pm8001_hba_info *pm8001_ha;
987 struct Scsi_Host *shost = NULL;
988 const struct pm8001_chip_info *chip;
989
990 dev_printk(KERN_INFO, &pdev->dev,
991 "pm80xx: driver version %s\n", DRV_VERSION);
992 rc = pci_enable_device(pdev);
993 if (rc)
994 goto err_out_enable;
995 pci_set_master(pdev);
996
997
998
999
1000
1001 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1002 pci_reg |= 0x157;
1003 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1004 rc = pci_request_regions(pdev, DRV_NAME);
1005 if (rc)
1006 goto err_out_disable;
1007 rc = pci_go_44(pdev);
1008 if (rc)
1009 goto err_out_regions;
1010
1011 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1012 if (!shost) {
1013 rc = -ENOMEM;
1014 goto err_out_regions;
1015 }
1016 chip = &pm8001_chips[ent->driver_data];
1017 SHOST_TO_SAS_HA(shost) =
1018 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1019 if (!SHOST_TO_SAS_HA(shost)) {
1020 rc = -ENOMEM;
1021 goto err_out_free_host;
1022 }
1023
1024 rc = pm8001_prep_sas_ha_init(shost, chip);
1025 if (rc) {
1026 rc = -ENOMEM;
1027 goto err_out_free;
1028 }
1029 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1030
1031 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1032 if (!pm8001_ha) {
1033 rc = -ENOMEM;
1034 goto err_out_free;
1035 }
1036 list_add_tail(&pm8001_ha->list, &hba_list);
1037 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1038 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1039 if (rc) {
1040 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1041 "chip_init failed [ret: %d]\n", rc));
1042 goto err_out_ha_free;
1043 }
1044
1045 rc = scsi_add_host(shost, &pdev->dev);
1046 if (rc)
1047 goto err_out_ha_free;
1048 rc = pm8001_request_irq(pm8001_ha);
1049 if (rc) {
1050 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1051 "pm8001_request_irq failed [ret: %d]\n", rc));
1052 goto err_out_shost;
1053 }
1054
1055 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1056 if (pm8001_ha->chip_id != chip_8001) {
1057 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1058 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1059
1060 pm80xx_set_thermal_config(pm8001_ha);
1061 }
1062
1063 pm8001_init_sas_add(pm8001_ha);
1064
1065 if (pm8001_configure_phy_settings(pm8001_ha))
1066 goto err_out_shost;
1067
1068 pm8001_post_sas_ha_init(shost, chip);
1069 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1070 if (rc)
1071 goto err_out_shost;
1072 scsi_scan_host(pm8001_ha->shost);
1073 pm8001_ha->flags = PM8001F_RUN_TIME;
1074 return 0;
1075
1076err_out_shost:
1077 scsi_remove_host(pm8001_ha->shost);
1078err_out_ha_free:
1079 pm8001_free(pm8001_ha);
1080err_out_free:
1081 kfree(SHOST_TO_SAS_HA(shost));
1082err_out_free_host:
1083 scsi_host_put(shost);
1084err_out_regions:
1085 pci_release_regions(pdev);
1086err_out_disable:
1087 pci_disable_device(pdev);
1088err_out_enable:
1089 return rc;
1090}
1091
1092static void pm8001_pci_remove(struct pci_dev *pdev)
1093{
1094 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1095 struct pm8001_hba_info *pm8001_ha;
1096 int i, j;
1097 pm8001_ha = sha->lldd_ha;
1098 sas_unregister_ha(sha);
1099 sas_remove_host(pm8001_ha->shost);
1100 list_del(&pm8001_ha->list);
1101 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1102 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1103
1104#ifdef PM8001_USE_MSIX
1105 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1106 synchronize_irq(pci_irq_vector(pdev, i));
1107 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1108 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1109 pci_free_irq_vectors(pdev);
1110#else
1111 free_irq(pm8001_ha->irq, sha);
1112#endif
1113#ifdef PM8001_USE_TASKLET
1114
1115 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1116 (pm8001_ha->chip_id == chip_8001))
1117 tasklet_kill(&pm8001_ha->tasklet[0]);
1118 else
1119 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1120 tasklet_kill(&pm8001_ha->tasklet[j]);
1121#endif
1122 scsi_host_put(pm8001_ha->shost);
1123 pm8001_free(pm8001_ha);
1124 kfree(sha->sas_phy);
1125 kfree(sha->sas_port);
1126 kfree(sha);
1127 pci_release_regions(pdev);
1128 pci_disable_device(pdev);
1129}
1130
1131
1132
1133
1134
1135
1136
1137
1138static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1139{
1140 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1141 struct pm8001_hba_info *pm8001_ha;
1142 int i, j;
1143 u32 device_state;
1144 pm8001_ha = sha->lldd_ha;
1145 sas_suspend_ha(sha);
1146 flush_workqueue(pm8001_wq);
1147 scsi_block_requests(pm8001_ha->shost);
1148 if (!pdev->pm_cap) {
1149 dev_err(&pdev->dev, " PCI PM not supported\n");
1150 return -ENODEV;
1151 }
1152 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1153 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1154#ifdef PM8001_USE_MSIX
1155 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1156 synchronize_irq(pci_irq_vector(pdev, i));
1157 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1158 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1159 pci_free_irq_vectors(pdev);
1160#else
1161 free_irq(pm8001_ha->irq, sha);
1162#endif
1163#ifdef PM8001_USE_TASKLET
1164
1165 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1166 (pm8001_ha->chip_id == chip_8001))
1167 tasklet_kill(&pm8001_ha->tasklet[0]);
1168 else
1169 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1170 tasklet_kill(&pm8001_ha->tasklet[j]);
1171#endif
1172 device_state = pci_choose_state(pdev, state);
1173 pm8001_printk("pdev=0x%p, slot=%s, entering "
1174 "operating state [D%d]\n", pdev,
1175 pm8001_ha->name, device_state);
1176 pci_save_state(pdev);
1177 pci_disable_device(pdev);
1178 pci_set_power_state(pdev, device_state);
1179 return 0;
1180}
1181
1182
1183
1184
1185
1186
1187
1188static int pm8001_pci_resume(struct pci_dev *pdev)
1189{
1190 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1191 struct pm8001_hba_info *pm8001_ha;
1192 int rc;
1193 u8 i = 0, j;
1194 u32 device_state;
1195 DECLARE_COMPLETION_ONSTACK(completion);
1196 pm8001_ha = sha->lldd_ha;
1197 device_state = pdev->current_state;
1198
1199 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1200 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1201
1202 pci_set_power_state(pdev, PCI_D0);
1203 pci_enable_wake(pdev, PCI_D0, 0);
1204 pci_restore_state(pdev);
1205 rc = pci_enable_device(pdev);
1206 if (rc) {
1207 pm8001_printk("slot=%s Enable device failed during resume\n",
1208 pm8001_ha->name);
1209 goto err_out_enable;
1210 }
1211
1212 pci_set_master(pdev);
1213 rc = pci_go_44(pdev);
1214 if (rc)
1215 goto err_out_disable;
1216 sas_prep_resume_ha(sha);
1217
1218 if (pm8001_ha->chip_id == chip_8001) {
1219 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1220 PM8001_INIT_DBG(pm8001_ha,
1221 pm8001_printk("chip soft reset successful\n"));
1222 }
1223 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1224 if (rc)
1225 goto err_out_disable;
1226
1227
1228 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1229
1230 rc = pm8001_request_irq(pm8001_ha);
1231 if (rc)
1232 goto err_out_disable;
1233#ifdef PM8001_USE_TASKLET
1234
1235 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1236 (pm8001_ha->chip_id == chip_8001))
1237 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1238 (unsigned long)&(pm8001_ha->irq_vector[0]));
1239 else
1240 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1241 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1242 (unsigned long)&(pm8001_ha->irq_vector[j]));
1243#endif
1244 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1245 if (pm8001_ha->chip_id != chip_8001) {
1246 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1247 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1248 }
1249
1250
1251
1252
1253
1254
1255 if (pm8001_ha->chip_id == chip_8070 ||
1256 pm8001_ha->chip_id == chip_8072) {
1257 mdelay(500);
1258 }
1259
1260
1261
1262 pm8001_ha->flags = PM8001F_RUN_TIME;
1263 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1264 pm8001_ha->phy[i].enable_completion = &completion;
1265 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1266 wait_for_completion(&completion);
1267 }
1268 sas_resume_ha(sha);
1269 return 0;
1270
1271err_out_disable:
1272 scsi_remove_host(pm8001_ha->shost);
1273 pci_disable_device(pdev);
1274err_out_enable:
1275 return rc;
1276}
1277
1278
1279
1280
1281static struct pci_device_id pm8001_pci_table[] = {
1282 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1283 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1284 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1285 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1286
1287 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1288 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1289 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1290 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1291 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1292 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1293 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1294 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1295 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1296 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1297 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1298 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1299 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1300 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1301 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1303 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1305 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1307 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1309 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1311 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1313 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1315 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1317 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1318 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1319 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1320 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1321 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1322 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1323 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1324 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1325 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1326 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1327 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1328 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1329 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1330 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1331 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1332 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1333 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1334 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1335 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1336 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1337 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1338 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1339 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1340 { PCI_VENDOR_ID_ATTO, 0x8070,
1341 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1342 { PCI_VENDOR_ID_ATTO, 0x8070,
1343 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1344 { PCI_VENDOR_ID_ATTO, 0x8072,
1345 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1346 { PCI_VENDOR_ID_ATTO, 0x8072,
1347 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1348 { PCI_VENDOR_ID_ATTO, 0x8070,
1349 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1350 { PCI_VENDOR_ID_ATTO, 0x8072,
1351 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1352 { PCI_VENDOR_ID_ATTO, 0x8072,
1353 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1354 {}
1355};
1356
1357static struct pci_driver pm8001_pci_driver = {
1358 .name = DRV_NAME,
1359 .id_table = pm8001_pci_table,
1360 .probe = pm8001_pci_probe,
1361 .remove = pm8001_pci_remove,
1362 .suspend = pm8001_pci_suspend,
1363 .resume = pm8001_pci_resume,
1364};
1365
1366
1367
1368
1369static int __init pm8001_init(void)
1370{
1371 int rc = -ENOMEM;
1372
1373 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1374 if (!pm8001_wq)
1375 goto err;
1376
1377 pm8001_id = 0;
1378 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1379 if (!pm8001_stt)
1380 goto err_wq;
1381 rc = pci_register_driver(&pm8001_pci_driver);
1382 if (rc)
1383 goto err_tp;
1384 return 0;
1385
1386err_tp:
1387 sas_release_transport(pm8001_stt);
1388err_wq:
1389 destroy_workqueue(pm8001_wq);
1390err:
1391 return rc;
1392}
1393
1394static void __exit pm8001_exit(void)
1395{
1396 pci_unregister_driver(&pm8001_pci_driver);
1397 sas_release_transport(pm8001_stt);
1398 destroy_workqueue(pm8001_wq);
1399}
1400
1401module_init(pm8001_init);
1402module_exit(pm8001_exit);
1403
1404MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1405MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1406MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1407MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1408MODULE_DESCRIPTION(
1409 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1410 "SAS/SATA controller driver");
1411MODULE_VERSION(DRV_VERSION);
1412MODULE_LICENSE("GPL");
1413MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1414
1415
