LXR linux/drivers/staging/comedi/drivers/plx9080.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * plx9080.h
   4 *
   5 * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   6 *
   7 ********************************************************************
   8 *
   9 * Copyright (C) 1999 RG Studio s.c.
  10 * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
  11 *
  12 * Portions (C) SBE Inc., used by permission.
  13 */
  14
  15#ifndef __COMEDI_PLX9080_H
  16#define __COMEDI_PLX9080_H
  17
  18#include <linux/compiler.h>
  19#include <linux/types.h>
  20#include <linux/bitops.h>
  21#include <linux/delay.h>
  22#include <linux/errno.h>
  23#include <linux/io.h>
  24
  25/**
  26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
  27 * @pci_start_addr:     PCI Bus address for transfer (DMAPADR).
  28 * @local_start_addr:   Local Bus address for transfer (DMALADR).
  29 * @transfer_size:      Transfer size in bytes (max 8 MiB) (DMASIZ).
  30 * @next:               Address of next descriptor + flags (DMADPR).
  31 *
  32 * Describes the format of a scatter-gather DMA descriptor for the PLX
  33 * PCI 9080.  All members are raw, little-endian register values that
  34 * will be transferred by the DMA engine from local or PCI memory into
  35 * corresponding registers for the DMA channel.
  36 *
  37 * The DMA descriptors must be aligned on a 16-byte boundary.  Bits 3:0
  38 * of @next contain flags describing the address space of the next
  39 * descriptor (local or PCI), an "end of chain" marker, an "interrupt on
  40 * terminal count" bit, and a data transfer direction.
  41 */
  42struct plx_dma_desc {
  43        __le32 pci_start_addr;
  44        __le32 local_start_addr;
  45        __le32 transfer_size;
  46        __le32 next;
  47};
  48
  49/*
  50 * Register Offsets and Bit Definitions
  51 */
  52
  53/* Local Address Space 0 Range Register */
  54#define PLX_REG_LAS0RR          0x0000
  55/* Local Address Space 1 Range Register */
  56#define PLX_REG_LAS1RR          0x00f0
  57
  58#define PLX_LASRR_IO            BIT(0)          /* Map to: 1=I/O, 0=Mem */
  59#define PLX_LASRR_MLOC_ANY32    (BIT(1) * 0)    /* Locate anywhere in 32 bit */
  60#define PLX_LASRR_MLOC_LT1MB    (BIT(1) * 1)    /* Locate in 1st meg */
  61#define PLX_LASRR_MLOC_ANY64    (BIT(1) * 2)    /* Locate anywhere in 64 bit */
  62#define PLX_LASRR_MLOC_MASK     GENMASK(2, 1)   /* Memory location bits */
  63#define PLX_LASRR_PREFETCH      BIT(3)          /* Memory is prefetchable */
  64/* bits that specify range for memory space decode bits */
  65#define PLX_LASRR_MEM_MASK      GENMASK(31, 4)
  66/* bits that specify range for i/o space decode bits */
  67#define PLX_LASRR_IO_MASK       GENMASK(31, 2)
  68
  69/* Local Address Space 0 Local Base Address (Remap) Register */
  70#define PLX_REG_LAS0BA          0x0004
  71/* Local Address Space 1 Local Base Address (Remap) Register */
  72#define PLX_REG_LAS1BA          0x00f4
  73
  74#define PLX_LASBA_EN            BIT(0)          /* Enable slave decode */
  75/* bits that specify local base address for memory space */
  76#define PLX_LASBA_MEM_MASK      GENMASK(31, 4)
  77/* bits that specify local base address for i/o space */
  78#define PLX_LASBA_IO_MASK       GENMASK(31, 2)
  79
  80/* Mode/Arbitration Register */
  81#define PLX_REG_MARBR           0x0008
  82/* DMA Arbitration Register (alias of MARBR). */
  83#define PLX_REG_DMAARB          0x00ac
  84
  85/* Local Bus Latency Timer */
  86#define PLX_MARBR_LT(x)         (BIT(0) * ((x) & 0xff))
  87#define PLX_MARBR_LT_MASK       GENMASK(7, 0)
  88#define PLX_MARBR_TO_LT(r)      ((r) & PLX_MARBR_LT_MASK)
  89/* Local Bus Pause Timer */
  90#define PLX_MARBR_PT(x)         (BIT(8) * ((x) & 0xff))
  91#define PLX_MARBR_PT_MASK       GENMASK(15, 8)
  92#define PLX_MARBR_TO_PT(r)      (((r) & PLX_MARBR_PT_MASK) >> 8)
  93/* Local Bus Latency Timer Enable */
  94#define PLX_MARBR_LTEN          BIT(16)
  95/* Local Bus Pause Timer Enable */
  96#define PLX_MARBR_PTEN          BIT(17)
  97/* Local Bus BREQ Enable */
  98#define PLX_MARBR_BREQEN        BIT(18)
  99/* DMA Channel Priority */
 100#define PLX_MARBR_PRIO_ROT      (BIT(19) * 0)   /* Rotational priority */
 101#define PLX_MARBR_PRIO_DMA0     (BIT(19) * 1)   /* DMA channel 0 has priority */
 102#define PLX_MARBR_PRIO_DMA1     (BIT(19) * 2)   /* DMA channel 1 has priority */
 103#define PLX_MARBR_PRIO_MASK     GENMASK(20, 19)
 104/* Local Bus Direct Slave Give Up Bus Mode */
 105#define PLX_MARBR_DSGUBM        BIT(21)
 106/* Direct Slace LLOCKo# Enable */
 107#define PLX_MARBR_DSLLOCKOEN    BIT(22)
 108/* PCI Request Mode */
 109#define PLX_MARBR_PCIREQM       BIT(23)
 110/* PCI Specification v2.1 Mode */
 111#define PLX_MARBR_PCIV21M       BIT(24)
 112/* PCI Read No Write Mode */
 113#define PLX_MARBR_PCIRNWM       BIT(25)
 114/* PCI Read with Write Flush Mode */
 115#define PLX_MARBR_PCIRWFM       BIT(26)
 116/* Gate Local Bus Latency Timer with BREQ */
 117#define PLX_MARBR_GLTBREQ       BIT(27)
 118/* PCI Read No Flush Mode */
 119#define PLX_MARBR_PCIRNFM       BIT(28)
 120/*
 121 * Make reads from PCI Configuration register 0 return Subsystem ID and
 122 * Subsystem Vendor ID instead of Device ID and Vendor ID
 123 */
 124#define PLX_MARBR_SUBSYSIDS     BIT(29)
 125
 126/* Big/Little Endian Descriptor Register */
 127#define PLX_REG_BIGEND          0x000c
 128
 129/* Configuration Register Big Endian Mode */
 130#define PLX_BIGEND_CONFIG       BIT(0)
 131/* Direct Master Big Endian Mode */
 132#define PLX_BIGEND_DM           BIT(1)
 133/* Direct Slave Address Space 0 Big Endian Mode */
 134#define PLX_BIGEND_DSAS0        BIT(2)
 135/* Direct Slave Expansion ROM Big Endian Mode */
 136#define PLX_BIGEND_EROM         BIT(3)
 137/* Big Endian Byte Lane Mode - use most significant byte lanes */
 138#define PLX_BIGEND_BEBLM        BIT(4)
 139/* Direct Slave Address Space 1 Big Endian Mode */
 140#define PLX_BIGEND_DSAS1        BIT(5)
 141/* DMA Channel 1 Big Endian Mode */
 142#define PLX_BIGEND_DMA1         BIT(6)
 143/* DMA Channel 0 Big Endian Mode */
 144#define PLX_BIGEND_DMA0         BIT(7)
 145/* DMA Channel N Big Endian Mode (N <= 1) */
 146#define PLX_BIGEND_DMA(n)       ((n) ? PLX_BIGEND_DMA1 : PLX_BIGEND_DMA0)
 147
 148/*
 149 * Note: The Expansion ROM  stuff is only relevant to the PC environment.
 150 *       This expansion ROM code is executed by the host CPU at boot time.
 151 *       For this reason no bit definitions are provided here.
 152 */
 153
 154/* Expansion ROM Range Register */
 155#define PLX_REG_EROMRR          0x0010
 156/* Expansion ROM Local Base Address (Remap) Register */
 157#define PLX_REG_EROMBA          0x0014
 158
 159/* Local Address Space 0/Expansion ROM Bus Region Descriptor Register */
 160#define PLX_REG_LBRD0           0x0018
 161/* Local Address Space 1 Bus Region Descriptor Register */
 162#define PLX_REG_LBRD1           0x00f8
 163
 164/* Memory Space Local Bus Width */
 165#define PLX_LBRD_MSWIDTH_8      (BIT(0) * 0)    /* 8 bits wide */
 166#define PLX_LBRD_MSWIDTH_16     (BIT(0) * 1)    /* 16 bits wide */
 167#define PLX_LBRD_MSWIDTH_32     (BIT(0) * 2)    /* 32 bits wide */
 168#define PLX_LBRD_MSWIDTH_32A    (BIT(0) * 3)    /* 32 bits wide */
 169#define PLX_LBRD_MSWIDTH_MASK   GENMASK(1, 0)
 170/* Memory Space Internal Wait States */
 171#define PLX_LBRD_MSIWS(x)       (BIT(2) * ((x) & 0xf))
 172#define PLX_LBRD_MSIWS_MASK     GENMASK(5, 2)
 173#define PLX_LBRD_TO_MSIWS(r)    (((r) & PLS_LBRD_MSIWS_MASK) >> 2)
 174/* Memory Space Ready Input Enable */
 175#define PLX_LBRD_MSREADYIEN     BIT(6)
 176/* Memory Space BTERM# Input Enable */
 177#define PLX_LBRD_MSBTERMIEN     BIT(7)
 178/* Memory Space 0 Prefetch Disable (LBRD0 only) */
 179#define PLX_LBRD0_MSPREDIS      BIT(8)
 180/* Memory Space 1 Burst Enable (LBRD1 only) */
 181#define PLX_LBRD1_MSBURSTEN     BIT(8)
 182/* Expansion ROM Space Prefetch Disable (LBRD0 only) */
 183#define PLX_LBRD0_EROMPREDIS    BIT(9)
 184/* Memory Space 1 Prefetch Disable (LBRD1 only) */
 185#define PLX_LBRD1_MSPREDIS      BIT(9)
 186/* Read Prefetch Count Enable */
 187#define PLX_LBRD_RPFCOUNTEN     BIT(10)
 188/* Prefetch Counter */
 189#define PLX_LBRD_PFCOUNT(x)     (BIT(11) * ((x) & 0xf))
 190#define PLX_LBRD_PFCOUNT_MASK   GENMASK(14, 11)
 191#define PLX_LBRD_TO_PFCOUNT(r)  (((r) & PLX_LBRD_PFCOUNT_MASK) >> 11)
 192/* Expansion ROM Space Local Bus Width (LBRD0 only) */
 193#define PLX_LBRD0_EROMWIDTH_8   (BIT(16) * 0)   /* 8 bits wide */
 194#define PLX_LBRD0_EROMWIDTH_16  (BIT(16) * 1)   /* 16 bits wide */
 195#define PLX_LBRD0_EROMWIDTH_32  (BIT(16) * 2)   /* 32 bits wide */
 196#define PLX_LBRD0_EROMWIDTH_32A (BIT(16) * 3)   /* 32 bits wide */
 197#define PLX_LBRD0_EROMWIDTH_MASK        GENMASK(17, 16)
 198/* Expansion ROM Space Internal Wait States (LBRD0 only) */
 199#define PLX_LBRD0_EROMIWS(x)    (BIT(18) * ((x) & 0xf))
 200#define PLX_LBRD0_EROMIWS_MASK  GENMASK(21, 18)
 201#define PLX_LBRD0_TO_EROMIWS(r) (((r) & PLX_LBRD0_EROMIWS_MASK) >> 18)
 202/* Expansion ROM Space Ready Input Enable (LBDR0 only) */
 203#define PLX_LBRD0_EROMREADYIEN  BIT(22)
 204/* Expansion ROM Space BTERM# Input Enable (LBRD0 only) */
 205#define PLX_LBRD0_EROMBTERMIEN  BIT(23)
 206/* Memory Space 0 Burst Enable (LBRD0 only) */
 207#define PLX_LBRD0_MSBURSTEN     BIT(24)
 208/* Extra Long Load From Serial EEPROM  (LBRD0 only) */
 209#define PLX_LBRD0_EELONGLOAD    BIT(25)
 210/* Expansion ROM Space Burst Enable (LBRD0 only) */
 211#define PLX_LBRD0_EROMBURSTEN   BIT(26)
 212/* Direct Slave PCI Write Mode - assert TRDY# when FIFO full (LBRD0 only) */
 213#define PLX_LBRD0_DSWMTRDY      BIT(27)
 214/* PCI Target Retry Delay Clocks / 8 (LBRD0 only) */
 215#define PLX_LBRD0_TRDELAY(x)    (BIT(28) * ((x) & 0xF))
 216#define PLX_LBRD0_TRDELAY_MASK  GENMASK(31, 28)
 217#define PLX_LBRD0_TO_TRDELAY(r) (((r) & PLX_LBRD0_TRDELAY_MASK) >> 28)
 218
 219/* Local Range Register for Direct Master to PCI */
 220#define PLX_REG_DMRR            0x001c
 221
 222/* Local Bus Base Address Register for Direct Master to PCI Memory */
 223#define PLX_REG_DMLBAM          0x0020
 224
 225/* Local Base Address Register for Direct Master to PCI IO/CFG */
 226#define PLX_REG_DMLBAI          0x0024
 227
 228/* PCI Base Address (Remap) Register for Direct Master to PCI Memory */
 229#define PLX_REG_DMPBAM          0x0028
 230
 231/* Direct Master Memory Access Enable */
 232#define PLX_DMPBAM_MEMACCEN     BIT(0)
 233/* Direct Master I/O Access Enable */
 234#define PLX_DMPBAM_IOACCEN      BIT(1)
 235/* LLOCK# Input Enable */
 236#define PLX_DMPBAM_LLOCKIEN     BIT(2)
 237/* Direct Master Read Prefetch Size Control (bits 12, 3) */
 238#define PLX_DMPBAM_RPSIZE_CONT  ((BIT(12) * 0) | (BIT(3) * 0))
 239#define PLX_DMPBAM_RPSIZE_4     ((BIT(12) * 0) | (BIT(3) * 1))
 240#define PLX_DMPBAM_RPSIZE_8     ((BIT(12) * 1) | (BIT(3) * 0))
 241#define PLX_DMPBAM_RPSIZE_16    ((BIT(12) * 1) | (BIT(3) * 1))
 242#define PLX_DMPBAM_RPSIZE_MASK  (BIT(12) | BIT(3))
 243/* Direct Master PCI Read Mode - deassert IRDY when FIFO full */
 244#define PLX_DMPBAM_RMIRDY       BIT(4)
 245/* Programmable Almost Full Level (bits 10, 8:5) */
 246#define PLX_DMPBAM_PAFL(x)      ((BIT(10) * !!((x) & 0x10)) | \
 247                                 (BIT(5) * ((x) & 0xf)))
 248#define PLX_DMPBAM_TO_PAFL(v)   ((((BIT(10) & (v)) >> 1) | \
 249                                  (GENMASK(8, 5) & (v))) >> 5)
 250#define PLX_DMPBAM_PAFL_MASK    (BIT(10) | GENMASK(8, 5))
 251/* Write And Invalidate Mode */
 252#define PLX_DMPBAM_WIM          BIT(9)
 253/* Direct Master Prefetch Limit */
 254#define PLX_DBPBAM_PFLIMIT      BIT(11)
 255/* I/O Remap Select */
 256#define PLX_DMPBAM_IOREMAPSEL   BIT(13)
 257/* Direct Master Write Delay */
 258#define PLX_DMPBAM_WDELAY_NONE  (BIT(14) * 0)
 259#define PLX_DMPBAM_WDELAY_4     (BIT(14) * 1)
 260#define PLX_DMPBAM_WDELAY_8     (BIT(14) * 2)
 261#define PLX_DMPBAM_WDELAY_16    (BIT(14) * 3)
 262#define PLX_DMPBAM_WDELAY_MASK  GENMASK(15, 14)
 263/* Remap of Local-to-PCI Space Into PCI Address Space */
 264#define PLX_DMPBAM_REMAP_MASK   GENMASK(31, 16)
 265
 266/* PCI Configuration Address Register for Direct Master to PCI IO/CFG */
 267#define PLX_REG_DMCFGA          0x002c
 268
 269/* Congiguration Type */
 270#define PLX_DMCFGA_TYPE0        (BIT(0) * 0)
 271#define PLX_DMCFGA_TYPE1        (BIT(0) * 1)
 272#define PLX_DMCFGA_TYPE_MASK    GENMASK(1, 0)
 273/* Register Number */
 274#define PLX_DMCFGA_REGNUM(x)    (BIT(2) * ((x) & 0x3f))
 275#define PLX_DMCFGA_REGNUM_MASK  GENMASK(7, 2)
 276#define PLX_DMCFGA_TO_REGNUM(r) (((r) & PLX_DMCFGA_REGNUM_MASK) >> 2)
 277/* Function Number */
 278#define PLX_DMCFGA_FUNCNUM(x)   (BIT(8) * ((x) & 0x7))
 279#define PLX_DMCFGA_FUNCNUM_MASK GENMASK(10, 8)
 280#define PLX_DMCFGA_TO_FUNCNUM(r) (((r) & PLX_DMCFGA_FUNCNUM_MASK) >> 8)
 281/* Device Number */
 282#define PLX_DMCFGA_DEVNUM(x)    (BIT(11) * ((x) & 0x1f))
 283#define PLX_DMCFGA_DEVNUM_MASK  GENMASK(15, 11)
 284#define PLX_DMCFGA_TO_DEVNUM(r) (((r) & PLX_DMCFGA_DEVNUM_MASK) >> 11)
 285/* Bus Number */
 286#define PLX_DMCFGA_BUSNUM(x)    (BIT(16) * ((x) & 0xff))
 287#define PLX_DMCFGA_BUSNUM_MASK  GENMASK(23, 16)
 288#define PLX_DMCFGA_TO_BUSNUM(r) (((r) & PLX_DMCFGA_BUSNUM_MASK) >> 16)
 289/* Configuration Enable */
 290#define PLX_DMCFGA_CONFIGEN     BIT(31)
 291
 292/*
 293 * Mailbox Register N (N <= 7)
 294 *
 295 * Note that if the I2O feature is enabled (QSR[0] is set), Mailbox Register 0
 296 * is replaced by the Inbound Queue Port, and Mailbox Register 1 is replaced
 297 * by the Outbound Queue Port.  However, Mailbox Register 0 and 1 are always
 298 * accessible at alternative offsets if the I2O feature is enabled.
 299 */
 300#define PLX_REG_MBOX(n)         (0x0040 + (n) * 4)
 301#define PLX_REG_MBOX0           PLX_REG_MBOX(0)
 302#define PLX_REG_MBOX1           PLX_REG_MBOX(1)
 303#define PLX_REG_MBOX2           PLX_REG_MBOX(2)
 304#define PLX_REG_MBOX3           PLX_REG_MBOX(3)
 305#define PLX_REG_MBOX4           PLX_REG_MBOX(4)
 306#define PLX_REG_MBOX5           PLX_REG_MBOX(5)
 307#define PLX_REG_MBOX6           PLX_REG_MBOX(6)
 308#define PLX_REG_MBOX7           PLX_REG_MBOX(7)
 309
 310/* Alternative offsets for Mailbox Registers 0 and 1 (in case I2O is enabled) */
 311#define PLX_REG_ALT_MBOX(n)     ((n) < 2 ? 0x0078 + (n) * 4 : PLX_REG_MBOX(n))
 312#define PLX_REG_ALT_MBOX0       PLX_REG_ALT_MBOX(0)
 313#define PLX_REG_ALT_MBOX1       PLX_REG_ALT_MBOX(1)
 314
 315/* PCI-to-Local Doorbell Register */
 316#define PLX_REG_P2LDBELL        0x0060
 317
 318/* Local-to-PCI Doorbell Register */
 319#define PLX_REG_L2PDBELL        0x0064
 320
 321/* Interrupt Control/Status Register */
 322#define PLX_REG_INTCSR          0x0068
 323
 324/* Enable Local Bus LSERR# when PCI Bus Target Abort or Master Abort occurs */
 325#define PLX_INTCSR_LSEABORTEN   BIT(0)
 326/* Enable Local Bus LSERR# when PCI parity error occurs */
 327#define PLX_INTCSR_LSEPARITYEN  BIT(1)
 328/* Generate PCI Bus SERR# when set to 1 */
 329#define PLX_INTCSR_GENSERR      BIT(2)
 330/* Mailbox Interrupt Enable (local bus interrupts on PCI write to MBOX0-3) */
 331#define PLX_INTCSR_MBIEN        BIT(3)
 332/* PCI Interrupt Enable */
 333#define PLX_INTCSR_PIEN         BIT(8)
 334/* PCI Doorbell Interrupt Enable */
 335#define PLX_INTCSR_PDBIEN       BIT(9)
 336/* PCI Abort Interrupt Enable */
 337#define PLX_INTCSR_PABORTIEN    BIT(10)
 338/* PCI Local Interrupt Enable */
 339#define PLX_INTCSR_PLIEN        BIT(11)
 340/* Retry Abort Enable (for diagnostic purposes only) */
 341#define PLX_INTCSR_RAEN         BIT(12)
 342/* PCI Doorbell Interrupt Active (read-only) */
 343#define PLX_INTCSR_PDBIA        BIT(13)
 344/* PCI Abort Interrupt Active (read-only) */
 345#define PLX_INTCSR_PABORTIA     BIT(14)
 346/* Local Interrupt (LINTi#) Active (read-only) */
 347#define PLX_INTCSR_PLIA         BIT(15)
 348/* Local Interrupt Output (LINTo#) Enable */
 349#define PLX_INTCSR_LIOEN        BIT(16)
 350/* Local Doorbell Interrupt Enable */
 351#define PLX_INTCSR_LDBIEN       BIT(17)
 352/* DMA Channel 0 Interrupt Enable */
 353#define PLX_INTCSR_DMA0IEN      BIT(18)
 354/* DMA Channel 1 Interrupt Enable */
 355#define PLX_INTCSR_DMA1IEN      BIT(19)
 356/* DMA Channel N Interrupt Enable (N <= 1) */
 357#define PLX_INTCSR_DMAIEN(n)    ((n) ? PLX_INTCSR_DMA1IEN : PLX_INTCSR_DMA0IEN)
 358/* Local Doorbell Interrupt Active (read-only) */
 359#define PLX_INTCSR_LDBIA        BIT(20)
 360/* DMA Channel 0 Interrupt Active (read-only) */
 361#define PLX_INTCSR_DMA0IA       BIT(21)
 362/* DMA Channel 1 Interrupt Active (read-only) */
 363#define PLX_INTCSR_DMA1IA       BIT(22)
 364/* DMA Channel N Interrupt Active (N <= 1) (read-only) */
 365#define PLX_INTCSR_DMAIA(n)     ((n) ? PLX_INTCSR_DMA1IA : PLX_INTCSR_DMA0IA)
 366/* BIST Interrupt Active (read-only) */
 367#define PLX_INTCSR_BISTIA       BIT(23)
 368/* Direct Master Not Bus Master During Master Or Target Abort (read-only) */
 369#define PLX_INTCSR_ABNOTDM      BIT(24)
 370/* DMA Channel 0 Not Bus Master During Master Or Target Abort (read-only) */
 371#define PLX_INTCSR_ABNOTDMA0    BIT(25)
 372/* DMA Channel 1 Not Bus Master During Master Or Target Abort (read-only) */
 373#define PLX_INTCSR_ABNOTDMA1    BIT(26)
 374/* DMA Channel N Not Bus Master During Master Or Target Abort (read-only) */
 375#define PLX_INTCSR_ABNOTDMA(n)  ((n) ? PLX_INTCSR_ABNOTDMA1 \
 376                                     : PLX_INTCSR_ABNOTDMA0)
 377/* Target Abort Not Generated After 256 Master Retries (read-only) */
 378#define PLX_INTCSR_ABNOTRETRY   BIT(27)
 379/* PCI Wrote Mailbox 0 (enabled if bit 3 set) (read-only) */
 380#define PLX_INTCSR_MB0IA        BIT(28)
 381/* PCI Wrote Mailbox 1 (enabled if bit 3 set) (read-only) */
 382#define PLX_INTCSR_MB1IA        BIT(29)
 383/* PCI Wrote Mailbox 2 (enabled if bit 3 set) (read-only) */
 384#define PLX_INTCSR_MB2IA        BIT(30)
 385/* PCI Wrote Mailbox 3 (enabled if bit 3 set) (read-only) */
 386#define PLX_INTCSR_MB3IA        BIT(31)
 387/* PCI Wrote Mailbox N (N <= 3) (enabled if bit 3 set) (read-only) */
 388#define PLX_INTCSR_MBIA(n)      BIT(28 + (n))
 389
 390/*
 391 * Serial EEPROM Control, PCI Command Codes, User I/O Control,
 392 * Init Control Register
 393 */
 394#define PLX_REG_CNTRL           0x006c
 395
 396/* PCI Read Command Code For DMA */
 397#define PLX_CNTRL_CCRDMA(x)     (BIT(0) * ((x) & 0xf))
 398#define PLX_CNTRL_CCRDMA_MASK   GENMASK(3, 0)
 399#define PLX_CNTRL_TO_CCRDMA(r)  ((r) & PLX_CNTRL_CCRDMA_MASK)
 400#define PLX_CNTRL_CCRDMA_NORMAL PLX_CNTRL_CCRDMA(14)    /* value after reset */
 401/* PCI Write Command Code For DMA 0 */
 402#define PLX_CNTRL_CCWDMA(x)     (BIT(4) * ((x) & 0xf))
 403#define PLX_CNTRL_CCWDMA_MASK   GENMASK(7, 4)
 404#define PLX_CNTRL_TO_CCWDMA(r)  (((r) & PLX_CNTRL_CCWDMA_MASK) >> 4)
 405#define PLX_CNTRL_CCWDMA_NORMAL PLX_CNTRL_CCWDMA(7)     /* value after reset */
 406/* PCI Memory Read Command Code For Direct Master */
 407#define PLX_CNTRL_CCRDM(x)      (BIT(8) * ((x) & 0xf))
 408#define PLX_CNTRL_CCRDM_MASK    GENMASK(11, 8)
 409#define PLX_CNTRL_TO_CCRDM(r)   (((r) & PLX_CNTRL_CCRDM_MASK) >> 8)
 410#define PLX_CNTRL_CCRDM_NORMAL  PLX_CNTRL_CCRDM(6)      /* value after reset */
 411/* PCI Memory Write Command Code For Direct Master */
 412#define PLX_CNTRL_CCWDM(x)      (BIT(12) * ((x) & 0xf))
 413#define PLX_CNTRL_CCWDM_MASK    GENMASK(15, 12)
 414#define PLX_CNTRL_TO_CCWDM(r)   (((r) & PLX_CNTRL_CCWDM_MASK) >> 12)
 415#define PLX_CNTRL_CCWDM_NORMAL  PLX_CNTRL_CCWDM(7)      /* value after reset */
 416/* General Purpose Output (USERO) */
 417#define PLX_CNTRL_USERO         BIT(16)
 418/* General Purpose Input (USERI) (read-only) */
 419#define PLX_CNTRL_USERI         BIT(17)
 420/* Serial EEPROM Clock Output (EESK) */
 421#define PLX_CNTRL_EESK          BIT(24)
 422/* Serial EEPROM Chip Select Output (EECS) */
 423#define PLX_CNTRL_EECS          BIT(25)
 424/* Serial EEPROM Data Write Bit (EEDI (sic)) */
 425#define PLX_CNTRL_EEWB          BIT(26)
 426/* Serial EEPROM Data Read Bit (EEDO (sic)) (read-only) */
 427#define PLX_CNTRL_EERB          BIT(27)
 428/* Serial EEPROM Present (read-only) */
 429#define PLX_CNTRL_EEPRESENT     BIT(28)
 430/* Reload Configuration Registers from EEPROM */
 431#define PLX_CNTRL_EERELOAD      BIT(29)
 432/* PCI Adapter Software Reset (asserts LRESETo#) */
 433#define PLX_CNTRL_RESET         BIT(30)
 434/* Local Init Status (read-only) */
 435#define PLX_CNTRL_INITDONE      BIT(31)
 436/*
 437 * Combined command code stuff for convenience.
 438 */
 439#define PLX_CNTRL_CC_MASK       \
 440        (PLX_CNTRL_CCRDMA_MASK | PLX_CNTRL_CCWDMA_MASK | \
 441         PLX_CNTRL_CCRDM_MASK | PLX_CNTRL_CCWDM_MASK)
 442#define PLX_CNTRL_CC_NORMAL     \
 443        (PLX_CNTRL_CCRDMA_NORMAL | PLX_CNTRL_CCWDMA_NORMAL | \
 444         PLX_CNTRL_CCRDM_NORMAL | PLX_CNTRL_CCWDM_NORMAL) /* val after reset */
 445
 446/* PCI Permanent Configuration ID Register (hard-coded PLX vendor and device) */
 447#define PLX_REG_PCIHIDR         0x0070
 448
 449/* Hard-coded ID for PLX PCI 9080 */
 450#define PLX_PCIHIDR_9080        0x908010b5
 451
 452/* PCI Permanent Revision ID Register (hard-coded silicon revision) (8-bit). */
 453#define PLX_REG_PCIHREV         0x0074
 454
 455/* DMA Channel N Mode Register (N <= 1) */
 456#define PLX_REG_DMAMODE(n)      ((n) ? PLX_REG_DMAMODE1 : PLX_REG_DMAMODE0)
 457#define PLX_REG_DMAMODE0        0x0080
 458#define PLX_REG_DMAMODE1        0x0094
 459
 460/* Local Bus Width */
 461#define PLX_DMAMODE_WIDTH_8     (BIT(0) * 0)    /* 8 bits wide */
 462#define PLX_DMAMODE_WIDTH_16    (BIT(0) * 1)    /* 16 bits wide */
 463#define PLX_DMAMODE_WIDTH_32    (BIT(0) * 2)    /* 32 bits wide */
 464#define PLX_DMAMODE_WIDTH_32A   (BIT(0) * 3)    /* 32 bits wide */
 465#define PLX_DMAMODE_WIDTH_MASK  GENMASK(1, 0)
 466/* Internal Wait States */
 467#define PLX_DMAMODE_IWS(x)      (BIT(2) * ((x) & 0xf))
 468#define PLX_DMAMODE_IWS_MASK    GENMASK(5, 2)
 469#define PLX_DMAMODE_TO_IWS(r)   (((r) & PLX_DMAMODE_IWS_MASK) >> 2)
 470/* Ready Input Enable */
 471#define PLX_DMAMODE_READYIEN    BIT(6)
 472/* BTERM# Input Enable */
 473#define PLX_DMAMODE_BTERMIEN    BIT(7)
 474/* Local Burst Enable */
 475#define PLX_DMAMODE_BURSTEN     BIT(8)
 476/* Chaining Enable */
 477#define PLX_DMAMODE_CHAINEN     BIT(9)
 478/* Done Interrupt Enable */
 479#define PLX_DMAMODE_DONEIEN     BIT(10)
 480/* Hold Local Address Constant */
 481#define PLX_DMAMODE_LACONST     BIT(11)
 482/* Demand Mode */
 483#define PLX_DMAMODE_DEMAND      BIT(12)
 484/* Write And Invalidate Mode */
 485#define PLX_DMAMODE_WINVALIDATE BIT(13)
 486/* DMA EOT Enable - enables EOT0# or EOT1# input pin */
 487#define PLX_DMAMODE_EOTEN       BIT(14)
 488/* DMA Stop Data Transfer Mode - 0:BLAST; 1:EOT asserted or DREQ deasserted */
 489#define PLX_DMAMODE_STOP        BIT(15)
 490/* DMA Clear Count Mode - count in descriptor cleared on completion */
 491#define PLX_DMAMODE_CLRCOUNT    BIT(16)
 492/* DMA Channel Interrupt Select - 0:local bus interrupt; 1:PCI interrupt */
 493#define PLX_DMAMODE_INTRPCI     BIT(17)
 494
 495/* DMA Channel N PCI Address Register (N <= 1) */
 496#define PLX_REG_DMAPADR(n)      ((n) ? PLX_REG_DMAPADR1 : PLX_REG_DMAPADR0)
 497#define PLX_REG_DMAPADR0        0x0084
 498#define PLX_REG_DMAPADR1        0x0098
 499
 500/* DMA Channel N Local Address Register (N <= 1) */
 501#define PLX_REG_DMALADR(n)      ((n) ? PLX_REG_DMALADR1 : PLX_REG_DMALADR0)
 502#define PLX_REG_DMALADR0        0x0088
 503#define PLX_REG_DMALADR1        0x009c
 504
 505/* DMA Channel N Transfer Size (Bytes) Register (N <= 1) (first 23 bits) */
 506#define PLX_REG_DMASIZ(n)       ((n) ? PLX_REG_DMASIZ1 : PLX_REG_DMASIZ0)
 507#define PLX_REG_DMASIZ0         0x008c
 508#define PLX_REG_DMASIZ1         0x00a0
 509
 510/* DMA Channel N Descriptor Pointer Register (N <= 1) */
 511#define PLX_REG_DMADPR(n)       ((n) ? PLX_REG_DMADPR1 : PLX_REG_DMADPR0)
 512#define PLX_REG_DMADPR0         0x0090
 513#define PLX_REG_DMADPR1         0x00a4
 514
 515/* Descriptor Located In PCI Address Space (not local address space) */
 516#define PLX_DMADPR_DESCPCI      BIT(0)
 517/* End Of Chain */
 518#define PLX_DMADPR_CHAINEND     BIT(1)
 519/* Interrupt After Terminal Count */
 520#define PLX_DMADPR_TCINTR       BIT(2)
 521/* Direction Of Transfer Local Bus To PCI (not PCI to local) */
 522#define PLX_DMADPR_XFERL2P      BIT(3)
 523/* Next Descriptor Address Bits 31:4 (16 byte boundary) */
 524#define PLX_DMADPR_NEXT_MASK    GENMASK(31, 4)
 525
 526/* DMA Channel N Command/Status Register (N <= 1) (8-bit) */
 527#define PLX_REG_DMACSR(n)       ((n) ? PLX_REG_DMACSR1 : PLX_REG_DMACSR0)
 528#define PLX_REG_DMACSR0         0x00a8
 529#define PLX_REG_DMACSR1         0x00a9
 530
 531/* Channel Enable */
 532#define PLX_DMACSR_ENABLE       BIT(0)
 533/* Channel Start - write 1 to start transfer (write-only) */
 534#define PLX_DMACSR_START        BIT(1)
 535/* Channel Abort - write 1 to abort transfer (write-only) */
 536#define PLX_DMACSR_ABORT        BIT(2)
 537/* Clear Interrupt - write 1 to clear DMA Channel Interrupt (write-only) */
 538#define PLX_DMACSR_CLEARINTR    BIT(3)
 539/* Channel Done - transfer complete/inactive (read-only) */
 540#define PLX_DMACSR_DONE         BIT(4)
 541
 542/* DMA Threshold Register */
 543#define PLX_REG_DMATHR          0x00b0
 544
 545/*
 546 * DMA Threshold constraints:
 547 * (C0PLAF + 1) + (C0PLAE + 1) <= 32
 548 * (C0LPAF + 1) + (C0LPAE + 1) <= 32
 549 * (C1PLAF + 1) + (C1PLAE + 1) <= 16
 550 * (C1LPAF + 1) + (C1LPAE + 1) <= 16
 551 */
 552
 553/* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
 554#define PLX_DMATHR_C0PLAF(x)    (BIT(0) * ((x) & 0xf))
 555#define PLX_DMATHR_C0PLAF_MASK  GENMASK(3, 0)
 556#define PLX_DMATHR_TO_C0PLAF(r) ((r) & PLX_DMATHR_C0PLAF_MASK)
 557/* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
 558#define PLX_DMATHR_C0LPAE(x)    (BIT(4) * ((x) & 0xf))
 559#define PLX_DMATHR_C0LPAE_MASK  GENMASK(7, 4)
 560#define PLX_DMATHR_TO_C0LPAE(r) (((r) & PLX_DMATHR_C0LPAE_MASK) >> 4)
 561/* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
 562#define PLX_DMATHR_C0LPAF(x)    (BIT(8) * ((x) & 0xf))
 563#define PLX_DMATHR_C0LPAF_MASK  GENMASK(11, 8)
 564#define PLX_DMATHR_TO_C0LPAF(r) (((r) & PLX_DMATHR_C0LPAF_MASK) >> 8)
 565/* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
 566#define PLX_DMATHR_C0PLAE(x)    (BIT(12) * ((x) & 0xf))
 567#define PLX_DMATHR_C0PLAE_MASK  GENMASK(15, 12)
 568#define PLX_DMATHR_TO_C0PLAE(r) (((r) & PLX_DMATHR_C0PLAE_MASK) >> 12)
 569/* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
 570#define PLX_DMATHR_C1PLAF(x)    (BIT(16) * ((x) & 0xf))
 571#define PLX_DMATHR_C1PLAF_MASK  GENMASK(19, 16)
 572#define PLX_DMATHR_TO_C1PLAF(r) (((r) & PLX_DMATHR_C1PLAF_MASK) >> 16)
 573/* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
 574#define PLX_DMATHR_C1LPAE(x)    (BIT(20) * ((x) & 0xf))
 575#define PLX_DMATHR_C1LPAE_MASK  GENMASK(23, 20)
 576#define PLX_DMATHR_TO_C1LPAE(r) (((r) & PLX_DMATHR_C1LPAE_MASK) >> 20)
 577/* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
 578#define PLX_DMATHR_C1LPAF(x)    (BIT(24) * ((x) & 0xf))
 579#define PLX_DMATHR_C1LPAF_MASK  GENMASK(27, 24)
 580#define PLX_DMATHR_TO_C1LPAF(r) (((r) & PLX_DMATHR_C1LPAF_MASK) >> 24)
 581/* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
 582#define PLX_DMATHR_C1PLAE(x)    (BIT(28) * ((x) & 0xf))
 583#define PLX_DMATHR_C1PLAE_MASK  GENMASK(31, 28)
 584#define PLX_DMATHR_TO_C1PLAE(r) (((r) & PLX_DMATHR_C1PLAE_MASK) >> 28)
 585
 586/*
 587 * Messaging Queue Registers OPLFIS, OPLFIM, IQP, OQP, MQCR, QBAR, IFHPR,
 588 * IFTPR, IPHPR, IPTPR, OFHPR, OFTPR, OPHPR, OPTPR, and QSR have been omitted.
 589 * They are used by the I2O feature.  (IQP and OQP occupy the usual offsets of
 590 * the MBOX0 and MBOX1 registers if the I2O feature is enabled, but MBOX0 and
 591 * MBOX1 are accessible via alternative offsets.
 592 */
 593
 594/* Queue Status/Control Register */
 595#define PLX_REG_QSR             0x00e8
 596
 597/* Value of QSR after reset - disables I2O feature completely. */
 598#define PLX_QSR_VALUE_AFTER_RESET       0x00000050
 599
 600/*
 601 * Accesses near the end of memory can cause the PLX chip
 602 * to pre-fetch data off of end-of-ram.  Limit the size of
 603 * memory so host-side accesses cannot occur.
 604 */
 605
 606#define PLX_PREFETCH   32
 607
 608/**
 609 * plx9080_abort_dma - Abort a PLX PCI 9080 DMA transfer
 610 * @iobase:     Remapped base address of configuration registers.
 611 * @channel:    DMA channel number (0 or 1).
 612 *
 613 * Aborts the DMA transfer on the channel, which must have been enabled
 614 * and started beforehand.
 615 *
 616 * Return:
 617 *      %0 on success.
 618 *      -%ETIMEDOUT if timed out waiting for abort to complete.
 619 */
 620static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
 621{
 622        void __iomem *dma_cs_addr;
 623        u8 dma_status;
 624        const int timeout = 10000;
 625        unsigned int i;
 626
 627        dma_cs_addr = iobase + PLX_REG_DMACSR(channel);
 628
 629        /* abort dma transfer if necessary */
 630        dma_status = readb(dma_cs_addr);
 631        if ((dma_status & PLX_DMACSR_ENABLE) == 0)
 632                return 0;
 633
 634        /* wait to make sure done bit is zero */
 635        for (i = 0; (dma_status & PLX_DMACSR_DONE) && i < timeout; i++) {
 636                udelay(1);
 637                dma_status = readb(dma_cs_addr);
 638        }
 639        if (i == timeout)
 640                return -ETIMEDOUT;
 641
 642        /* disable and abort channel */
 643        writeb(PLX_DMACSR_ABORT, dma_cs_addr);
 644        /* wait for dma done bit */
 645        dma_status = readb(dma_cs_addr);
 646        for (i = 0; (dma_status & PLX_DMACSR_DONE) == 0 && i < timeout; i++) {
 647                udelay(1);
 648                dma_status = readb(dma_cs_addr);
 649        }
 650        if (i == timeout)
 651                return -ETIMEDOUT;
 652
 653        return 0;
 654}
 655
 656#endif /* __COMEDI_PLX9080_H */
 657