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5
6
7#ifndef _QLGE_H_
8#define _QLGE_H_
9
10#include <linux/interrupt.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/rtnetlink.h>
14#include <linux/if_vlan.h>
15
16
17
18
19#define DRV_NAME "qlge"
20#define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
21#define DRV_VERSION "1.00.00.35"
22
23#define WQ_ADDR_ALIGN 0x3
24
25#define QLGE_VENDOR_ID 0x1077
26#define QLGE_DEVICE_ID_8012 0x8012
27#define QLGE_DEVICE_ID_8000 0x8000
28#define QLGE_MEZZ_SSYS_ID_068 0x0068
29#define QLGE_MEZZ_SSYS_ID_180 0x0180
30#define MAX_CPUS 8
31#define MAX_TX_RINGS MAX_CPUS
32#define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
33
34#define NUM_TX_RING_ENTRIES 256
35#define NUM_RX_RING_ENTRIES 256
36
37
38
39
40#define QLGE_BQ_SHIFT 9
41#define QLGE_BQ_LEN BIT(QLGE_BQ_SHIFT)
42#define QLGE_BQ_SIZE (QLGE_BQ_LEN * sizeof(__le64))
43
44#define DB_PAGE_SIZE 4096
45
46
47
48
49#define MAX_DB_PAGES_PER_BQ(x) \
50 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
51 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
52
53#define RX_RING_SHADOW_SPACE (sizeof(u64) + \
54 MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(QLGE_BQ_LEN) * sizeof(u64))
56#define LARGE_BUFFER_MAX_SIZE 8192
57#define LARGE_BUFFER_MIN_SIZE 2048
58
59#define MAX_CQ 128
60#define DFLT_COALESCE_WAIT 100
61#define MAX_INTER_FRAME_WAIT 10
62#define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
63#define UDELAY_COUNT 3
64#define UDELAY_DELAY 100
65
66
67#define TX_DESC_PER_IOCB 8
68
69#if ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2) > 0
70#define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
71#else
72#define TX_DESC_PER_OAL 0
73#endif
74
75
76
77
78
79
80#define LSW(x) ((u16)(x))
81#define MSW(x) ((u16)((u32)(x) >> 16))
82#define LSD(x) ((u32)((u64)(x)))
83#define MSD(x) ((u32)((((u64)(x)) >> 32)))
84
85
86
87
88#define QLGE_FIT16(value) ((u16)(value))
89
90
91
92
93
94enum {
95 MPI_TEST_FUNC_PORT_CFG = 0x1002,
96 MPI_TEST_FUNC_PRB_CTL = 0x100e,
97 MPI_TEST_FUNC_PRB_EN = 0x18a20000,
98 MPI_TEST_FUNC_RST_STS = 0x100a,
99 MPI_TEST_FUNC_RST_FRC = 0x00000003,
100 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
101 MPI_TEST_NIC1_FUNCTION_ENABLE = (1 << 0),
102 MPI_TEST_NIC1_FUNCTION_MASK = 0x0000000e,
103 MPI_TEST_NIC1_FUNC_SHIFT = 1,
104 MPI_TEST_NIC2_FUNCTION_ENABLE = (1 << 4),
105 MPI_TEST_NIC2_FUNCTION_MASK = 0x000000e0,
106 MPI_TEST_NIC2_FUNC_SHIFT = 5,
107 MPI_TEST_FC1_FUNCTION_ENABLE = (1 << 8),
108 MPI_TEST_FC1_FUNCTION_MASK = 0x00000e00,
109 MPI_TEST_FC1_FUNCTION_SHIFT = 9,
110 MPI_TEST_FC2_FUNCTION_ENABLE = (1 << 12),
111 MPI_TEST_FC2_FUNCTION_MASK = 0x0000e000,
112 MPI_TEST_FC2_FUNCTION_SHIFT = 13,
113
114 MPI_NIC_READ = 0x00000000,
115 MPI_NIC_REG_BLOCK = 0x00020000,
116 MPI_NIC_FUNCTION_SHIFT = 6,
117};
118
119
120
121
122enum {
123
124
125 MAILBOX_COUNT = 16,
126 MAILBOX_TIMEOUT = 5,
127
128 PROC_ADDR_RDY = (1 << 31),
129 PROC_ADDR_R = (1 << 30),
130 PROC_ADDR_ERR = (1 << 29),
131 PROC_ADDR_DA = (1 << 28),
132 PROC_ADDR_FUNC0_MBI = 0x00001180,
133 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
134 PROC_ADDR_FUNC0_CTL = 0x000011a1,
135 PROC_ADDR_FUNC2_MBI = 0x00001280,
136 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
137 PROC_ADDR_FUNC2_CTL = 0x000012a1,
138 PROC_ADDR_MPI_RISC = 0x00000000,
139 PROC_ADDR_MDE = 0x00010000,
140 PROC_ADDR_REGBLOCK = 0x00020000,
141 PROC_ADDR_RISC_REG = 0x00030000,
142};
143
144
145
146
147enum {
148 SYS_EFE = (1 << 0),
149 SYS_FAE = (1 << 1),
150 SYS_MDC = (1 << 2),
151 SYS_DST = (1 << 3),
152 SYS_DWC = (1 << 4),
153 SYS_EVW = (1 << 5),
154 SYS_OMP_DLY_MASK = 0x3f000000,
155
156
157
158 SYS_ODI = (1 << 14),
159};
160
161
162
163
164enum {
165 RST_FO_TFO = (1 << 0),
166 RST_FO_RR_MASK = 0x00060000,
167 RST_FO_RR_CQ_CAM = 0x00000000,
168 RST_FO_RR_DROP = 0x00000002,
169 RST_FO_RR_DQ = 0x00000004,
170 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
171 RST_FO_FRB = (1 << 12),
172 RST_FO_MOP = (1 << 13),
173 RST_FO_REG = (1 << 14),
174 RST_FO_FR = (1 << 15),
175};
176
177
178
179
180enum {
181 FSC_DBRST_MASK = 0x00070000,
182 FSC_DBRST_256 = 0x00000000,
183 FSC_DBRST_512 = 0x00000001,
184 FSC_DBRST_768 = 0x00000002,
185 FSC_DBRST_1024 = 0x00000003,
186 FSC_DBL_MASK = 0x00180000,
187 FSC_DBL_DBRST = 0x00000000,
188 FSC_DBL_MAX_PLD = 0x00000008,
189 FSC_DBL_MAX_BRST = 0x00000010,
190 FSC_DBL_128_BYTES = 0x00000018,
191 FSC_EC = (1 << 5),
192 FSC_EPC_MASK = 0x00c00000,
193 FSC_EPC_INBOUND = (1 << 6),
194 FSC_EPC_OUTBOUND = (1 << 7),
195 FSC_VM_PAGESIZE_MASK = 0x07000000,
196 FSC_VM_PAGE_2K = 0x00000100,
197 FSC_VM_PAGE_4K = 0x00000200,
198 FSC_VM_PAGE_8K = 0x00000300,
199 FSC_VM_PAGE_64K = 0x00000600,
200 FSC_SH = (1 << 11),
201 FSC_DSB = (1 << 12),
202 FSC_STE = (1 << 13),
203 FSC_FE = (1 << 15),
204};
205
206
207
208
209enum {
210 CSR_ERR_STS_MASK = 0x0000003f,
211
212
213
214 CSR_RR = (1 << 8),
215 CSR_HRI = (1 << 9),
216 CSR_RP = (1 << 10),
217 CSR_CMD_PARM_SHIFT = 22,
218 CSR_CMD_NOP = 0x00000000,
219 CSR_CMD_SET_RST = 0x10000000,
220 CSR_CMD_CLR_RST = 0x20000000,
221 CSR_CMD_SET_PAUSE = 0x30000000,
222 CSR_CMD_CLR_PAUSE = 0x40000000,
223 CSR_CMD_SET_H2R_INT = 0x50000000,
224 CSR_CMD_CLR_H2R_INT = 0x60000000,
225 CSR_CMD_PAR_EN = 0x70000000,
226 CSR_CMD_SET_BAD_PAR = 0x80000000,
227 CSR_CMD_CLR_BAD_PAR = 0x90000000,
228 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
229};
230
231
232
233
234enum {
235 CFG_LRQ = (1 << 0),
236 CFG_DRQ = (1 << 1),
237 CFG_LR = (1 << 2),
238 CFG_DR = (1 << 3),
239 CFG_LE = (1 << 5),
240 CFG_LCQ = (1 << 6),
241 CFG_DCQ = (1 << 7),
242 CFG_Q_SHIFT = 8,
243 CFG_Q_MASK = 0x7f000000,
244};
245
246
247
248
249enum {
250 STS_FE = (1 << 0),
251 STS_PI = (1 << 1),
252 STS_PL0 = (1 << 2),
253 STS_PL1 = (1 << 3),
254 STS_PI0 = (1 << 4),
255 STS_PI1 = (1 << 5),
256 STS_FUNC_ID_MASK = 0x000000c0,
257 STS_FUNC_ID_SHIFT = 6,
258 STS_F0E = (1 << 8),
259 STS_F1E = (1 << 9),
260 STS_F2E = (1 << 10),
261 STS_F3E = (1 << 11),
262 STS_NFE = (1 << 12),
263};
264
265
266
267
268enum {
269 INTR_EN_INTR_MASK = 0x007f0000,
270 INTR_EN_TYPE_MASK = 0x03000000,
271 INTR_EN_TYPE_ENABLE = 0x00000100,
272 INTR_EN_TYPE_DISABLE = 0x00000200,
273 INTR_EN_TYPE_READ = 0x00000300,
274 INTR_EN_IHD = (1 << 13),
275 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
276 INTR_EN_EI = (1 << 14),
277 INTR_EN_EN = (1 << 15),
278};
279
280
281
282
283enum {
284 INTR_MASK_PI = (1 << 0),
285 INTR_MASK_HL0 = (1 << 1),
286 INTR_MASK_LH0 = (1 << 2),
287 INTR_MASK_HL1 = (1 << 3),
288 INTR_MASK_LH1 = (1 << 4),
289 INTR_MASK_SE = (1 << 5),
290 INTR_MASK_LSC = (1 << 6),
291 INTR_MASK_MC = (1 << 7),
292 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
293};
294
295
296
297
298enum {
299 REV_ID_MASK = 0x0000000f,
300 REV_ID_NICROLL_SHIFT = 0,
301 REV_ID_NICREV_SHIFT = 4,
302 REV_ID_XGROLL_SHIFT = 8,
303 REV_ID_XGREV_SHIFT = 12,
304 REV_ID_CHIPREV_SHIFT = 28,
305};
306
307
308
309
310enum {
311 FRC_ECC_ERR_VW = (1 << 12),
312 FRC_ECC_ERR_VB = (1 << 13),
313 FRC_ECC_ERR_NI = (1 << 14),
314 FRC_ECC_ERR_NO = (1 << 15),
315 FRC_ECC_PFE_SHIFT = 16,
316 FRC_ECC_ERR_DO = (1 << 18),
317 FRC_ECC_P14 = (1 << 19),
318};
319
320
321
322
323enum {
324 ERR_STS_NOF = (1 << 0),
325 ERR_STS_NIF = (1 << 1),
326 ERR_STS_DRP = (1 << 2),
327 ERR_STS_XGP = (1 << 3),
328 ERR_STS_FOU = (1 << 4),
329 ERR_STS_FOC = (1 << 5),
330 ERR_STS_FOF = (1 << 6),
331 ERR_STS_FIU = (1 << 7),
332 ERR_STS_FIC = (1 << 8),
333 ERR_STS_FIF = (1 << 9),
334 ERR_STS_MOF = (1 << 10),
335 ERR_STS_TA = (1 << 11),
336 ERR_STS_MA = (1 << 12),
337 ERR_STS_MPE = (1 << 13),
338 ERR_STS_SCE = (1 << 14),
339 ERR_STS_STE = (1 << 15),
340 ERR_STS_FOW = (1 << 16),
341 ERR_STS_UE = (1 << 17),
342 ERR_STS_MCH = (1 << 26),
343 ERR_STS_LOC_SHIFT = 27,
344};
345
346
347
348
349enum {
350 RAM_DBG_ADDR_FW = (1 << 30),
351 RAM_DBG_ADDR_FR = (1 << 31),
352};
353
354
355
356
357enum {
358
359
360
361
362 SEM_CLEAR = 0,
363 SEM_SET = 1,
364 SEM_FORCE = 3,
365 SEM_XGMAC0_SHIFT = 0,
366 SEM_XGMAC1_SHIFT = 2,
367 SEM_ICB_SHIFT = 4,
368 SEM_MAC_ADDR_SHIFT = 6,
369 SEM_FLASH_SHIFT = 8,
370 SEM_PROBE_SHIFT = 10,
371 SEM_RT_IDX_SHIFT = 12,
372 SEM_PROC_REG_SHIFT = 14,
373 SEM_XGMAC0_MASK = 0x00030000,
374 SEM_XGMAC1_MASK = 0x000c0000,
375 SEM_ICB_MASK = 0x00300000,
376 SEM_MAC_ADDR_MASK = 0x00c00000,
377 SEM_FLASH_MASK = 0x03000000,
378 SEM_PROBE_MASK = 0x0c000000,
379 SEM_RT_IDX_MASK = 0x30000000,
380 SEM_PROC_REG_MASK = 0xc0000000,
381};
382
383
384
385
386enum {
387 XGMAC_ADDR_RDY = (1 << 31),
388 XGMAC_ADDR_R = (1 << 30),
389 XGMAC_ADDR_XME = (1 << 29),
390
391
392 PAUSE_SRC_LO = 0x00000100,
393 PAUSE_SRC_HI = 0x00000104,
394 GLOBAL_CFG = 0x00000108,
395 GLOBAL_CFG_RESET = (1 << 0),
396 GLOBAL_CFG_JUMBO = (1 << 6),
397 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
398 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
399 TX_CFG = 0x0000010c,
400 TX_CFG_RESET = (1 << 0),
401 TX_CFG_EN = (1 << 1),
402 TX_CFG_PREAM = (1 << 2),
403 RX_CFG = 0x00000110,
404 RX_CFG_RESET = (1 << 0),
405 RX_CFG_EN = (1 << 1),
406 RX_CFG_PREAM = (1 << 2),
407 FLOW_CTL = 0x0000011c,
408 PAUSE_OPCODE = 0x00000120,
409 PAUSE_TIMER = 0x00000124,
410 PAUSE_FRM_DEST_LO = 0x00000128,
411 PAUSE_FRM_DEST_HI = 0x0000012c,
412 MAC_TX_PARAMS = 0x00000134,
413 MAC_TX_PARAMS_JUMBO = (1 << 31),
414 MAC_TX_PARAMS_SIZE_SHIFT = 16,
415 MAC_RX_PARAMS = 0x00000138,
416 MAC_SYS_INT = 0x00000144,
417 MAC_SYS_INT_MASK = 0x00000148,
418 MAC_MGMT_INT = 0x0000014c,
419 MAC_MGMT_IN_MASK = 0x00000150,
420 EXT_ARB_MODE = 0x000001fc,
421
422
423 TX_PKTS = 0x00000200,
424 TX_BYTES = 0x00000208,
425 TX_MCAST_PKTS = 0x00000210,
426 TX_BCAST_PKTS = 0x00000218,
427 TX_UCAST_PKTS = 0x00000220,
428 TX_CTL_PKTS = 0x00000228,
429 TX_PAUSE_PKTS = 0x00000230,
430 TX_64_PKT = 0x00000238,
431 TX_65_TO_127_PKT = 0x00000240,
432 TX_128_TO_255_PKT = 0x00000248,
433 TX_256_511_PKT = 0x00000250,
434 TX_512_TO_1023_PKT = 0x00000258,
435 TX_1024_TO_1518_PKT = 0x00000260,
436 TX_1519_TO_MAX_PKT = 0x00000268,
437 TX_UNDERSIZE_PKT = 0x00000270,
438 TX_OVERSIZE_PKT = 0x00000278,
439
440
441 RX_HALF_FULL_DET = 0x000002a0,
442 TX_HALF_FULL_DET = 0x000002a4,
443 RX_OVERFLOW_DET = 0x000002a8,
444 TX_OVERFLOW_DET = 0x000002ac,
445 RX_HALF_FULL_MASK = 0x000002b0,
446 TX_HALF_FULL_MASK = 0x000002b4,
447 RX_OVERFLOW_MASK = 0x000002b8,
448 TX_OVERFLOW_MASK = 0x000002bc,
449 STAT_CNT_CTL = 0x000002c0,
450 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
451 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
452 AUX_RX_HALF_FULL_DET = 0x000002d0,
453 AUX_TX_HALF_FULL_DET = 0x000002d4,
454 AUX_RX_OVERFLOW_DET = 0x000002d8,
455 AUX_TX_OVERFLOW_DET = 0x000002dc,
456 AUX_RX_HALF_FULL_MASK = 0x000002f0,
457 AUX_TX_HALF_FULL_MASK = 0x000002f4,
458 AUX_RX_OVERFLOW_MASK = 0x000002f8,
459 AUX_TX_OVERFLOW_MASK = 0x000002fc,
460
461
462 RX_BYTES = 0x00000300,
463 RX_BYTES_OK = 0x00000308,
464 RX_PKTS = 0x00000310,
465 RX_PKTS_OK = 0x00000318,
466 RX_BCAST_PKTS = 0x00000320,
467 RX_MCAST_PKTS = 0x00000328,
468 RX_UCAST_PKTS = 0x00000330,
469 RX_UNDERSIZE_PKTS = 0x00000338,
470 RX_OVERSIZE_PKTS = 0x00000340,
471 RX_JABBER_PKTS = 0x00000348,
472 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
473 RX_DROP_EVENTS = 0x00000358,
474 RX_FCERR_PKTS = 0x00000360,
475 RX_ALIGN_ERR = 0x00000368,
476 RX_SYMBOL_ERR = 0x00000370,
477 RX_MAC_ERR = 0x00000378,
478 RX_CTL_PKTS = 0x00000380,
479 RX_PAUSE_PKTS = 0x00000388,
480 RX_64_PKTS = 0x00000390,
481 RX_65_TO_127_PKTS = 0x00000398,
482 RX_128_255_PKTS = 0x000003a0,
483 RX_256_511_PKTS = 0x000003a8,
484 RX_512_TO_1023_PKTS = 0x000003b0,
485 RX_1024_TO_1518_PKTS = 0x000003b8,
486 RX_1519_TO_MAX_PKTS = 0x000003c0,
487 RX_LEN_ERR_PKTS = 0x000003c8,
488
489
490 MDIO_TX_DATA = 0x00000400,
491 MDIO_RX_DATA = 0x00000410,
492 MDIO_CMD = 0x00000420,
493 MDIO_PHY_ADDR = 0x00000430,
494 MDIO_PORT = 0x00000440,
495 MDIO_STATUS = 0x00000450,
496
497 XGMAC_REGISTER_END = 0x00000740,
498};
499
500
501
502
503enum {
504 ETS_QUEUE_SHIFT = 29,
505 ETS_REF = (1 << 26),
506 ETS_RS = (1 << 27),
507 ETS_P = (1 << 28),
508 ETS_FC_COS_SHIFT = 23,
509};
510
511
512
513
514enum {
515 FLASH_ADDR_RDY = (1 << 31),
516 FLASH_ADDR_R = (1 << 30),
517 FLASH_ADDR_ERR = (1 << 29),
518};
519
520
521
522
523enum {
524 CQ_STOP_QUEUE_MASK = (0x007f0000),
525 CQ_STOP_TYPE_MASK = (0x03000000),
526 CQ_STOP_TYPE_START = 0x00000100,
527 CQ_STOP_TYPE_STOP = 0x00000200,
528 CQ_STOP_TYPE_READ = 0x00000300,
529 CQ_STOP_EN = (1 << 15),
530};
531
532
533
534
535enum {
536 MAC_ADDR_IDX_SHIFT = 4,
537 MAC_ADDR_TYPE_SHIFT = 16,
538 MAC_ADDR_TYPE_COUNT = 10,
539 MAC_ADDR_TYPE_MASK = 0x000f0000,
540 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
541 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
542 MAC_ADDR_TYPE_VLAN = 0x00020000,
543 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
544 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
545 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
546 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
547 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
548 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
549 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
550 MAC_ADDR_ADR = (1 << 25),
551 MAC_ADDR_RS = (1 << 26),
552 MAC_ADDR_E = (1 << 27),
553 MAC_ADDR_MR = (1 << 30),
554 MAC_ADDR_MW = (1 << 31),
555 MAX_MULTICAST_ENTRIES = 32,
556
557
558
559
560 MAC_ADDR_MAX_CAM_ENTRIES = 512,
561 MAC_ADDR_MAX_CAM_WCOUNT = 3,
562 MAC_ADDR_MAX_MULTICAST_ENTRIES = 32,
563 MAC_ADDR_MAX_MULTICAST_WCOUNT = 2,
564 MAC_ADDR_MAX_VLAN_ENTRIES = 4096,
565 MAC_ADDR_MAX_VLAN_WCOUNT = 1,
566 MAC_ADDR_MAX_MCAST_FLTR_ENTRIES = 4096,
567 MAC_ADDR_MAX_MCAST_FLTR_WCOUNT = 1,
568 MAC_ADDR_MAX_FC_MAC_ENTRIES = 4,
569 MAC_ADDR_MAX_FC_MAC_WCOUNT = 2,
570 MAC_ADDR_MAX_MGMT_MAC_ENTRIES = 8,
571 MAC_ADDR_MAX_MGMT_MAC_WCOUNT = 2,
572 MAC_ADDR_MAX_MGMT_VLAN_ENTRIES = 16,
573 MAC_ADDR_MAX_MGMT_VLAN_WCOUNT = 1,
574 MAC_ADDR_MAX_MGMT_V4_ENTRIES = 4,
575 MAC_ADDR_MAX_MGMT_V4_WCOUNT = 1,
576 MAC_ADDR_MAX_MGMT_V6_ENTRIES = 4,
577 MAC_ADDR_MAX_MGMT_V6_WCOUNT = 4,
578 MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES = 4,
579 MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT = 1,
580};
581
582
583
584
585enum {
586 SPLT_HDR_EP = (1 << 31),
587};
588
589
590
591
592enum {
593 FC_RCV_CFG_ECT = (1 << 15),
594 FC_RCV_CFG_DFH = (1 << 20),
595 FC_RCV_CFG_DVF = (1 << 21),
596 FC_RCV_CFG_RCE = (1 << 27),
597 FC_RCV_CFG_RFE = (1 << 28),
598 FC_RCV_CFG_TEE = (1 << 29),
599 FC_RCV_CFG_TCE = (1 << 30),
600 FC_RCV_CFG_TFE = (1 << 31),
601};
602
603
604
605
606enum {
607 NIC_RCV_CFG_PPE = (1 << 0),
608 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
609 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
610 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
611 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
612 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
613 NIC_RCV_CFG_RV = (1 << 3),
614 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
615 NIC_RCV_CFG_DFQ_SHIFT = 8,
616 NIC_RCV_CFG_DFQ = 0,
617};
618
619
620
621
622enum {
623 MGMT_RCV_CFG_ARP = (1 << 0),
624 MGMT_RCV_CFG_DHC = (1 << 1),
625 MGMT_RCV_CFG_DHS = (1 << 2),
626 MGMT_RCV_CFG_NP = (1 << 3),
627 MGMT_RCV_CFG_I6N = (1 << 4),
628 MGMT_RCV_CFG_I6R = (1 << 5),
629 MGMT_RCV_CFG_DH6 = (1 << 6),
630 MGMT_RCV_CFG_UD1 = (1 << 7),
631 MGMT_RCV_CFG_UD0 = (1 << 8),
632 MGMT_RCV_CFG_BCT = (1 << 9),
633 MGMT_RCV_CFG_MCT = (1 << 10),
634 MGMT_RCV_CFG_DM = (1 << 11),
635 MGMT_RCV_CFG_RM = (1 << 12),
636 MGMT_RCV_CFG_STL = (1 << 13),
637 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
638 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
639 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
640 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
641 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
642};
643
644
645
646
647enum {
648 RT_IDX_IDX_SHIFT = 8,
649 RT_IDX_TYPE_MASK = 0x000f0000,
650 RT_IDX_TYPE_SHIFT = 16,
651 RT_IDX_TYPE_RT = 0x00000000,
652 RT_IDX_TYPE_RT_INV = 0x00010000,
653 RT_IDX_TYPE_NICQ = 0x00020000,
654 RT_IDX_TYPE_NICQ_INV = 0x00030000,
655 RT_IDX_DST_MASK = 0x00700000,
656 RT_IDX_DST_RSS = 0x00000000,
657 RT_IDX_DST_CAM_Q = 0x00100000,
658 RT_IDX_DST_COS_Q = 0x00200000,
659 RT_IDX_DST_DFLT_Q = 0x00300000,
660 RT_IDX_DST_DEST_Q = 0x00400000,
661 RT_IDX_RS = (1 << 26),
662 RT_IDX_E = (1 << 27),
663 RT_IDX_MR = (1 << 30),
664 RT_IDX_MW = (1 << 31),
665
666
667 RT_IDX_BCAST = (1 << 0),
668 RT_IDX_MCAST = (1 << 1),
669 RT_IDX_MCAST_MATCH = (1 << 2),
670 RT_IDX_MCAST_REG_MATCH = (1 << 3),
671 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
672 RT_IDX_FC_MACH = (1 << 5),
673 RT_IDX_ETH_FCOE = (1 << 6),
674 RT_IDX_CAM_HIT = (1 << 7),
675 RT_IDX_CAM_BIT0 = (1 << 8),
676 RT_IDX_CAM_BIT1 = (1 << 9),
677 RT_IDX_VLAN_TAG = (1 << 10),
678 RT_IDX_VLAN_MATCH = (1 << 11),
679 RT_IDX_VLAN_FILTER = (1 << 12),
680 RT_IDX_ETH_SKIP1 = (1 << 13),
681 RT_IDX_ETH_SKIP2 = (1 << 14),
682 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
683 RT_IDX_802_3 = (1 << 16),
684 RT_IDX_LLDP = (1 << 17),
685 RT_IDX_UNUSED018 = (1 << 18),
686 RT_IDX_UNUSED019 = (1 << 19),
687 RT_IDX_UNUSED20 = (1 << 20),
688 RT_IDX_UNUSED21 = (1 << 21),
689 RT_IDX_ERR = (1 << 22),
690 RT_IDX_VALID = (1 << 23),
691 RT_IDX_TU_CSUM_ERR = (1 << 24),
692 RT_IDX_IP_CSUM_ERR = (1 << 25),
693 RT_IDX_MAC_ERR = (1 << 26),
694 RT_IDX_RSS_TCP6 = (1 << 27),
695 RT_IDX_RSS_TCP4 = (1 << 28),
696 RT_IDX_RSS_IPV6 = (1 << 29),
697 RT_IDX_RSS_IPV4 = (1 << 30),
698 RT_IDX_RSS_MATCH = (1 << 31),
699
700
701 RT_IDX_ALL_ERR_SLOT = 0,
702 RT_IDX_MAC_ERR_SLOT = 0,
703 RT_IDX_IP_CSUM_ERR_SLOT = 1,
704 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
705 RT_IDX_BCAST_SLOT = 3,
706 RT_IDX_MCAST_MATCH_SLOT = 4,
707 RT_IDX_ALLMULTI_SLOT = 5,
708 RT_IDX_UNUSED6_SLOT = 6,
709 RT_IDX_UNUSED7_SLOT = 7,
710 RT_IDX_RSS_MATCH_SLOT = 8,
711 RT_IDX_RSS_IPV4_SLOT = 8,
712 RT_IDX_RSS_IPV6_SLOT = 9,
713 RT_IDX_RSS_TCP4_SLOT = 10,
714 RT_IDX_RSS_TCP6_SLOT = 11,
715 RT_IDX_CAM_HIT_SLOT = 12,
716 RT_IDX_UNUSED013 = 13,
717 RT_IDX_UNUSED014 = 14,
718 RT_IDX_PROMISCUOUS_SLOT = 15,
719 RT_IDX_MAX_RT_SLOTS = 8,
720 RT_IDX_MAX_NIC_SLOTS = 16,
721};
722
723
724
725
726enum {
727 XG_SERDES_ADDR_RDY = (1 << 31),
728 XG_SERDES_ADDR_R = (1 << 30),
729
730 XG_SERDES_ADDR_STS = 0x00001E06,
731 XG_SERDES_ADDR_XFI1_PWR_UP = 0x00000005,
732 XG_SERDES_ADDR_XFI2_PWR_UP = 0x0000000a,
733 XG_SERDES_ADDR_XAUI_PWR_DOWN = 0x00000001,
734
735
736 XG_SERDES_XAUI_AN_START = 0x00000000,
737 XG_SERDES_XAUI_AN_END = 0x00000034,
738 XG_SERDES_XAUI_HSS_PCS_START = 0x00000800,
739 XG_SERDES_XAUI_HSS_PCS_END = 0x0000880,
740 XG_SERDES_XFI_AN_START = 0x00001000,
741 XG_SERDES_XFI_AN_END = 0x00001034,
742 XG_SERDES_XFI_TRAIN_START = 0x10001050,
743 XG_SERDES_XFI_TRAIN_END = 0x1000107C,
744 XG_SERDES_XFI_HSS_PCS_START = 0x00001800,
745 XG_SERDES_XFI_HSS_PCS_END = 0x00001838,
746 XG_SERDES_XFI_HSS_TX_START = 0x00001c00,
747 XG_SERDES_XFI_HSS_TX_END = 0x00001c1f,
748 XG_SERDES_XFI_HSS_RX_START = 0x00001c40,
749 XG_SERDES_XFI_HSS_RX_END = 0x00001c5f,
750 XG_SERDES_XFI_HSS_PLL_START = 0x00001e00,
751 XG_SERDES_XFI_HSS_PLL_END = 0x00001e1f,
752};
753
754
755
756
757enum {
758 PRB_MX_ADDR_ARE = (1 << 16),
759 PRB_MX_ADDR_UP = (1 << 15),
760 PRB_MX_ADDR_SWP = (1 << 14),
761
762
763 PRB_MX_ADDR_MAX_MODS = 21,
764 PRB_MX_ADDR_MOD_SEL_SHIFT = 9,
765 PRB_MX_ADDR_MOD_SEL_TBD = 0,
766 PRB_MX_ADDR_MOD_SEL_IDE1 = 1,
767 PRB_MX_ADDR_MOD_SEL_IDE2 = 2,
768 PRB_MX_ADDR_MOD_SEL_FRB = 3,
769 PRB_MX_ADDR_MOD_SEL_ODE1 = 4,
770 PRB_MX_ADDR_MOD_SEL_ODE2 = 5,
771 PRB_MX_ADDR_MOD_SEL_DA1 = 6,
772 PRB_MX_ADDR_MOD_SEL_DA2 = 7,
773 PRB_MX_ADDR_MOD_SEL_IMP1 = 8,
774 PRB_MX_ADDR_MOD_SEL_IMP2 = 9,
775 PRB_MX_ADDR_MOD_SEL_OMP1 = 10,
776 PRB_MX_ADDR_MOD_SEL_OMP2 = 11,
777 PRB_MX_ADDR_MOD_SEL_ORS1 = 12,
778 PRB_MX_ADDR_MOD_SEL_ORS2 = 13,
779 PRB_MX_ADDR_MOD_SEL_REG = 14,
780 PRB_MX_ADDR_MOD_SEL_MAC1 = 16,
781 PRB_MX_ADDR_MOD_SEL_MAC2 = 17,
782 PRB_MX_ADDR_MOD_SEL_VQM1 = 18,
783 PRB_MX_ADDR_MOD_SEL_VQM2 = 19,
784 PRB_MX_ADDR_MOD_SEL_MOP = 20,
785
786
787
788 PRB_MX_ADDR_VALID_SYS_MOD = 0x000f7ff7,
789 PRB_MX_ADDR_VALID_PCI_MOD = 0x000040c1,
790 PRB_MX_ADDR_VALID_XGM_MOD = 0x00037309,
791 PRB_MX_ADDR_VALID_FC_MOD = 0x00003001,
792 PRB_MX_ADDR_VALID_TOTAL = 34,
793
794
795 PRB_MX_ADDR_CLOCK_SHIFT = 6,
796 PRB_MX_ADDR_SYS_CLOCK = 0,
797 PRB_MX_ADDR_PCI_CLOCK = 2,
798 PRB_MX_ADDR_FC_CLOCK = 5,
799 PRB_MX_ADDR_XGM_CLOCK = 6,
800
801 PRB_MX_ADDR_MAX_MUX = 64,
802};
803
804
805
806
807enum {
808 PROC_ADDR = 0,
809 PROC_DATA = 0x04,
810 SYS = 0x08,
811 RST_FO = 0x0c,
812 FSC = 0x10,
813 CSR = 0x14,
814 LED = 0x18,
815 ICB_RID = 0x1c,
816 ICB_L = 0x20,
817 ICB_H = 0x24,
818 CFG = 0x28,
819 BIOS_ADDR = 0x2c,
820 STS = 0x30,
821 INTR_EN = 0x34,
822 INTR_MASK = 0x38,
823 ISR1 = 0x3c,
824 ISR2 = 0x40,
825 ISR3 = 0x44,
826 ISR4 = 0x48,
827 REV_ID = 0x4c,
828 FRC_ECC_ERR = 0x50,
829 ERR_STS = 0x54,
830 RAM_DBG_ADDR = 0x58,
831 RAM_DBG_DATA = 0x5c,
832 ECC_ERR_CNT = 0x60,
833 SEM = 0x64,
834 GPIO_1 = 0x68,
835 GPIO_2 = 0x6c,
836 GPIO_3 = 0x70,
837 RSVD2 = 0x74,
838 XGMAC_ADDR = 0x78,
839 XGMAC_DATA = 0x7c,
840 NIC_ETS = 0x80,
841 CNA_ETS = 0x84,
842 FLASH_ADDR = 0x88,
843 FLASH_DATA = 0x8c,
844 CQ_STOP = 0x90,
845 PAGE_TBL_RID = 0x94,
846 WQ_PAGE_TBL_LO = 0x98,
847 WQ_PAGE_TBL_HI = 0x9c,
848 CQ_PAGE_TBL_LO = 0xa0,
849 CQ_PAGE_TBL_HI = 0xa4,
850 MAC_ADDR_IDX = 0xa8,
851 MAC_ADDR_DATA = 0xac,
852 COS_DFLT_CQ1 = 0xb0,
853 COS_DFLT_CQ2 = 0xb4,
854 ETYPE_SKIP1 = 0xb8,
855 ETYPE_SKIP2 = 0xbc,
856 SPLT_HDR = 0xc0,
857 FC_PAUSE_THRES = 0xc4,
858 NIC_PAUSE_THRES = 0xc8,
859 FC_ETHERTYPE = 0xcc,
860 FC_RCV_CFG = 0xd0,
861 NIC_RCV_CFG = 0xd4,
862 FC_COS_TAGS = 0xd8,
863 NIC_COS_TAGS = 0xdc,
864 MGMT_RCV_CFG = 0xe0,
865 RT_IDX = 0xe4,
866 RT_DATA = 0xe8,
867 RSVD7 = 0xec,
868 XG_SERDES_ADDR = 0xf0,
869 XG_SERDES_DATA = 0xf4,
870 PRB_MX_ADDR = 0xf8,
871 PRB_MX_DATA = 0xfc,
872};
873
874#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
875#define SMALL_BUFFER_SIZE 256
876#define SMALL_BUF_MAP_SIZE SMALL_BUFFER_SIZE
877#define SPLT_SETTING FSC_DBRST_1024
878#define SPLT_LEN 0
879#define QLGE_SB_PAD 0
880#else
881#define SMALL_BUFFER_SIZE 512
882#define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
883#define SPLT_SETTING FSC_SH
884#define SPLT_LEN (SPLT_HDR_EP | \
885 min(SMALL_BUF_MAP_SIZE, 1023))
886#define QLGE_SB_PAD 32
887#endif
888
889
890
891
892enum {
893 CAM_OUT_ROUTE_FC = 0,
894 CAM_OUT_ROUTE_NIC = 1,
895 CAM_OUT_FUNC_SHIFT = 2,
896 CAM_OUT_RV = (1 << 4),
897 CAM_OUT_SH = (1 << 15),
898 CAM_OUT_CQ_ID_SHIFT = 5,
899};
900
901
902
903
904enum {
905
906 AEN_SYS_ERR = 0x00008002,
907 AEN_LINK_UP = 0x00008011,
908 AEN_LINK_DOWN = 0x00008012,
909 AEN_IDC_CMPLT = 0x00008100,
910 AEN_IDC_REQ = 0x00008101,
911 AEN_IDC_EXT = 0x00008102,
912 AEN_DCBX_CHG = 0x00008110,
913 AEN_AEN_LOST = 0x00008120,
914 AEN_AEN_SFP_IN = 0x00008130,
915 AEN_AEN_SFP_OUT = 0x00008131,
916 AEN_FW_INIT_DONE = 0x00008400,
917 AEN_FW_INIT_FAIL = 0x00008401,
918
919
920 MB_CMD_NOP = 0x00000000,
921 MB_CMD_EX_FW = 0x00000002,
922 MB_CMD_MB_TEST = 0x00000006,
923 MB_CMD_CSUM_TEST = 0x00000007,
924 MB_CMD_ABOUT_FW = 0x00000008,
925 MB_CMD_COPY_RISC_RAM = 0x0000000a,
926 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
927 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
928 MB_CMD_WRITE_RAM = 0x0000000d,
929 MB_CMD_INIT_RISC_RAM = 0x0000000e,
930 MB_CMD_READ_RAM = 0x0000000f,
931 MB_CMD_STOP_FW = 0x00000014,
932 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
933 MB_CMD_WRITE_SFP = 0x00000030,
934 MB_CMD_READ_SFP = 0x00000031,
935 MB_CMD_INIT_FW = 0x00000060,
936 MB_CMD_GET_IFCB = 0x00000061,
937 MB_CMD_GET_FW_STATE = 0x00000069,
938 MB_CMD_IDC_REQ = 0x00000100,
939 MB_CMD_IDC_ACK = 0x00000101,
940 MB_CMD_SET_WOL_MODE = 0x00000110,
941 MB_WOL_DISABLE = 0,
942 MB_WOL_MAGIC_PKT = (1 << 1),
943 MB_WOL_FLTR = (1 << 2),
944 MB_WOL_UCAST = (1 << 3),
945 MB_WOL_MCAST = (1 << 4),
946 MB_WOL_BCAST = (1 << 5),
947 MB_WOL_LINK_UP = (1 << 6),
948 MB_WOL_LINK_DOWN = (1 << 7),
949 MB_WOL_MODE_ON = (1 << 16),
950 MB_CMD_SET_WOL_FLTR = 0x00000111,
951 MB_CMD_CLEAR_WOL_FLTR = 0x00000112,
952 MB_CMD_SET_WOL_MAGIC = 0x00000113,
953 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,
954 MB_CMD_SET_WOL_IMMED = 0x00000115,
955 MB_CMD_PORT_RESET = 0x00000120,
956 MB_CMD_SET_PORT_CFG = 0x00000122,
957 MB_CMD_GET_PORT_CFG = 0x00000123,
958 MB_CMD_GET_LINK_STS = 0x00000124,
959 MB_CMD_SET_LED_CFG = 0x00000125,
960 QL_LED_BLINK = 0x03e803e8,
961 MB_CMD_GET_LED_CFG = 0x00000126,
962 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160,
963 MB_SET_MPI_TFK_STOP = (1 << 0),
964 MB_SET_MPI_TFK_RESUME = (1 << 1),
965 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161,
966 MB_GET_MPI_TFK_STOPPED = (1 << 0),
967 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
968
969
970
971
972 MB_CMD_IOP_NONE = 0x0000,
973 MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001,
974 MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002,
975 MB_CMD_IOP_PREP_LINK_DOWN = 0x0010,
976 MB_CMD_IOP_DVR_START = 0x0100,
977 MB_CMD_IOP_FLASH_ACC = 0x0101,
978 MB_CMD_IOP_RESTART_MPI = 0x0102,
979 MB_CMD_IOP_CORE_DUMP_MPI = 0x0103,
980
981
982 MB_CMD_STS_GOOD = 0x00004000,
983 MB_CMD_STS_INTRMDT = 0x00001000,
984 MB_CMD_STS_INVLD_CMD = 0x00004001,
985 MB_CMD_STS_XFC_ERR = 0x00004002,
986 MB_CMD_STS_CSUM_ERR = 0x00004003,
987 MB_CMD_STS_ERR = 0x00004005,
988 MB_CMD_STS_PARAM_ERR = 0x00004006,
989};
990
991struct mbox_params {
992 u32 mbox_in[MAILBOX_COUNT];
993 u32 mbox_out[MAILBOX_COUNT];
994 int in_count;
995 int out_count;
996};
997
998struct flash_params_8012 {
999 u8 dev_id_str[4];
1000 __le16 size;
1001 __le16 csum;
1002 __le16 ver;
1003 __le16 sub_dev_id;
1004 u8 mac_addr[6];
1005 __le16 res;
1006};
1007
1008
1009
1010
1011#define FUNC0_FLASH_OFFSET 0x140200
1012#define FUNC1_FLASH_OFFSET 0x140600
1013
1014
1015struct flash_params_8000 {
1016 u8 dev_id_str[4];
1017 __le16 ver;
1018 __le16 size;
1019 __le16 csum;
1020 __le16 reserved0;
1021 __le16 total_size;
1022 __le16 entry_count;
1023 u8 data_type0;
1024 u8 data_size0;
1025 u8 mac_addr[6];
1026 u8 data_type1;
1027 u8 data_size1;
1028 u8 mac_addr1[6];
1029 u8 data_type2;
1030 u8 data_size2;
1031 __le16 vlan_id;
1032 u8 data_type3;
1033 u8 data_size3;
1034 __le16 last;
1035 u8 reserved1[464];
1036 __le16 subsys_ven_id;
1037 __le16 subsys_dev_id;
1038 u8 reserved2[4];
1039};
1040
1041union flash_params {
1042 struct flash_params_8012 flash_params_8012;
1043 struct flash_params_8000 flash_params_8000;
1044};
1045
1046
1047
1048
1049struct rx_doorbell_context {
1050 u32 cnsmr_idx;
1051 u32 valid;
1052 u32 reserved[4];
1053 u32 lbq_prod_idx;
1054 u32 sbq_prod_idx;
1055};
1056
1057
1058
1059
1060struct tx_doorbell_context {
1061 u32 prod_idx;
1062 u32 valid;
1063 u32 reserved[4];
1064 u32 lbq_prod_idx;
1065 u32 sbq_prod_idx;
1066};
1067
1068
1069struct tx_buf_desc {
1070 __le64 addr;
1071 __le32 len;
1072#define TX_DESC_LEN_MASK 0x000fffff
1073#define TX_DESC_C 0x40000000
1074#define TX_DESC_E 0x80000000
1075} __packed;
1076
1077
1078
1079
1080
1081#define OPCODE_OB_MAC_IOCB 0x01
1082#define OPCODE_OB_MAC_TSO_IOCB 0x02
1083#define OPCODE_IB_MAC_IOCB 0x20
1084#define OPCODE_IB_MPI_IOCB 0x21
1085#define OPCODE_IB_AE_IOCB 0x3f
1086
1087struct ob_mac_iocb_req {
1088 u8 opcode;
1089 u8 flags1;
1090#define OB_MAC_IOCB_REQ_OI 0x01
1091#define OB_MAC_IOCB_REQ_I 0x02
1092#define OB_MAC_IOCB_REQ_D 0x08
1093#define OB_MAC_IOCB_REQ_F 0x10
1094 u8 flags2;
1095 u8 flags3;
1096#define OB_MAC_IOCB_DFP 0x02
1097#define OB_MAC_IOCB_V 0x04
1098 __le32 reserved1[2];
1099 __le16 frame_len;
1100#define OB_MAC_IOCB_LEN_MASK 0x3ffff
1101 __le16 reserved2;
1102 u32 tid;
1103 u32 txq_idx;
1104 __le32 reserved3;
1105 __le16 vlan_tci;
1106 __le16 reserved4;
1107 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1108} __packed;
1109
1110struct ob_mac_iocb_rsp {
1111 u8 opcode;
1112 u8 flags1;
1113#define OB_MAC_IOCB_RSP_OI 0x01
1114#define OB_MAC_IOCB_RSP_I 0x02
1115#define OB_MAC_IOCB_RSP_E 0x08
1116#define OB_MAC_IOCB_RSP_S 0x10
1117#define OB_MAC_IOCB_RSP_L 0x20
1118#define OB_MAC_IOCB_RSP_P 0x40
1119 u8 flags2;
1120 u8 flags3;
1121#define OB_MAC_IOCB_RSP_B 0x80
1122 u32 tid;
1123 u32 txq_idx;
1124 __le32 reserved[13];
1125} __packed;
1126
1127struct ob_mac_tso_iocb_req {
1128 u8 opcode;
1129 u8 flags1;
1130#define OB_MAC_TSO_IOCB_OI 0x01
1131#define OB_MAC_TSO_IOCB_I 0x02
1132#define OB_MAC_TSO_IOCB_D 0x08
1133#define OB_MAC_TSO_IOCB_IP4 0x40
1134#define OB_MAC_TSO_IOCB_IP6 0x80
1135 u8 flags2;
1136#define OB_MAC_TSO_IOCB_LSO 0x20
1137#define OB_MAC_TSO_IOCB_UC 0x40
1138#define OB_MAC_TSO_IOCB_TC 0x80
1139 u8 flags3;
1140#define OB_MAC_TSO_IOCB_IC 0x01
1141#define OB_MAC_TSO_IOCB_DFP 0x02
1142#define OB_MAC_TSO_IOCB_V 0x04
1143 __le32 reserved1[2];
1144 __le32 frame_len;
1145 u32 tid;
1146 u32 txq_idx;
1147 __le16 total_hdrs_len;
1148 __le16 net_trans_offset;
1149#define OB_MAC_TRANSPORT_HDR_SHIFT 6
1150 __le16 vlan_tci;
1151 __le16 mss;
1152 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1153} __packed;
1154
1155struct ob_mac_tso_iocb_rsp {
1156 u8 opcode;
1157 u8 flags1;
1158#define OB_MAC_TSO_IOCB_RSP_OI 0x01
1159#define OB_MAC_TSO_IOCB_RSP_I 0x02
1160#define OB_MAC_TSO_IOCB_RSP_E 0x08
1161#define OB_MAC_TSO_IOCB_RSP_S 0x10
1162#define OB_MAC_TSO_IOCB_RSP_L 0x20
1163#define OB_MAC_TSO_IOCB_RSP_P 0x40
1164 u8 flags2;
1165 u8 flags3;
1166#define OB_MAC_TSO_IOCB_RSP_B 0x8000
1167 u32 tid;
1168 u32 txq_idx;
1169 __le32 reserved2[13];
1170} __packed;
1171
1172struct ib_mac_iocb_rsp {
1173 u8 opcode;
1174 u8 flags1;
1175#define IB_MAC_IOCB_RSP_OI 0x01
1176#define IB_MAC_IOCB_RSP_I 0x02
1177#define IB_MAC_CSUM_ERR_MASK 0x1c
1178#define IB_MAC_IOCB_RSP_TE 0x04
1179#define IB_MAC_IOCB_RSP_NU 0x08
1180#define IB_MAC_IOCB_RSP_IE 0x10
1181#define IB_MAC_IOCB_RSP_M_MASK 0x60
1182#define IB_MAC_IOCB_RSP_M_NONE 0x00
1183#define IB_MAC_IOCB_RSP_M_HASH 0x20
1184#define IB_MAC_IOCB_RSP_M_REG 0x40
1185#define IB_MAC_IOCB_RSP_M_PROM 0x60
1186#define IB_MAC_IOCB_RSP_B 0x80
1187 u8 flags2;
1188#define IB_MAC_IOCB_RSP_P 0x01
1189#define IB_MAC_IOCB_RSP_V 0x02
1190#define IB_MAC_IOCB_RSP_ERR_MASK 0x1c
1191#define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1192#define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1193#define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1194#define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1195#define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1196#define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1197#define IB_MAC_IOCB_RSP_U 0x20
1198#define IB_MAC_IOCB_RSP_T 0x40
1199#define IB_MAC_IOCB_RSP_FO 0x80
1200 u8 flags3;
1201#define IB_MAC_IOCB_RSP_RSS_MASK 0x07
1202#define IB_MAC_IOCB_RSP_M_NONE 0x00
1203#define IB_MAC_IOCB_RSP_M_IPV4 0x04
1204#define IB_MAC_IOCB_RSP_M_IPV6 0x02
1205#define IB_MAC_IOCB_RSP_M_TCP_V4 0x05
1206#define IB_MAC_IOCB_RSP_M_TCP_V6 0x03
1207#define IB_MAC_IOCB_RSP_V4 0x08
1208#define IB_MAC_IOCB_RSP_V6 0x10
1209#define IB_MAC_IOCB_RSP_IH 0x20
1210#define IB_MAC_IOCB_RSP_DS 0x40
1211#define IB_MAC_IOCB_RSP_DL 0x80
1212 __le32 data_len;
1213 __le64 data_addr;
1214 __le32 rss;
1215 __le16 vlan_id;
1216#define IB_MAC_IOCB_RSP_C 0x1000
1217#define IB_MAC_IOCB_RSP_COS_SHIFT 12
1218#define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1219
1220 __le16 reserved1;
1221 __le32 reserved2[6];
1222 u8 reserved3[3];
1223 u8 flags4;
1224#define IB_MAC_IOCB_RSP_HV 0x20
1225#define IB_MAC_IOCB_RSP_HS 0x40
1226#define IB_MAC_IOCB_RSP_HL 0x80
1227 __le32 hdr_len;
1228 __le64 hdr_addr;
1229} __packed;
1230
1231struct ib_ae_iocb_rsp {
1232 u8 opcode;
1233 u8 flags1;
1234#define IB_AE_IOCB_RSP_OI 0x01
1235#define IB_AE_IOCB_RSP_I 0x02
1236 u8 event;
1237#define LINK_UP_EVENT 0x00
1238#define LINK_DOWN_EVENT 0x01
1239#define CAM_LOOKUP_ERR_EVENT 0x06
1240#define SOFT_ECC_ERROR_EVENT 0x07
1241#define MGMT_ERR_EVENT 0x08
1242#define TEN_GIG_MAC_EVENT 0x09
1243#define GPI0_H2L_EVENT 0x10
1244#define GPI0_L2H_EVENT 0x20
1245#define GPI1_H2L_EVENT 0x11
1246#define GPI1_L2H_EVENT 0x21
1247#define PCI_ERR_ANON_BUF_RD 0x40
1248 u8 q_id;
1249 __le32 reserved[15];
1250} __packed;
1251
1252
1253
1254
1255
1256struct ql_net_rsp_iocb {
1257 u8 opcode;
1258 u8 flags0;
1259 __le16 length;
1260 __le32 tid;
1261 __le32 reserved[14];
1262} __packed;
1263
1264struct net_req_iocb {
1265 u8 opcode;
1266 u8 flags0;
1267 __le16 flags1;
1268 __le32 tid;
1269 __le32 reserved1[30];
1270} __packed;
1271
1272
1273
1274
1275
1276
1277struct wqicb {
1278 __le16 len;
1279#define Q_LEN_V (1 << 4)
1280#define Q_LEN_CPP_CONT 0x0000
1281#define Q_LEN_CPP_16 0x0001
1282#define Q_LEN_CPP_32 0x0002
1283#define Q_LEN_CPP_64 0x0003
1284#define Q_LEN_CPP_512 0x0006
1285 __le16 flags;
1286#define Q_PRI_SHIFT 1
1287#define Q_FLAGS_LC 0x1000
1288#define Q_FLAGS_LB 0x2000
1289#define Q_FLAGS_LI 0x4000
1290#define Q_FLAGS_LO 0x8000
1291 __le16 cq_id_rss;
1292#define Q_CQ_ID_RSS_RV 0x8000
1293 __le16 rid;
1294 __le64 addr;
1295 __le64 cnsmr_idx_addr;
1296} __packed;
1297
1298
1299
1300
1301
1302
1303struct cqicb {
1304 u8 msix_vect;
1305 u8 reserved1;
1306 u8 reserved2;
1307 u8 flags;
1308#define FLAGS_LV 0x08
1309#define FLAGS_LS 0x10
1310#define FLAGS_LL 0x20
1311#define FLAGS_LI 0x40
1312#define FLAGS_LC 0x80
1313 __le16 len;
1314#define LEN_V (1 << 4)
1315#define LEN_CPP_CONT 0x0000
1316#define LEN_CPP_32 0x0001
1317#define LEN_CPP_64 0x0002
1318#define LEN_CPP_128 0x0003
1319 __le16 rid;
1320 __le64 addr;
1321 __le64 prod_idx_addr;
1322 __le16 pkt_delay;
1323 __le16 irq_delay;
1324 __le64 lbq_addr;
1325 __le16 lbq_buf_size;
1326 __le16 lbq_len;
1327 __le64 sbq_addr;
1328 __le16 sbq_buf_size;
1329 __le16 sbq_len;
1330} __packed;
1331
1332struct ricb {
1333 u8 base_cq;
1334#define RSS_L4K 0x80
1335 u8 flags;
1336#define RSS_L6K 0x01
1337#define RSS_LI 0x02
1338#define RSS_LB 0x04
1339#define RSS_LM 0x08
1340#define RSS_RI4 0x10
1341#define RSS_RT4 0x20
1342#define RSS_RI6 0x40
1343#define RSS_RT6 0x80
1344 __le16 mask;
1345 u8 hash_cq_id[1024];
1346 __le32 ipv6_hash_key[10];
1347 __le32 ipv4_hash_key[4];
1348} __packed;
1349
1350
1351
1352struct oal {
1353 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1354};
1355
1356struct map_list {
1357 DEFINE_DMA_UNMAP_ADDR(mapaddr);
1358 DEFINE_DMA_UNMAP_LEN(maplen);
1359};
1360
1361struct tx_ring_desc {
1362 struct sk_buff *skb;
1363 struct ob_mac_iocb_req *queue_entry;
1364 u32 index;
1365 struct oal oal;
1366 struct map_list map[MAX_SKB_FRAGS + 2];
1367 int map_cnt;
1368 struct tx_ring_desc *next;
1369};
1370
1371#define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1372
1373struct tx_ring {
1374
1375
1376
1377 struct wqicb wqicb;
1378 void *wq_base;
1379 dma_addr_t wq_base_dma;
1380 __le32 *cnsmr_idx_sh_reg;
1381 dma_addr_t cnsmr_idx_sh_reg_dma;
1382 u32 wq_size;
1383 u32 wq_len;
1384 void __iomem *prod_idx_db_reg;
1385 void __iomem *valid_db_reg;
1386 u16 prod_idx;
1387 u16 cq_id;
1388 u8 wq_id;
1389 u8 reserved1[3];
1390 struct tx_ring_desc *q;
1391 spinlock_t lock;
1392 atomic_t tx_count;
1393 struct delayed_work tx_work;
1394 struct ql_adapter *qdev;
1395 u64 tx_packets;
1396 u64 tx_bytes;
1397 u64 tx_errors;
1398};
1399
1400struct qlge_page_chunk {
1401 struct page *page;
1402 void *va;
1403 unsigned int offset;
1404};
1405
1406struct qlge_bq_desc {
1407 union {
1408
1409 struct qlge_page_chunk pg_chunk;
1410
1411 struct sk_buff *skb;
1412 } p;
1413 dma_addr_t dma_addr;
1414
1415 __le64 *buf_ptr;
1416 u32 index;
1417};
1418
1419
1420struct qlge_bq {
1421 __le64 *base;
1422 dma_addr_t base_dma;
1423 __le64 *base_indirect;
1424 dma_addr_t base_indirect_dma;
1425 struct qlge_bq_desc *queue;
1426
1427
1428
1429 void __iomem *prod_idx_db_reg;
1430
1431 u16 next_to_use;
1432
1433 u16 next_to_clean;
1434 enum {
1435 QLGE_SB,
1436 QLGE_LB,
1437 } type;
1438};
1439
1440#define QLGE_BQ_CONTAINER(bq) \
1441({ \
1442 typeof(bq) _bq = bq; \
1443 (struct rx_ring *)((char *)_bq - (_bq->type == QLGE_SB ? \
1444 offsetof(struct rx_ring, sbq) : \
1445 offsetof(struct rx_ring, lbq))); \
1446})
1447
1448
1449
1450
1451#define QLGE_BQ_ALIGN(index) ALIGN_DOWN(index, 16)
1452
1453#define QLGE_BQ_WRAP(index) ((index) & (QLGE_BQ_LEN - 1))
1454
1455#define QLGE_BQ_HW_OWNED(bq) \
1456({ \
1457 typeof(bq) _bq = bq; \
1458 QLGE_BQ_WRAP(QLGE_BQ_ALIGN((_bq)->next_to_use) - \
1459 (_bq)->next_to_clean); \
1460})
1461
1462struct rx_ring {
1463 struct cqicb cqicb;
1464
1465
1466 void *cq_base;
1467 dma_addr_t cq_base_dma;
1468 u32 cq_size;
1469 u32 cq_len;
1470 u16 cq_id;
1471 __le32 *prod_idx_sh_reg;
1472 dma_addr_t prod_idx_sh_reg_dma;
1473 void __iomem *cnsmr_idx_db_reg;
1474 u32 cnsmr_idx;
1475 struct ql_net_rsp_iocb *curr_entry;
1476 void __iomem *valid_db_reg;
1477
1478
1479 struct qlge_bq lbq;
1480 struct qlge_page_chunk master_chunk;
1481 dma_addr_t chunk_dma_addr;
1482
1483
1484 struct qlge_bq sbq;
1485
1486
1487 u32 irq;
1488 u32 cpu;
1489 struct delayed_work refill_work;
1490 char name[IFNAMSIZ + 5];
1491 struct napi_struct napi;
1492 u8 reserved;
1493 struct ql_adapter *qdev;
1494 u64 rx_packets;
1495 u64 rx_multicast;
1496 u64 rx_bytes;
1497 u64 rx_dropped;
1498 u64 rx_errors;
1499};
1500
1501
1502
1503
1504struct hash_id {
1505 u8 value[4];
1506};
1507
1508struct nic_stats {
1509
1510
1511
1512
1513 u64 tx_pkts;
1514 u64 tx_bytes;
1515 u64 tx_mcast_pkts;
1516 u64 tx_bcast_pkts;
1517 u64 tx_ucast_pkts;
1518 u64 tx_ctl_pkts;
1519 u64 tx_pause_pkts;
1520 u64 tx_64_pkt;
1521 u64 tx_65_to_127_pkt;
1522 u64 tx_128_to_255_pkt;
1523 u64 tx_256_511_pkt;
1524 u64 tx_512_to_1023_pkt;
1525 u64 tx_1024_to_1518_pkt;
1526 u64 tx_1519_to_max_pkt;
1527 u64 tx_undersize_pkt;
1528 u64 tx_oversize_pkt;
1529
1530
1531
1532
1533
1534 u64 rx_bytes;
1535 u64 rx_bytes_ok;
1536 u64 rx_pkts;
1537 u64 rx_pkts_ok;
1538 u64 rx_bcast_pkts;
1539 u64 rx_mcast_pkts;
1540 u64 rx_ucast_pkts;
1541 u64 rx_undersize_pkts;
1542 u64 rx_oversize_pkts;
1543 u64 rx_jabber_pkts;
1544 u64 rx_undersize_fcerr_pkts;
1545 u64 rx_drop_events;
1546 u64 rx_fcerr_pkts;
1547 u64 rx_align_err;
1548 u64 rx_symbol_err;
1549 u64 rx_mac_err;
1550 u64 rx_ctl_pkts;
1551 u64 rx_pause_pkts;
1552 u64 rx_64_pkts;
1553 u64 rx_65_to_127_pkts;
1554 u64 rx_128_255_pkts;
1555 u64 rx_256_511_pkts;
1556 u64 rx_512_to_1023_pkts;
1557 u64 rx_1024_to_1518_pkts;
1558 u64 rx_1519_to_max_pkts;
1559 u64 rx_len_err_pkts;
1560
1561 u64 rx_code_err;
1562 u64 rx_oversize_err;
1563 u64 rx_undersize_err;
1564 u64 rx_preamble_err;
1565 u64 rx_frame_len_err;
1566 u64 rx_crc_err;
1567 u64 rx_err_count;
1568
1569
1570
1571
1572 u64 tx_cbfc_pause_frames0;
1573 u64 tx_cbfc_pause_frames1;
1574 u64 tx_cbfc_pause_frames2;
1575 u64 tx_cbfc_pause_frames3;
1576 u64 tx_cbfc_pause_frames4;
1577 u64 tx_cbfc_pause_frames5;
1578 u64 tx_cbfc_pause_frames6;
1579 u64 tx_cbfc_pause_frames7;
1580 u64 rx_cbfc_pause_frames0;
1581 u64 rx_cbfc_pause_frames1;
1582 u64 rx_cbfc_pause_frames2;
1583 u64 rx_cbfc_pause_frames3;
1584 u64 rx_cbfc_pause_frames4;
1585 u64 rx_cbfc_pause_frames5;
1586 u64 rx_cbfc_pause_frames6;
1587 u64 rx_cbfc_pause_frames7;
1588 u64 rx_nic_fifo_drop;
1589};
1590
1591
1592enum {
1593 MPI_CORE_REGS_ADDR = 0x00030000,
1594 MPI_CORE_REGS_CNT = 127,
1595 MPI_CORE_SH_REGS_CNT = 16,
1596 TEST_REGS_ADDR = 0x00001000,
1597 TEST_REGS_CNT = 23,
1598 RMII_REGS_ADDR = 0x00001040,
1599 RMII_REGS_CNT = 64,
1600 FCMAC1_REGS_ADDR = 0x00001080,
1601 FCMAC2_REGS_ADDR = 0x000010c0,
1602 FCMAC_REGS_CNT = 64,
1603 FC1_MBX_REGS_ADDR = 0x00001100,
1604 FC2_MBX_REGS_ADDR = 0x00001240,
1605 FC_MBX_REGS_CNT = 64,
1606 IDE_REGS_ADDR = 0x00001140,
1607 IDE_REGS_CNT = 64,
1608 NIC1_MBX_REGS_ADDR = 0x00001180,
1609 NIC2_MBX_REGS_ADDR = 0x00001280,
1610 NIC_MBX_REGS_CNT = 64,
1611 SMBUS_REGS_ADDR = 0x00001200,
1612 SMBUS_REGS_CNT = 64,
1613 I2C_REGS_ADDR = 0x00001fc0,
1614 I2C_REGS_CNT = 64,
1615 MEMC_REGS_ADDR = 0x00003000,
1616 MEMC_REGS_CNT = 256,
1617 PBUS_REGS_ADDR = 0x00007c00,
1618 PBUS_REGS_CNT = 256,
1619 MDE_REGS_ADDR = 0x00010000,
1620 MDE_REGS_CNT = 6,
1621 CODE_RAM_ADDR = 0x00020000,
1622 CODE_RAM_CNT = 0x2000,
1623 MEMC_RAM_ADDR = 0x00100000,
1624 MEMC_RAM_CNT = 0x2000,
1625};
1626
1627#define MPI_COREDUMP_COOKIE 0x5555aaaa
1628struct mpi_coredump_global_header {
1629 u32 cookie;
1630 u8 idString[16];
1631 u32 timeLo;
1632 u32 timeHi;
1633 u32 imageSize;
1634 u32 headerSize;
1635 u8 info[220];
1636};
1637
1638struct mpi_coredump_segment_header {
1639 u32 cookie;
1640 u32 segNum;
1641 u32 segSize;
1642 u32 extra;
1643 u8 description[16];
1644};
1645
1646
1647enum {
1648 CORE_SEG_NUM = 1,
1649 TEST_LOGIC_SEG_NUM = 2,
1650 RMII_SEG_NUM = 3,
1651 FCMAC1_SEG_NUM = 4,
1652 FCMAC2_SEG_NUM = 5,
1653 FC1_MBOX_SEG_NUM = 6,
1654 IDE_SEG_NUM = 7,
1655 NIC1_MBOX_SEG_NUM = 8,
1656 SMBUS_SEG_NUM = 9,
1657 FC2_MBOX_SEG_NUM = 10,
1658 NIC2_MBOX_SEG_NUM = 11,
1659 I2C_SEG_NUM = 12,
1660 MEMC_SEG_NUM = 13,
1661 PBUS_SEG_NUM = 14,
1662 MDE_SEG_NUM = 15,
1663 NIC1_CONTROL_SEG_NUM = 16,
1664 NIC2_CONTROL_SEG_NUM = 17,
1665 NIC1_XGMAC_SEG_NUM = 18,
1666 NIC2_XGMAC_SEG_NUM = 19,
1667 WCS_RAM_SEG_NUM = 20,
1668 MEMC_RAM_SEG_NUM = 21,
1669 XAUI_AN_SEG_NUM = 22,
1670 XAUI_HSS_PCS_SEG_NUM = 23,
1671 XFI_AN_SEG_NUM = 24,
1672 XFI_TRAIN_SEG_NUM = 25,
1673 XFI_HSS_PCS_SEG_NUM = 26,
1674 XFI_HSS_TX_SEG_NUM = 27,
1675 XFI_HSS_RX_SEG_NUM = 28,
1676 XFI_HSS_PLL_SEG_NUM = 29,
1677 MISC_NIC_INFO_SEG_NUM = 30,
1678 INTR_STATES_SEG_NUM = 31,
1679 CAM_ENTRIES_SEG_NUM = 32,
1680 ROUTING_WORDS_SEG_NUM = 33,
1681 ETS_SEG_NUM = 34,
1682 PROBE_DUMP_SEG_NUM = 35,
1683 ROUTING_INDEX_SEG_NUM = 36,
1684 MAC_PROTOCOL_SEG_NUM = 37,
1685 XAUI2_AN_SEG_NUM = 38,
1686 XAUI2_HSS_PCS_SEG_NUM = 39,
1687 XFI2_AN_SEG_NUM = 40,
1688 XFI2_TRAIN_SEG_NUM = 41,
1689 XFI2_HSS_PCS_SEG_NUM = 42,
1690 XFI2_HSS_TX_SEG_NUM = 43,
1691 XFI2_HSS_RX_SEG_NUM = 44,
1692 XFI2_HSS_PLL_SEG_NUM = 45,
1693 SEM_REGS_SEG_NUM = 50
1694
1695};
1696
1697
1698#define NIC_REGS_DUMP_WORD_COUNT 64
1699
1700#define XGMAC_DUMP_WORD_COUNT (XGMAC_REGISTER_END / 4)
1701
1702#define XG_SERDES_XAUI_AN_COUNT 14
1703#define XG_SERDES_XAUI_HSS_PCS_COUNT 33
1704#define XG_SERDES_XFI_AN_COUNT 14
1705#define XG_SERDES_XFI_TRAIN_COUNT 12
1706#define XG_SERDES_XFI_HSS_PCS_COUNT 15
1707#define XG_SERDES_XFI_HSS_TX_COUNT 32
1708#define XG_SERDES_XFI_HSS_RX_COUNT 32
1709#define XG_SERDES_XFI_HSS_PLL_COUNT 32
1710
1711
1712#define ETS_REGS_DUMP_WORD_COUNT 10
1713
1714
1715
1716
1717
1718#define PRB_MX_ADDR_PRB_WORD_COUNT (1 + (PRB_MX_ADDR_MAX_MUX * 2))
1719#define PRB_MX_DUMP_TOT_COUNT (PRB_MX_ADDR_PRB_WORD_COUNT * \
1720 PRB_MX_ADDR_VALID_TOTAL)
1721
1722
1723
1724
1725
1726
1727#define RT_IDX_DUMP_ENTRIES 48
1728#define RT_IDX_DUMP_WORDS_PER_ENTRY 4
1729#define RT_IDX_DUMP_TOT_WORDS (RT_IDX_DUMP_ENTRIES * \
1730 RT_IDX_DUMP_WORDS_PER_ENTRY)
1731
1732
1733
1734#define MAC_ADDR_DUMP_ENTRIES \
1735 ((MAC_ADDR_MAX_CAM_ENTRIES * MAC_ADDR_MAX_CAM_WCOUNT) + \
1736 (MAC_ADDR_MAX_MULTICAST_ENTRIES * MAC_ADDR_MAX_MULTICAST_WCOUNT) + \
1737 (MAC_ADDR_MAX_VLAN_ENTRIES * MAC_ADDR_MAX_VLAN_WCOUNT) + \
1738 (MAC_ADDR_MAX_MCAST_FLTR_ENTRIES * MAC_ADDR_MAX_MCAST_FLTR_WCOUNT) + \
1739 (MAC_ADDR_MAX_FC_MAC_ENTRIES * MAC_ADDR_MAX_FC_MAC_WCOUNT) + \
1740 (MAC_ADDR_MAX_MGMT_MAC_ENTRIES * MAC_ADDR_MAX_MGMT_MAC_WCOUNT) + \
1741 (MAC_ADDR_MAX_MGMT_VLAN_ENTRIES * MAC_ADDR_MAX_MGMT_VLAN_WCOUNT) + \
1742 (MAC_ADDR_MAX_MGMT_V4_ENTRIES * MAC_ADDR_MAX_MGMT_V4_WCOUNT) + \
1743 (MAC_ADDR_MAX_MGMT_V6_ENTRIES * MAC_ADDR_MAX_MGMT_V6_WCOUNT) + \
1744 (MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES * MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT))
1745#define MAC_ADDR_DUMP_WORDS_PER_ENTRY 2
1746#define MAC_ADDR_DUMP_TOT_WORDS (MAC_ADDR_DUMP_ENTRIES * \
1747 MAC_ADDR_DUMP_WORDS_PER_ENTRY)
1748
1749
1750
1751#define MAX_SEMAPHORE_FUNCTIONS 4
1752
1753#define RISC_124 0x0003007c
1754#define RISC_127 0x0003007f
1755#define SHADOW_OFFSET 0xb0000000
1756#define SHADOW_REG_SHIFT 20
1757
1758struct ql_nic_misc {
1759 u32 rx_ring_count;
1760 u32 tx_ring_count;
1761 u32 intr_count;
1762 u32 function;
1763};
1764
1765struct ql_reg_dump {
1766
1767
1768 struct mpi_coredump_global_header mpi_global_header;
1769
1770
1771 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1772 u32 nic_regs[64];
1773
1774
1775 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1776 struct ql_nic_misc misc_nic_info;
1777
1778
1779
1780 struct mpi_coredump_segment_header intr_states_seg_hdr;
1781 u32 intr_states[MAX_CPUS];
1782
1783
1784
1785
1786
1787 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1788 u32 cam_entries[(16 * 3) + (32 * 3)];
1789
1790
1791 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1792 u32 nic_routing_words[16];
1793
1794
1795 struct mpi_coredump_segment_header ets_seg_hdr;
1796 u32 ets[8+2];
1797};
1798
1799struct ql_mpi_coredump {
1800
1801 struct mpi_coredump_global_header mpi_global_header;
1802
1803
1804 struct mpi_coredump_segment_header core_regs_seg_hdr;
1805 u32 mpi_core_regs[MPI_CORE_REGS_CNT];
1806 u32 mpi_core_sh_regs[MPI_CORE_SH_REGS_CNT];
1807
1808
1809 struct mpi_coredump_segment_header test_logic_regs_seg_hdr;
1810 u32 test_logic_regs[TEST_REGS_CNT];
1811
1812
1813 struct mpi_coredump_segment_header rmii_regs_seg_hdr;
1814 u32 rmii_regs[RMII_REGS_CNT];
1815
1816
1817 struct mpi_coredump_segment_header fcmac1_regs_seg_hdr;
1818 u32 fcmac1_regs[FCMAC_REGS_CNT];
1819
1820
1821 struct mpi_coredump_segment_header fcmac2_regs_seg_hdr;
1822 u32 fcmac2_regs[FCMAC_REGS_CNT];
1823
1824
1825 struct mpi_coredump_segment_header fc1_mbx_regs_seg_hdr;
1826 u32 fc1_mbx_regs[FC_MBX_REGS_CNT];
1827
1828
1829 struct mpi_coredump_segment_header ide_regs_seg_hdr;
1830 u32 ide_regs[IDE_REGS_CNT];
1831
1832
1833 struct mpi_coredump_segment_header nic1_mbx_regs_seg_hdr;
1834 u32 nic1_mbx_regs[NIC_MBX_REGS_CNT];
1835
1836
1837 struct mpi_coredump_segment_header smbus_regs_seg_hdr;
1838 u32 smbus_regs[SMBUS_REGS_CNT];
1839
1840
1841 struct mpi_coredump_segment_header fc2_mbx_regs_seg_hdr;
1842 u32 fc2_mbx_regs[FC_MBX_REGS_CNT];
1843
1844
1845 struct mpi_coredump_segment_header nic2_mbx_regs_seg_hdr;
1846 u32 nic2_mbx_regs[NIC_MBX_REGS_CNT];
1847
1848
1849 struct mpi_coredump_segment_header i2c_regs_seg_hdr;
1850 u32 i2c_regs[I2C_REGS_CNT];
1851
1852 struct mpi_coredump_segment_header memc_regs_seg_hdr;
1853 u32 memc_regs[MEMC_REGS_CNT];
1854
1855
1856 struct mpi_coredump_segment_header pbus_regs_seg_hdr;
1857 u32 pbus_regs[PBUS_REGS_CNT];
1858
1859
1860 struct mpi_coredump_segment_header mde_regs_seg_hdr;
1861 u32 mde_regs[MDE_REGS_CNT];
1862
1863
1864 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1865 u32 nic_regs[NIC_REGS_DUMP_WORD_COUNT];
1866
1867
1868 struct mpi_coredump_segment_header nic2_regs_seg_hdr;
1869 u32 nic2_regs[NIC_REGS_DUMP_WORD_COUNT];
1870
1871
1872 struct mpi_coredump_segment_header xgmac1_seg_hdr;
1873 u32 xgmac1[XGMAC_DUMP_WORD_COUNT];
1874
1875
1876 struct mpi_coredump_segment_header xgmac2_seg_hdr;
1877 u32 xgmac2[XGMAC_DUMP_WORD_COUNT];
1878
1879
1880 struct mpi_coredump_segment_header code_ram_seg_hdr;
1881 u32 code_ram[CODE_RAM_CNT];
1882
1883
1884 struct mpi_coredump_segment_header memc_ram_seg_hdr;
1885 u32 memc_ram[MEMC_RAM_CNT];
1886
1887
1888 struct mpi_coredump_segment_header xaui_an_hdr;
1889 u32 serdes_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1890
1891
1892 struct mpi_coredump_segment_header xaui_hss_pcs_hdr;
1893 u32 serdes_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1894
1895
1896 struct mpi_coredump_segment_header xfi_an_hdr;
1897 u32 serdes_xfi_an[XG_SERDES_XFI_AN_COUNT];
1898
1899
1900 struct mpi_coredump_segment_header xfi_train_hdr;
1901 u32 serdes_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1902
1903
1904 struct mpi_coredump_segment_header xfi_hss_pcs_hdr;
1905 u32 serdes_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1906
1907
1908 struct mpi_coredump_segment_header xfi_hss_tx_hdr;
1909 u32 serdes_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1910
1911
1912 struct mpi_coredump_segment_header xfi_hss_rx_hdr;
1913 u32 serdes_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1914
1915
1916 struct mpi_coredump_segment_header xfi_hss_pll_hdr;
1917 u32 serdes_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1918
1919
1920 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1921 struct ql_nic_misc misc_nic_info;
1922
1923
1924
1925 struct mpi_coredump_segment_header intr_states_seg_hdr;
1926 u32 intr_states[MAX_RX_RINGS];
1927
1928
1929
1930
1931
1932 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1933 u32 cam_entries[(16 * 3) + (32 * 3)];
1934
1935
1936 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1937 u32 nic_routing_words[16];
1938
1939 struct mpi_coredump_segment_header ets_seg_hdr;
1940 u32 ets[ETS_REGS_DUMP_WORD_COUNT];
1941
1942
1943 struct mpi_coredump_segment_header probe_dump_seg_hdr;
1944 u32 probe_dump[PRB_MX_DUMP_TOT_COUNT];
1945
1946
1947 struct mpi_coredump_segment_header routing_reg_seg_hdr;
1948 u32 routing_regs[RT_IDX_DUMP_TOT_WORDS];
1949
1950
1951 struct mpi_coredump_segment_header mac_prot_reg_seg_hdr;
1952 u32 mac_prot_regs[MAC_ADDR_DUMP_TOT_WORDS];
1953
1954
1955 struct mpi_coredump_segment_header xaui2_an_hdr;
1956 u32 serdes2_xaui_an[XG_SERDES_XAUI_AN_COUNT];
1957
1958
1959 struct mpi_coredump_segment_header xaui2_hss_pcs_hdr;
1960 u32 serdes2_xaui_hss_pcs[XG_SERDES_XAUI_HSS_PCS_COUNT];
1961
1962
1963 struct mpi_coredump_segment_header xfi2_an_hdr;
1964 u32 serdes2_xfi_an[XG_SERDES_XFI_AN_COUNT];
1965
1966
1967 struct mpi_coredump_segment_header xfi2_train_hdr;
1968 u32 serdes2_xfi_train[XG_SERDES_XFI_TRAIN_COUNT];
1969
1970
1971 struct mpi_coredump_segment_header xfi2_hss_pcs_hdr;
1972 u32 serdes2_xfi_hss_pcs[XG_SERDES_XFI_HSS_PCS_COUNT];
1973
1974
1975 struct mpi_coredump_segment_header xfi2_hss_tx_hdr;
1976 u32 serdes2_xfi_hss_tx[XG_SERDES_XFI_HSS_TX_COUNT];
1977
1978
1979 struct mpi_coredump_segment_header xfi2_hss_rx_hdr;
1980 u32 serdes2_xfi_hss_rx[XG_SERDES_XFI_HSS_RX_COUNT];
1981
1982
1983 struct mpi_coredump_segment_header xfi2_hss_pll_hdr;
1984 u32 serdes2_xfi_hss_pll[XG_SERDES_XFI_HSS_PLL_COUNT];
1985
1986
1987
1988 struct mpi_coredump_segment_header sem_regs_seg_hdr;
1989 u32 sem_regs[MAX_SEMAPHORE_FUNCTIONS];
1990};
1991
1992
1993
1994
1995
1996
1997struct intr_context {
1998 struct ql_adapter *qdev;
1999 u32 intr;
2000 u32 irq_mask;
2001 u32 hooked;
2002 u32 intr_en_mask;
2003 u32 intr_dis_mask;
2004 u32 intr_read_mask;
2005 char name[IFNAMSIZ * 2];
2006 irq_handler_t handler;
2007};
2008
2009
2010enum {
2011 QL_ADAPTER_UP = 0,
2012 QL_LEGACY_ENABLED = 1,
2013 QL_MSI_ENABLED = 2,
2014 QL_MSIX_ENABLED = 3,
2015 QL_DMA64 = 4,
2016 QL_PROMISCUOUS = 5,
2017 QL_ALLMULTI = 6,
2018 QL_PORT_CFG = 7,
2019 QL_CAM_RT_SET = 8,
2020 QL_SELFTEST = 9,
2021 QL_LB_LINK_UP = 10,
2022 QL_FRC_COREDUMP = 11,
2023 QL_EEH_FATAL = 12,
2024 QL_ASIC_RECOVERY = 14,
2025};
2026
2027
2028enum {
2029 STS_LOOPBACK_MASK = 0x00000700,
2030 STS_LOOPBACK_PCS = 0x00000100,
2031 STS_LOOPBACK_HSS = 0x00000200,
2032 STS_LOOPBACK_EXT = 0x00000300,
2033 STS_PAUSE_MASK = 0x000000c0,
2034 STS_PAUSE_STD = 0x00000040,
2035 STS_PAUSE_PRI = 0x00000080,
2036 STS_SPEED_MASK = 0x00000038,
2037 STS_SPEED_100Mb = 0x00000000,
2038 STS_SPEED_1Gb = 0x00000008,
2039 STS_SPEED_10Gb = 0x00000010,
2040 STS_LINK_TYPE_MASK = 0x00000007,
2041 STS_LINK_TYPE_XFI = 0x00000001,
2042 STS_LINK_TYPE_XAUI = 0x00000002,
2043 STS_LINK_TYPE_XFI_BP = 0x00000003,
2044 STS_LINK_TYPE_XAUI_BP = 0x00000004,
2045 STS_LINK_TYPE_10GBASET = 0x00000005,
2046};
2047
2048
2049enum {
2050 CFG_JUMBO_FRAME_SIZE = 0x00010000,
2051 CFG_PAUSE_MASK = 0x00000060,
2052 CFG_PAUSE_STD = 0x00000020,
2053 CFG_PAUSE_PRI = 0x00000040,
2054 CFG_DCBX = 0x00000010,
2055 CFG_LOOPBACK_MASK = 0x00000007,
2056 CFG_LOOPBACK_PCS = 0x00000002,
2057 CFG_LOOPBACK_HSS = 0x00000004,
2058 CFG_LOOPBACK_EXT = 0x00000006,
2059 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
2060};
2061
2062struct nic_operations {
2063
2064 int (*get_flash) (struct ql_adapter *);
2065 int (*port_initialize) (struct ql_adapter *);
2066};
2067
2068
2069
2070
2071
2072struct ql_adapter {
2073 struct ricb ricb;
2074 unsigned long flags;
2075 u32 wol;
2076
2077 struct nic_stats nic_stats;
2078
2079 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
2080
2081
2082 struct pci_dev *pdev;
2083 struct net_device *ndev;
2084
2085
2086 u32 chip_rev_id;
2087 u32 fw_rev_id;
2088 u32 func;
2089 u32 alt_func;
2090 u32 port;
2091
2092 spinlock_t adapter_lock;
2093 spinlock_t stats_lock;
2094
2095
2096 void __iomem *reg_base;
2097 void __iomem *doorbell_area;
2098 u32 doorbell_area_size;
2099
2100 u32 msg_enable;
2101
2102
2103 void *rx_ring_shadow_reg_area;
2104 dma_addr_t rx_ring_shadow_reg_dma;
2105 void *tx_ring_shadow_reg_area;
2106 dma_addr_t tx_ring_shadow_reg_dma;
2107
2108 u32 mailbox_in;
2109 u32 mailbox_out;
2110 struct mbox_params idc_mbc;
2111 struct mutex mpi_mutex;
2112
2113 int tx_ring_size;
2114 int rx_ring_size;
2115 u32 intr_count;
2116 struct msix_entry *msi_x_entry;
2117 struct intr_context intr_context[MAX_RX_RINGS];
2118
2119 int tx_ring_count;
2120 u32 rss_ring_count;
2121
2122
2123
2124
2125
2126 int rx_ring_count;
2127 int ring_mem_size;
2128 void *ring_mem;
2129
2130 struct rx_ring rx_ring[MAX_RX_RINGS];
2131 struct tx_ring tx_ring[MAX_TX_RINGS];
2132 unsigned int lbq_buf_order;
2133 u32 lbq_buf_size;
2134
2135 int rx_csum;
2136 u32 default_rx_queue;
2137
2138 u16 rx_coalesce_usecs;
2139 u16 rx_max_coalesced_frames;
2140 u16 tx_coalesce_usecs;
2141 u16 tx_max_coalesced_frames;
2142
2143 u32 xg_sem_mask;
2144 u32 port_link_up;
2145 u32 port_init;
2146 u32 link_status;
2147 struct ql_mpi_coredump *mpi_coredump;
2148 u32 core_is_dumped;
2149 u32 link_config;
2150 u32 led_config;
2151 u32 max_frame_size;
2152
2153 union flash_params flash;
2154
2155 struct workqueue_struct *workqueue;
2156 struct delayed_work asic_reset_work;
2157 struct delayed_work mpi_reset_work;
2158 struct delayed_work mpi_work;
2159 struct delayed_work mpi_port_cfg_work;
2160 struct delayed_work mpi_idc_work;
2161 struct delayed_work mpi_core_to_log;
2162 struct completion ide_completion;
2163 const struct nic_operations *nic_ops;
2164 u16 device_id;
2165 struct timer_list timer;
2166 atomic_t lb_count;
2167
2168 char current_mac_addr[ETH_ALEN];
2169};
2170
2171
2172
2173
2174static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
2175{
2176 return readl(qdev->reg_base + reg);
2177}
2178
2179
2180
2181
2182static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
2183{
2184 writel(val, qdev->reg_base + reg);
2185}
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197static inline void ql_write_db_reg(u32 val, void __iomem *addr)
2198{
2199 writel(val, addr);
2200}
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213static inline void ql_write_db_reg_relaxed(u32 val, void __iomem *addr)
2214{
2215 writel_relaxed(val, addr);
2216}
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228static inline u32 ql_read_sh_reg(__le32 *addr)
2229{
2230 u32 reg;
2231 reg = le32_to_cpu(*addr);
2232 rmb();
2233 return reg;
2234}
2235
2236extern char qlge_driver_name[];
2237extern const char qlge_driver_version[];
2238extern const struct ethtool_ops qlge_ethtool_ops;
2239
2240int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
2241void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
2242int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2243int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
2244 u32 *value);
2245int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
2246int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
2247 u16 q_id);
2248void ql_queue_fw_error(struct ql_adapter *qdev);
2249void ql_mpi_work(struct work_struct *work);
2250void ql_mpi_reset_work(struct work_struct *work);
2251void ql_mpi_core_to_log(struct work_struct *work);
2252int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
2253void ql_queue_asic_error(struct ql_adapter *qdev);
2254void ql_set_ethtool_ops(struct net_device *ndev);
2255int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
2256void ql_mpi_idc_work(struct work_struct *work);
2257void ql_mpi_port_cfg_work(struct work_struct *work);
2258int ql_mb_get_fw_state(struct ql_adapter *qdev);
2259int ql_cam_route_initialize(struct ql_adapter *qdev);
2260int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
2261int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data);
2262int ql_unpause_mpi_risc(struct ql_adapter *qdev);
2263int ql_pause_mpi_risc(struct ql_adapter *qdev);
2264int ql_hard_reset_mpi_risc(struct ql_adapter *qdev);
2265int ql_soft_reset_mpi_risc(struct ql_adapter *qdev);
2266int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf, u32 ram_addr,
2267 int word_count);
2268int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump);
2269int ql_mb_about_fw(struct ql_adapter *qdev);
2270int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol);
2271int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol);
2272int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config);
2273int ql_mb_get_led_cfg(struct ql_adapter *qdev);
2274void ql_link_on(struct ql_adapter *qdev);
2275void ql_link_off(struct ql_adapter *qdev);
2276int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
2277int ql_mb_get_port_cfg(struct ql_adapter *qdev);
2278int ql_mb_set_port_cfg(struct ql_adapter *qdev);
2279int ql_wait_fifo_empty(struct ql_adapter *qdev);
2280void ql_get_dump(struct ql_adapter *qdev, void *buff);
2281netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
2282void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *);
2283int ql_own_firmware(struct ql_adapter *qdev);
2284int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
2285
2286
2287
2288
2289
2290
2291
2292
2293#ifdef QL_REG_DUMP
2294void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
2295void ql_dump_routing_entries(struct ql_adapter *qdev);
2296void ql_dump_regs(struct ql_adapter *qdev);
2297#define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
2298#define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
2299#define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
2300#else
2301#define QL_DUMP_REGS(qdev)
2302#define QL_DUMP_ROUTE(qdev)
2303#define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
2304#endif
2305
2306#ifdef QL_STAT_DUMP
2307void ql_dump_stat(struct ql_adapter *qdev);
2308#define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
2309#else
2310#define QL_DUMP_STAT(qdev)
2311#endif
2312
2313#ifdef QL_DEV_DUMP
2314void ql_dump_qdev(struct ql_adapter *qdev);
2315#define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
2316#else
2317#define QL_DUMP_QDEV(qdev)
2318#endif
2319
2320#ifdef QL_CB_DUMP
2321void ql_dump_wqicb(struct wqicb *wqicb);
2322void ql_dump_tx_ring(struct tx_ring *tx_ring);
2323void ql_dump_ricb(struct ricb *ricb);
2324void ql_dump_cqicb(struct cqicb *cqicb);
2325void ql_dump_rx_ring(struct rx_ring *rx_ring);
2326void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
2327#define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
2328#define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
2329#define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
2330#define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
2331#define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
2332#define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
2333 ql_dump_hw_cb(qdev, size, bit, q_id)
2334#else
2335#define QL_DUMP_RICB(ricb)
2336#define QL_DUMP_WQICB(wqicb)
2337#define QL_DUMP_TX_RING(tx_ring)
2338#define QL_DUMP_CQICB(cqicb)
2339#define QL_DUMP_RX_RING(rx_ring)
2340#define QL_DUMP_HW_CB(qdev, size, bit, q_id)
2341#endif
2342
2343#ifdef QL_OB_DUMP
2344void ql_dump_tx_desc(struct tx_buf_desc *tbd);
2345void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
2346void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
2347#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
2348#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
2349#else
2350#define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
2351#define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
2352#endif
2353
2354#ifdef QL_IB_DUMP
2355void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
2356#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
2357#else
2358#define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
2359#endif
2360
2361#ifdef QL_ALL_DUMP
2362void ql_dump_all(struct ql_adapter *qdev);
2363#define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
2364#else
2365#define QL_DUMP_ALL(qdev)
2366#endif
2367
2368#endif
2369