1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Driver for Realtek PCI-Express card reader 4 * 5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 6 * 7 * Author: 8 * Wei WANG (wei_wang@realsil.com.cn) 9 * Micky Ching (micky_ching@realsil.com.cn) 10 */ 11 12#ifndef __REALTEK_RTSX_XD_H 13#define __REALTEK_RTSX_XD_H 14 15#define XD_DELAY_WRITE 16 17/* Error Codes */ 18#define XD_NO_ERROR 0x00 19#define XD_NO_MEMORY 0x80 20#define XD_PRG_ERROR 0x40 21#define XD_NO_CARD 0x20 22#define XD_READ_FAIL 0x10 23#define XD_ERASE_FAIL 0x08 24#define XD_WRITE_FAIL 0x04 25#define XD_ECC_ERROR 0x02 26#define XD_TO_ERROR 0x01 27 28/* XD Commands */ 29#define READ1_1 0x00 30#define READ1_2 0x01 31#define READ2 0x50 32#define READ_ID 0x90 33#define RESET 0xff 34#define PAGE_PRG_1 0x80 35#define PAGE_PRG_2 0x10 36#define BLK_ERASE_1 0x60 37#define BLK_ERASE_2 0xD0 38#define READ_STS 0x70 39#define READ_XD_ID 0x9A 40#define COPY_BACK_512 0x8A 41#define COPY_BACK_2K 0x85 42#define READ1_1_2 0x30 43#define READ1_1_3 0x35 44#define CHG_DAT_OUT_1 0x05 45#define RDM_DAT_OUT_1 0x05 46#define CHG_DAT_OUT_2 0xE0 47#define RDM_DAT_OUT_2 0xE0 48#define CHG_DAT_OUT_2 0xE0 49#define CHG_DAT_IN_1 0x85 50#define CACHE_PRG 0x15 51 52/* Redundant Area Related */ 53#define XD_EXTRA_SIZE 0x10 54#define XD_2K_EXTRA_SIZE 0x40 55 56#define NOT_WRITE_PROTECTED 0x80 57#define READY_STATE 0x40 58#define PROGRAM_ERROR 0x01 59#define PROGRAM_ERROR_N_1 0x02 60#define INTERNAL_READY 0x20 61#define READY_FLAG 0x5F 62 63#define XD_8M_X8_512 0xE6 64#define XD_16M_X8_512 0x73 65#define XD_32M_X8_512 0x75 66#define XD_64M_X8_512 0x76 67#define XD_128M_X8_512 0x79 68#define XD_256M_X8_512 0x71 69#define XD_128M_X8_2048 0xF1 70#define XD_256M_X8_2048 0xDA 71#define XD_512M_X8 0xDC 72#define XD_128M_X16_2048 0xC1 73#define XD_4M_X8_512_1 0xE3 74#define XD_4M_X8_512_2 0xE5 75#define XD_1G_X8_512 0xD3 76#define XD_2G_X8_512 0xD5 77 78#define XD_ID_CODE 0xB5 79 80#define VENDOR_BLOCK 0xEFFF 81#define CIS_BLOCK 0xDFFF 82 83#define BLK_NOT_FOUND 0xFFFFFFFF 84 85#define NO_NEW_BLK 0xFFFFFFFF 86 87#define PAGE_CORRECTABLE 0x0 88#define PAGE_NOTCORRECTABLE 0x1 89 90#define NO_OFFSET 0x0 91#define WITH_OFFSET 0x1 92 93#define SECT_PER_PAGE 4 94#define XD_ADDR_MODE_2C XD_ADDR_MODE_2A 95 96#define ZONE0_BAD_BLOCK 23 97#define NOT_ZONE0_BAD_BLOCK 24 98 99#define XD_RW_ADDR 0x01 100#define XD_ERASE_ADDR 0x02 101 102#define XD_PAGE_512(xd_card) \ 103do { \ 104 (xd_card)->block_shift = 5; \ 105 (xd_card)->page_off = 0x1F; \ 106} while (0) 107 108#define XD_SET_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag |= 0x01) 109#define XD_CLR_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag &= ~0x01) 110#define XD_CHK_BAD_NEWBLK(xd_card) ((xd_card)->multi_flag & 0x01) 111 112#define XD_SET_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag |= 0x02) 113#define XD_CLR_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag &= ~0x02) 114#define XD_CHK_BAD_OLDBLK(xd_card) ((xd_card)->multi_flag & 0x02) 115 116#define XD_SET_MBR_FAIL(xd_card) ((xd_card)->multi_flag |= 0x04) 117#define XD_CLR_MBR_FAIL(xd_card) ((xd_card)->multi_flag &= ~0x04) 118#define XD_CHK_MBR_FAIL(xd_card) ((xd_card)->multi_flag & 0x04) 119 120#define XD_SET_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag |= 0x08) 121#define XD_CLR_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag &= ~0x08) 122#define XD_CHK_ECC_FLD_ERR(xd_card) ((xd_card)->multi_flag & 0x08) 123 124#define XD_SET_4MB(xd_card) ((xd_card)->multi_flag |= 0x10) 125#define XD_CLR_4MB(xd_card) ((xd_card)->multi_flag &= ~0x10) 126#define XD_CHK_4MB(xd_card) ((xd_card)->multi_flag & 0x10) 127 128#define XD_SET_ECC_ERR(xd_card) ((xd_card)->multi_flag |= 0x40) 129#define XD_CLR_ECC_ERR(xd_card) ((xd_card)->multi_flag &= ~0x40) 130#define XD_CHK_ECC_ERR(xd_card) ((xd_card)->multi_flag & 0x40) 131 132#define PAGE_STATUS 0 133#define BLOCK_STATUS 1 134#define BLOCK_ADDR1_L 2 135#define BLOCK_ADDR1_H 3 136#define BLOCK_ADDR2_L 4 137#define BLOCK_ADDR2_H 5 138#define RESERVED0 6 139#define RESERVED1 7 140#define RESERVED2 8 141#define RESERVED3 9 142#define PARITY 10 143 144#define CIS0_0 0 145#define CIS0_1 1 146#define CIS0_2 2 147#define CIS0_3 3 148#define CIS0_4 4 149#define CIS0_5 5 150#define CIS0_6 6 151#define CIS0_7 7 152#define CIS0_8 8 153#define CIS0_9 9 154#define CIS1_0 256 155#define CIS1_1 (256 + 1) 156#define CIS1_2 (256 + 2) 157#define CIS1_3 (256 + 3) 158#define CIS1_4 (256 + 4) 159#define CIS1_5 (256 + 5) 160#define CIS1_6 (256 + 6) 161#define CIS1_7 (256 + 7) 162#define CIS1_8 (256 + 8) 163#define CIS1_9 (256 + 9) 164 165int reset_xd_card(struct rtsx_chip *chip); 166#ifdef XD_DELAY_WRITE 167int xd_delay_write(struct rtsx_chip *chip); 168#endif 169int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 170 u32 start_sector, u16 sector_cnt); 171void xd_free_l2p_tbl(struct rtsx_chip *chip); 172void xd_cleanup_work(struct rtsx_chip *chip); 173int xd_power_off_card3v3(struct rtsx_chip *chip); 174int release_xd_card(struct rtsx_chip *chip); 175 176#endif /* __REALTEK_RTSX_XD_H */ 177