LXR linux/drivers/thermal/qcom/tsens.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef __QCOM_TSENS_H__
   7#define __QCOM_TSENS_H__
   8
   9#define ONE_PT_CALIB            0x1
  10#define ONE_PT_CALIB2           0x2
  11#define TWO_PT_CALIB            0x3
  12#define CAL_DEGC_PT1            30
  13#define CAL_DEGC_PT2            120
  14#define SLOPE_FACTOR            1000
  15#define SLOPE_DEFAULT           3200
  16#define THRESHOLD_MAX_ADC_CODE  0x3ff
  17#define THRESHOLD_MIN_ADC_CODE  0x0
  18
  19#include <linux/interrupt.h>
  20#include <linux/thermal.h>
  21#include <linux/regmap.h>
  22#include <linux/slab.h>
  23
  24struct tsens_priv;
  25
  26enum tsens_ver {
  27        VER_0_1 = 0,
  28        VER_1_X,
  29        VER_2_X,
  30};
  31
  32enum tsens_irq_type {
  33        LOWER,
  34        UPPER,
  35};
  36
  37/**
  38 * struct tsens_sensor - data for each sensor connected to the tsens device
  39 * @priv: tsens device instance that this sensor is connected to
  40 * @tzd: pointer to the thermal zone that this sensor is in
  41 * @offset: offset of temperature adjustment curve
  42 * @hw_id: HW ID can be used in case of platform-specific IDs
  43 * @slope: slope of temperature adjustment curve
  44 * @status: 8960-specific variable to track 8960 and 8660 status register offset
  45 */
  46struct tsens_sensor {
  47        struct tsens_priv               *priv;
  48        struct thermal_zone_device      *tzd;
  49        int                             offset;
  50        unsigned int                    hw_id;
  51        int                             slope;
  52        u32                             status;
  53};
  54
  55/**
  56 * struct tsens_ops - operations as supported by the tsens device
  57 * @init: Function to initialize the tsens device
  58 * @calibrate: Function to calibrate the tsens device
  59 * @get_temp: Function which returns the temp in millidegC
  60 * @enable: Function to enable (clocks/power) tsens device
  61 * @disable: Function to disable the tsens device
  62 * @suspend: Function to suspend the tsens device
  63 * @resume: Function to resume the tsens device
  64 * @get_trend: Function to get the thermal/temp trend
  65 */
  66struct tsens_ops {
  67        /* mandatory callbacks */
  68        int (*init)(struct tsens_priv *priv);
  69        int (*calibrate)(struct tsens_priv *priv);
  70        int (*get_temp)(struct tsens_sensor *s, int *temp);
  71        /* optional callbacks */
  72        int (*enable)(struct tsens_priv *priv, int i);
  73        void (*disable)(struct tsens_priv *priv);
  74        int (*suspend)(struct tsens_priv *priv);
  75        int (*resume)(struct tsens_priv *priv);
  76        int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
  77};
  78
  79#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
  80        [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
  81        [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
  82        [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
  83        [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  84        [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
  85        [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
  86        [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
  87        [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
  88        [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
  89        [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
  90        [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit)
  91
  92#define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \
  93        [_name##_##0]  = REG_FIELD(_offset,      _startbit, _stopbit),  \
  94        [_name##_##1]  = REG_FIELD(_offset +  4, _startbit, _stopbit), \
  95        [_name##_##2]  = REG_FIELD(_offset +  8, _startbit, _stopbit), \
  96        [_name##_##3]  = REG_FIELD(_offset + 12, _startbit, _stopbit), \
  97        [_name##_##4]  = REG_FIELD(_offset + 16, _startbit, _stopbit), \
  98        [_name##_##5]  = REG_FIELD(_offset + 20, _startbit, _stopbit), \
  99        [_name##_##6]  = REG_FIELD(_offset + 24, _startbit, _stopbit), \
 100        [_name##_##7]  = REG_FIELD(_offset + 28, _startbit, _stopbit), \
 101        [_name##_##8]  = REG_FIELD(_offset + 32, _startbit, _stopbit), \
 102        [_name##_##9]  = REG_FIELD(_offset + 36, _startbit, _stopbit), \
 103        [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \
 104        [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \
 105        [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \
 106        [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \
 107        [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \
 108        [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit)
 109
 110#define REG_FIELD_SPLIT_BITS_0_15(_name, _offset)               \
 111        [_name##_##0]  = REG_FIELD(_offset,  0,  0),            \
 112        [_name##_##1]  = REG_FIELD(_offset,  1,  1),    \
 113        [_name##_##2]  = REG_FIELD(_offset,  2,  2),    \
 114        [_name##_##3]  = REG_FIELD(_offset,  3,  3),    \
 115        [_name##_##4]  = REG_FIELD(_offset,  4,  4),    \
 116        [_name##_##5]  = REG_FIELD(_offset,  5,  5),    \
 117        [_name##_##6]  = REG_FIELD(_offset,  6,  6),    \
 118        [_name##_##7]  = REG_FIELD(_offset,  7,  7),    \
 119        [_name##_##8]  = REG_FIELD(_offset,  8,  8),    \
 120        [_name##_##9]  = REG_FIELD(_offset,  9,  9),    \
 121        [_name##_##10] = REG_FIELD(_offset, 10, 10),    \
 122        [_name##_##11] = REG_FIELD(_offset, 11, 11),    \
 123        [_name##_##12] = REG_FIELD(_offset, 12, 12),    \
 124        [_name##_##13] = REG_FIELD(_offset, 13, 13),    \
 125        [_name##_##14] = REG_FIELD(_offset, 14, 14),    \
 126        [_name##_##15] = REG_FIELD(_offset, 15, 15)
 127
 128#define REG_FIELD_SPLIT_BITS_16_31(_name, _offset)              \
 129        [_name##_##0]  = REG_FIELD(_offset, 16, 16),            \
 130        [_name##_##1]  = REG_FIELD(_offset, 17, 17),    \
 131        [_name##_##2]  = REG_FIELD(_offset, 18, 18),    \
 132        [_name##_##3]  = REG_FIELD(_offset, 19, 19),    \
 133        [_name##_##4]  = REG_FIELD(_offset, 20, 20),    \
 134        [_name##_##5]  = REG_FIELD(_offset, 21, 21),    \
 135        [_name##_##6]  = REG_FIELD(_offset, 22, 22),    \
 136        [_name##_##7]  = REG_FIELD(_offset, 23, 23),    \
 137        [_name##_##8]  = REG_FIELD(_offset, 24, 24),    \
 138        [_name##_##9]  = REG_FIELD(_offset, 25, 25),    \
 139        [_name##_##10] = REG_FIELD(_offset, 26, 26),    \
 140        [_name##_##11] = REG_FIELD(_offset, 27, 27),    \
 141        [_name##_##12] = REG_FIELD(_offset, 28, 28),    \
 142        [_name##_##13] = REG_FIELD(_offset, 29, 29),    \
 143        [_name##_##14] = REG_FIELD(_offset, 30, 30),    \
 144        [_name##_##15] = REG_FIELD(_offset, 31, 31)
 145
 146/*
 147 * reg_field IDs to use as an index into an array
 148 * If you change the order of the entries, check the devm_regmap_field_alloc()
 149 * calls in init_common()
 150 */
 151enum regfield_ids {
 152        /* ----- SROT ------ */
 153        /* HW_VER */
 154        VER_MAJOR,
 155        VER_MINOR,
 156        VER_STEP,
 157        /* CTRL_OFFSET */
 158        TSENS_EN,
 159        TSENS_SW_RST,
 160        SENSOR_EN,
 161        CODE_OR_TEMP,
 162
 163        /* ----- TM ------ */
 164        /* TRDY */
 165        TRDY,
 166        /* INTERRUPT ENABLE */
 167        INT_EN, /* v2+ has separate enables for crit, upper and lower irq */
 168        /* STATUS */
 169        LAST_TEMP_0,    /* Last temperature reading */
 170        LAST_TEMP_1,
 171        LAST_TEMP_2,
 172        LAST_TEMP_3,
 173        LAST_TEMP_4,
 174        LAST_TEMP_5,
 175        LAST_TEMP_6,
 176        LAST_TEMP_7,
 177        LAST_TEMP_8,
 178        LAST_TEMP_9,
 179        LAST_TEMP_10,
 180        LAST_TEMP_11,
 181        LAST_TEMP_12,
 182        LAST_TEMP_13,
 183        LAST_TEMP_14,
 184        LAST_TEMP_15,
 185        VALID_0,                /* VALID reading or not */
 186        VALID_1,
 187        VALID_2,
 188        VALID_3,
 189        VALID_4,
 190        VALID_5,
 191        VALID_6,
 192        VALID_7,
 193        VALID_8,
 194        VALID_9,
 195        VALID_10,
 196        VALID_11,
 197        VALID_12,
 198        VALID_13,
 199        VALID_14,
 200        VALID_15,
 201        LOWER_STATUS_0, /* LOWER threshold violated */
 202        LOWER_STATUS_1,
 203        LOWER_STATUS_2,
 204        LOWER_STATUS_3,
 205        LOWER_STATUS_4,
 206        LOWER_STATUS_5,
 207        LOWER_STATUS_6,
 208        LOWER_STATUS_7,
 209        LOWER_STATUS_8,
 210        LOWER_STATUS_9,
 211        LOWER_STATUS_10,
 212        LOWER_STATUS_11,
 213        LOWER_STATUS_12,
 214        LOWER_STATUS_13,
 215        LOWER_STATUS_14,
 216        LOWER_STATUS_15,
 217        LOW_INT_STATUS_0,       /* LOWER interrupt status */
 218        LOW_INT_STATUS_1,
 219        LOW_INT_STATUS_2,
 220        LOW_INT_STATUS_3,
 221        LOW_INT_STATUS_4,
 222        LOW_INT_STATUS_5,
 223        LOW_INT_STATUS_6,
 224        LOW_INT_STATUS_7,
 225        LOW_INT_STATUS_8,
 226        LOW_INT_STATUS_9,
 227        LOW_INT_STATUS_10,
 228        LOW_INT_STATUS_11,
 229        LOW_INT_STATUS_12,
 230        LOW_INT_STATUS_13,
 231        LOW_INT_STATUS_14,
 232        LOW_INT_STATUS_15,
 233        LOW_INT_CLEAR_0,        /* LOWER interrupt clear */
 234        LOW_INT_CLEAR_1,
 235        LOW_INT_CLEAR_2,
 236        LOW_INT_CLEAR_3,
 237        LOW_INT_CLEAR_4,
 238        LOW_INT_CLEAR_5,
 239        LOW_INT_CLEAR_6,
 240        LOW_INT_CLEAR_7,
 241        LOW_INT_CLEAR_8,
 242        LOW_INT_CLEAR_9,
 243        LOW_INT_CLEAR_10,
 244        LOW_INT_CLEAR_11,
 245        LOW_INT_CLEAR_12,
 246        LOW_INT_CLEAR_13,
 247        LOW_INT_CLEAR_14,
 248        LOW_INT_CLEAR_15,
 249        LOW_INT_MASK_0, /* LOWER interrupt mask */
 250        LOW_INT_MASK_1,
 251        LOW_INT_MASK_2,
 252        LOW_INT_MASK_3,
 253        LOW_INT_MASK_4,
 254        LOW_INT_MASK_5,
 255        LOW_INT_MASK_6,
 256        LOW_INT_MASK_7,
 257        LOW_INT_MASK_8,
 258        LOW_INT_MASK_9,
 259        LOW_INT_MASK_10,
 260        LOW_INT_MASK_11,
 261        LOW_INT_MASK_12,
 262        LOW_INT_MASK_13,
 263        LOW_INT_MASK_14,
 264        LOW_INT_MASK_15,
 265        LOW_THRESH_0,           /* LOWER threshold values */
 266        LOW_THRESH_1,
 267        LOW_THRESH_2,
 268        LOW_THRESH_3,
 269        LOW_THRESH_4,
 270        LOW_THRESH_5,
 271        LOW_THRESH_6,
 272        LOW_THRESH_7,
 273        LOW_THRESH_8,
 274        LOW_THRESH_9,
 275        LOW_THRESH_10,
 276        LOW_THRESH_11,
 277        LOW_THRESH_12,
 278        LOW_THRESH_13,
 279        LOW_THRESH_14,
 280        LOW_THRESH_15,
 281        UPPER_STATUS_0, /* UPPER threshold violated */
 282        UPPER_STATUS_1,
 283        UPPER_STATUS_2,
 284        UPPER_STATUS_3,
 285        UPPER_STATUS_4,
 286        UPPER_STATUS_5,
 287        UPPER_STATUS_6,
 288        UPPER_STATUS_7,
 289        UPPER_STATUS_8,
 290        UPPER_STATUS_9,
 291        UPPER_STATUS_10,
 292        UPPER_STATUS_11,
 293        UPPER_STATUS_12,
 294        UPPER_STATUS_13,
 295        UPPER_STATUS_14,
 296        UPPER_STATUS_15,
 297        UP_INT_STATUS_0,        /* UPPER interrupt status */
 298        UP_INT_STATUS_1,
 299        UP_INT_STATUS_2,
 300        UP_INT_STATUS_3,
 301        UP_INT_STATUS_4,
 302        UP_INT_STATUS_5,
 303        UP_INT_STATUS_6,
 304        UP_INT_STATUS_7,
 305        UP_INT_STATUS_8,
 306        UP_INT_STATUS_9,
 307        UP_INT_STATUS_10,
 308        UP_INT_STATUS_11,
 309        UP_INT_STATUS_12,
 310        UP_INT_STATUS_13,
 311        UP_INT_STATUS_14,
 312        UP_INT_STATUS_15,
 313        UP_INT_CLEAR_0, /* UPPER interrupt clear */
 314        UP_INT_CLEAR_1,
 315        UP_INT_CLEAR_2,
 316        UP_INT_CLEAR_3,
 317        UP_INT_CLEAR_4,
 318        UP_INT_CLEAR_5,
 319        UP_INT_CLEAR_6,
 320        UP_INT_CLEAR_7,
 321        UP_INT_CLEAR_8,
 322        UP_INT_CLEAR_9,
 323        UP_INT_CLEAR_10,
 324        UP_INT_CLEAR_11,
 325        UP_INT_CLEAR_12,
 326        UP_INT_CLEAR_13,
 327        UP_INT_CLEAR_14,
 328        UP_INT_CLEAR_15,
 329        UP_INT_MASK_0,          /* UPPER interrupt mask */
 330        UP_INT_MASK_1,
 331        UP_INT_MASK_2,
 332        UP_INT_MASK_3,
 333        UP_INT_MASK_4,
 334        UP_INT_MASK_5,
 335        UP_INT_MASK_6,
 336        UP_INT_MASK_7,
 337        UP_INT_MASK_8,
 338        UP_INT_MASK_9,
 339        UP_INT_MASK_10,
 340        UP_INT_MASK_11,
 341        UP_INT_MASK_12,
 342        UP_INT_MASK_13,
 343        UP_INT_MASK_14,
 344        UP_INT_MASK_15,
 345        UP_THRESH_0,            /* UPPER threshold values */
 346        UP_THRESH_1,
 347        UP_THRESH_2,
 348        UP_THRESH_3,
 349        UP_THRESH_4,
 350        UP_THRESH_5,
 351        UP_THRESH_6,
 352        UP_THRESH_7,
 353        UP_THRESH_8,
 354        UP_THRESH_9,
 355        UP_THRESH_10,
 356        UP_THRESH_11,
 357        UP_THRESH_12,
 358        UP_THRESH_13,
 359        UP_THRESH_14,
 360        UP_THRESH_15,
 361        CRITICAL_STATUS_0,      /* CRITICAL threshold violated */
 362        CRITICAL_STATUS_1,
 363        CRITICAL_STATUS_2,
 364        CRITICAL_STATUS_3,
 365        CRITICAL_STATUS_4,
 366        CRITICAL_STATUS_5,
 367        CRITICAL_STATUS_6,
 368        CRITICAL_STATUS_7,
 369        CRITICAL_STATUS_8,
 370        CRITICAL_STATUS_9,
 371        CRITICAL_STATUS_10,
 372        CRITICAL_STATUS_11,
 373        CRITICAL_STATUS_12,
 374        CRITICAL_STATUS_13,
 375        CRITICAL_STATUS_14,
 376        CRITICAL_STATUS_15,
 377        MIN_STATUS_0,           /* MIN threshold violated */
 378        MIN_STATUS_1,
 379        MIN_STATUS_2,
 380        MIN_STATUS_3,
 381        MIN_STATUS_4,
 382        MIN_STATUS_5,
 383        MIN_STATUS_6,
 384        MIN_STATUS_7,
 385        MIN_STATUS_8,
 386        MIN_STATUS_9,
 387        MIN_STATUS_10,
 388        MIN_STATUS_11,
 389        MIN_STATUS_12,
 390        MIN_STATUS_13,
 391        MIN_STATUS_14,
 392        MIN_STATUS_15,
 393        MAX_STATUS_0,           /* MAX threshold violated */
 394        MAX_STATUS_1,
 395        MAX_STATUS_2,
 396        MAX_STATUS_3,
 397        MAX_STATUS_4,
 398        MAX_STATUS_5,
 399        MAX_STATUS_6,
 400        MAX_STATUS_7,
 401        MAX_STATUS_8,
 402        MAX_STATUS_9,
 403        MAX_STATUS_10,
 404        MAX_STATUS_11,
 405        MAX_STATUS_12,
 406        MAX_STATUS_13,
 407        MAX_STATUS_14,
 408        MAX_STATUS_15,
 409
 410        /* Keep last */
 411        MAX_REGFIELDS
 412};
 413
 414/**
 415 * struct tsens_features - Features supported by the IP
 416 * @ver_major: Major number of IP version
 417 * @crit_int: does the IP support critical interrupts?
 418 * @adc:      do the sensors only output adc code (instead of temperature)?
 419 * @srot_split: does the IP neatly splits the register space into SROT and TM,
 420 *              with SROT only being available to secure boot firmware?
 421 * @max_sensors: maximum sensors supported by this version of the IP
 422 */
 423struct tsens_features {
 424        unsigned int ver_major;
 425        unsigned int crit_int:1;
 426        unsigned int adc:1;
 427        unsigned int srot_split:1;
 428        unsigned int max_sensors;
 429};
 430
 431/**
 432 * struct tsens_plat_data - tsens compile-time platform data
 433 * @num_sensors: Number of sensors supported by platform
 434 * @ops: operations the tsens instance supports
 435 * @hw_ids: Subset of sensors ids supported by platform, if not the first n
 436 * @feat: features of the IP
 437 * @fields: bitfield locations
 438 */
 439struct tsens_plat_data {
 440        const u32               num_sensors;
 441        const struct tsens_ops  *ops;
 442        unsigned int            *hw_ids;
 443        const struct tsens_features     *feat;
 444        const struct reg_field          *fields;
 445};
 446
 447/**
 448 * struct tsens_context - Registers to be saved/restored across a context loss
 449 */
 450struct tsens_context {
 451        int     threshold;
 452        int     control;
 453};
 454
 455/**
 456 * struct tsens_priv - private data for each instance of the tsens IP
 457 * @dev: pointer to struct device
 458 * @num_sensors: number of sensors enabled on this device
 459 * @tm_map: pointer to TM register address space
 460 * @srot_map: pointer to SROT register address space
 461 * @tm_offset: deal with old device trees that don't address TM and SROT
 462 *             address space separately
 463 * @rf: array of regmap_fields used to store value of the field
 464 * @ctx: registers to be saved and restored during suspend/resume
 465 * @feat: features of the IP
 466 * @fields: bitfield locations
 467 * @ops: pointer to list of callbacks supported by this device
 468 * @debug_root: pointer to debugfs dentry for all tsens
 469 * @debug: pointer to debugfs dentry for tsens controller
 470 * @sensor: list of sensors attached to this device
 471 */
 472struct tsens_priv {
 473        struct device                   *dev;
 474        u32                             num_sensors;
 475        struct regmap                   *tm_map;
 476        struct regmap                   *srot_map;
 477        u32                             tm_offset;
 478
 479        /* lock for upper/lower threshold interrupts */
 480        spinlock_t                      ul_lock;
 481
 482        struct regmap_field             *rf[MAX_REGFIELDS];
 483        struct tsens_context            ctx;
 484        const struct tsens_features     *feat;
 485        const struct reg_field          *fields;
 486        const struct tsens_ops          *ops;
 487
 488        struct dentry                   *debug_root;
 489        struct dentry                   *debug;
 490
 491        struct tsens_sensor             sensor[0];
 492};
 493
 494char *qfprom_read(struct device *dev, const char *cname);
 495void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode);
 496int init_common(struct tsens_priv *priv);
 497int get_temp_tsens_valid(struct tsens_sensor *s, int *temp);
 498int get_temp_common(struct tsens_sensor *s, int *temp);
 499int tsens_enable_irq(struct tsens_priv *priv);
 500void tsens_disable_irq(struct tsens_priv *priv);
 501int tsens_set_trips(void *_sensor, int low, int high);
 502irqreturn_t tsens_irq_thread(int irq, void *data);
 503
 504/* TSENS target */
 505extern const struct tsens_plat_data data_8960;
 506
 507/* TSENS v0.1 targets */
 508extern const struct tsens_plat_data data_8916, data_8974;
 509
 510/* TSENS v1 targets */
 511extern const struct tsens_plat_data data_tsens_v1, data_8976;
 512
 513/* TSENS v2 targets */
 514extern const struct tsens_plat_data data_8996, data_tsens_v2;
 515
 516#endif /* __QCOM_TSENS_H__ */
 517