linux/drivers/tty/synclinkmp.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-1.0+
   2/*
   3 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   4 *
   5 * Device driver for Microgate SyncLink Multiport
   6 * high speed multiprotocol serial adapter.
   7 *
   8 * written by Paul Fulghum for Microgate Corporation
   9 * paulkf@microgate.com
  10 *
  11 * Microgate and SyncLink are trademarks of Microgate Corporation
  12 *
  13 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  14 *
  15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25 * OF THE POSSIBILITY OF SUCH DAMAGE.
  26 */
  27
  28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29#if defined(__i386__)
  30#  define BREAKPOINT() asm("   int $3");
  31#else
  32#  define BREAKPOINT() { }
  33#endif
  34
  35#define MAX_DEVICES 12
  36
  37#include <linux/module.h>
  38#include <linux/errno.h>
  39#include <linux/signal.h>
  40#include <linux/sched.h>
  41#include <linux/timer.h>
  42#include <linux/interrupt.h>
  43#include <linux/pci.h>
  44#include <linux/tty.h>
  45#include <linux/tty_flip.h>
  46#include <linux/serial.h>
  47#include <linux/major.h>
  48#include <linux/string.h>
  49#include <linux/fcntl.h>
  50#include <linux/ptrace.h>
  51#include <linux/ioport.h>
  52#include <linux/mm.h>
  53#include <linux/seq_file.h>
  54#include <linux/slab.h>
  55#include <linux/netdevice.h>
  56#include <linux/vmalloc.h>
  57#include <linux/init.h>
  58#include <linux/delay.h>
  59#include <linux/ioctl.h>
  60
  61#include <asm/io.h>
  62#include <asm/irq.h>
  63#include <asm/dma.h>
  64#include <linux/bitops.h>
  65#include <asm/types.h>
  66#include <linux/termios.h>
  67#include <linux/workqueue.h>
  68#include <linux/hdlc.h>
  69#include <linux/synclink.h>
  70
  71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72#define SYNCLINK_GENERIC_HDLC 1
  73#else
  74#define SYNCLINK_GENERIC_HDLC 0
  75#endif
  76
  77#define GET_USER(error,value,addr) error = get_user(value,addr)
  78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79#define PUT_USER(error,value,addr) error = put_user(value,addr)
  80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82#include <linux/uaccess.h>
  83
  84static MGSL_PARAMS default_params = {
  85        MGSL_MODE_HDLC,                 /* unsigned long mode */
  86        0,                              /* unsigned char loopback; */
  87        HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88        HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89        0,                              /* unsigned long clock_speed; */
  90        0xff,                           /* unsigned char addr_filter; */
  91        HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92        HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93        HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94        9600,                           /* unsigned long data_rate; */
  95        8,                              /* unsigned char data_bits; */
  96        1,                              /* unsigned char stop_bits; */
  97        ASYNC_PARITY_NONE               /* unsigned char parity; */
  98};
  99
 100/* size in bytes of DMA data buffers */
 101#define SCABUFSIZE      1024
 102#define SCA_MEM_SIZE    0x40000
 103#define SCA_BASE_SIZE   512
 104#define SCA_REG_SIZE    16
 105#define SCA_MAX_PORTS   4
 106#define SCAMAXDESC      128
 107
 108#define BUFFERLISTSIZE  4096
 109
 110/* SCA-I style DMA buffer descriptor */
 111typedef struct _SCADESC
 112{
 113        u16     next;           /* lower l6 bits of next descriptor addr */
 114        u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115        u8      buf_base;       /* upper 8 bits of buffer addr */
 116        u8      pad1;
 117        u16     length;         /* length of buffer */
 118        u8      status;         /* status of buffer */
 119        u8      pad2;
 120} SCADESC, *PSCADESC;
 121
 122typedef struct _SCADESC_EX
 123{
 124        /* device driver bookkeeping section */
 125        char    *virt_addr;     /* virtual address of data buffer */
 126        u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127} SCADESC_EX, *PSCADESC_EX;
 128
 129/* The queue of BH actions to be performed */
 130
 131#define BH_RECEIVE  1
 132#define BH_TRANSMIT 2
 133#define BH_STATUS   4
 134
 135#define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137struct  _input_signal_events {
 138        int     ri_up;
 139        int     ri_down;
 140        int     dsr_up;
 141        int     dsr_down;
 142        int     dcd_up;
 143        int     dcd_down;
 144        int     cts_up;
 145        int     cts_down;
 146};
 147
 148/*
 149 * Device instance data structure
 150 */
 151typedef struct _synclinkmp_info {
 152        void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153        int                     magic;
 154        struct tty_port         port;
 155        int                     line;
 156        unsigned short          close_delay;
 157        unsigned short          closing_wait;   /* time to wait before closing */
 158
 159        struct mgsl_icount      icount;
 160
 161        int                     timeout;
 162        int                     x_char;         /* xon/xoff character */
 163        u16                     read_status_mask1;  /* break detection (SR1 indications) */
 164        u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 165        unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 166        unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 167        unsigned char           *tx_buf;
 168        int                     tx_put;
 169        int                     tx_get;
 170        int                     tx_count;
 171
 172        wait_queue_head_t       status_event_wait_q;
 173        wait_queue_head_t       event_wait_q;
 174        struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 175        struct _synclinkmp_info *next_device;   /* device list link */
 176        struct timer_list       status_timer;   /* input signal status check timer */
 177
 178        spinlock_t lock;                /* spinlock for synchronizing with ISR */
 179        struct work_struct task;                        /* task structure for scheduling bh */
 180
 181        u32 max_frame_size;                     /* as set by device config */
 182
 183        u32 pending_bh;
 184
 185        bool bh_running;                                /* Protection from multiple */
 186        int isr_overflow;
 187        bool bh_requested;
 188
 189        int dcd_chkcount;                       /* check counts to prevent */
 190        int cts_chkcount;                       /* too many IRQs if a signal */
 191        int dsr_chkcount;                       /* is floating */
 192        int ri_chkcount;
 193
 194        char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 195        unsigned long buffer_list_phys;
 196
 197        unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 198        SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 199        SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 200        unsigned int current_rx_buf;
 201
 202        unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 203        SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 204        SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 205        unsigned int last_tx_buf;
 206
 207        unsigned char *tmp_rx_buf;
 208        unsigned int tmp_rx_buf_count;
 209
 210        bool rx_enabled;
 211        bool rx_overflow;
 212
 213        bool tx_enabled;
 214        bool tx_active;
 215        u32 idle_mode;
 216
 217        unsigned char ie0_value;
 218        unsigned char ie1_value;
 219        unsigned char ie2_value;
 220        unsigned char ctrlreg_value;
 221        unsigned char old_signals;
 222
 223        char device_name[25];                   /* device instance name */
 224
 225        int port_count;
 226        int adapter_num;
 227        int port_num;
 228
 229        struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 230
 231        unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 232
 233        unsigned int irq_level;                 /* interrupt level */
 234        unsigned long irq_flags;
 235        bool irq_requested;                     /* true if IRQ requested */
 236
 237        MGSL_PARAMS params;                     /* communications parameters */
 238
 239        unsigned char serial_signals;           /* current serial signal states */
 240
 241        bool irq_occurred;                      /* for diagnostics use */
 242        unsigned int init_error;                /* Initialization startup error */
 243
 244        u32 last_mem_alloc;
 245        unsigned char* memory_base;             /* shared memory address (PCI only) */
 246        u32 phys_memory_base;
 247        int shared_mem_requested;
 248
 249        unsigned char* sca_base;                /* HD64570 SCA Memory address */
 250        u32 phys_sca_base;
 251        u32 sca_offset;
 252        bool sca_base_requested;
 253
 254        unsigned char* lcr_base;                /* local config registers (PCI only) */
 255        u32 phys_lcr_base;
 256        u32 lcr_offset;
 257        int lcr_mem_requested;
 258
 259        unsigned char* statctrl_base;           /* status/control register memory */
 260        u32 phys_statctrl_base;
 261        u32 statctrl_offset;
 262        bool sca_statctrl_requested;
 263
 264        u32 misc_ctrl_value;
 265        char *flag_buf;
 266        bool drop_rts_on_tx_done;
 267
 268        struct  _input_signal_events    input_signal_events;
 269
 270        /* SPPP/Cisco HDLC device parts */
 271        int netcount;
 272        spinlock_t netlock;
 273
 274#if SYNCLINK_GENERIC_HDLC
 275        struct net_device *netdev;
 276#endif
 277
 278} SLMP_INFO;
 279
 280#define MGSL_MAGIC 0x5401
 281
 282/*
 283 * define serial signal status change macros
 284 */
 285#define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 286#define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 287#define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 288#define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 289
 290/* Common Register macros */
 291#define LPR     0x00
 292#define PABR0   0x02
 293#define PABR1   0x03
 294#define WCRL    0x04
 295#define WCRM    0x05
 296#define WCRH    0x06
 297#define DPCR    0x08
 298#define DMER    0x09
 299#define ISR0    0x10
 300#define ISR1    0x11
 301#define ISR2    0x12
 302#define IER0    0x14
 303#define IER1    0x15
 304#define IER2    0x16
 305#define ITCR    0x18
 306#define INTVR   0x1a
 307#define IMVR    0x1c
 308
 309/* MSCI Register macros */
 310#define TRB     0x20
 311#define TRBL    0x20
 312#define TRBH    0x21
 313#define SR0     0x22
 314#define SR1     0x23
 315#define SR2     0x24
 316#define SR3     0x25
 317#define FST     0x26
 318#define IE0     0x28
 319#define IE1     0x29
 320#define IE2     0x2a
 321#define FIE     0x2b
 322#define CMD     0x2c
 323#define MD0     0x2e
 324#define MD1     0x2f
 325#define MD2     0x30
 326#define CTL     0x31
 327#define SA0     0x32
 328#define SA1     0x33
 329#define IDL     0x34
 330#define TMC     0x35
 331#define RXS     0x36
 332#define TXS     0x37
 333#define TRC0    0x38
 334#define TRC1    0x39
 335#define RRC     0x3a
 336#define CST0    0x3c
 337#define CST1    0x3d
 338
 339/* Timer Register Macros */
 340#define TCNT    0x60
 341#define TCNTL   0x60
 342#define TCNTH   0x61
 343#define TCONR   0x62
 344#define TCONRL  0x62
 345#define TCONRH  0x63
 346#define TMCS    0x64
 347#define TEPR    0x65
 348
 349/* DMA Controller Register macros */
 350#define DARL    0x80
 351#define DARH    0x81
 352#define DARB    0x82
 353#define BAR     0x80
 354#define BARL    0x80
 355#define BARH    0x81
 356#define BARB    0x82
 357#define SAR     0x84
 358#define SARL    0x84
 359#define SARH    0x85
 360#define SARB    0x86
 361#define CPB     0x86
 362#define CDA     0x88
 363#define CDAL    0x88
 364#define CDAH    0x89
 365#define EDA     0x8a
 366#define EDAL    0x8a
 367#define EDAH    0x8b
 368#define BFL     0x8c
 369#define BFLL    0x8c
 370#define BFLH    0x8d
 371#define BCR     0x8e
 372#define BCRL    0x8e
 373#define BCRH    0x8f
 374#define DSR     0x90
 375#define DMR     0x91
 376#define FCT     0x93
 377#define DIR     0x94
 378#define DCMD    0x95
 379
 380/* combine with timer or DMA register address */
 381#define TIMER0  0x00
 382#define TIMER1  0x08
 383#define TIMER2  0x10
 384#define TIMER3  0x18
 385#define RXDMA   0x00
 386#define TXDMA   0x20
 387
 388/* SCA Command Codes */
 389#define NOOP            0x00
 390#define TXRESET         0x01
 391#define TXENABLE        0x02
 392#define TXDISABLE       0x03
 393#define TXCRCINIT       0x04
 394#define TXCRCEXCL       0x05
 395#define TXEOM           0x06
 396#define TXABORT         0x07
 397#define MPON            0x08
 398#define TXBUFCLR        0x09
 399#define RXRESET         0x11
 400#define RXENABLE        0x12
 401#define RXDISABLE       0x13
 402#define RXCRCINIT       0x14
 403#define RXREJECT        0x15
 404#define SEARCHMP        0x16
 405#define RXCRCEXCL       0x17
 406#define RXCRCCALC       0x18
 407#define CHRESET         0x21
 408#define HUNT            0x31
 409
 410/* DMA command codes */
 411#define SWABORT         0x01
 412#define FEICLEAR        0x02
 413
 414/* IE0 */
 415#define TXINTE          BIT7
 416#define RXINTE          BIT6
 417#define TXRDYE          BIT1
 418#define RXRDYE          BIT0
 419
 420/* IE1 & SR1 */
 421#define UDRN    BIT7
 422#define IDLE    BIT6
 423#define SYNCD   BIT4
 424#define FLGD    BIT4
 425#define CCTS    BIT3
 426#define CDCD    BIT2
 427#define BRKD    BIT1
 428#define ABTD    BIT1
 429#define GAPD    BIT1
 430#define BRKE    BIT0
 431#define IDLD    BIT0
 432
 433/* IE2 & SR2 */
 434#define EOM     BIT7
 435#define PMP     BIT6
 436#define SHRT    BIT6
 437#define PE      BIT5
 438#define ABT     BIT5
 439#define FRME    BIT4
 440#define RBIT    BIT4
 441#define OVRN    BIT3
 442#define CRCE    BIT2
 443
 444
 445/*
 446 * Global linked list of SyncLink devices
 447 */
 448static SLMP_INFO *synclinkmp_device_list = NULL;
 449static int synclinkmp_adapter_count = -1;
 450static int synclinkmp_device_count = 0;
 451
 452/*
 453 * Set this param to non-zero to load eax with the
 454 * .text section address and breakpoint on module load.
 455 * This is useful for use with gdb and add-symbol-file command.
 456 */
 457static bool break_on_load = 0;
 458
 459/*
 460 * Driver major number, defaults to zero to get auto
 461 * assigned major number. May be forced as module parameter.
 462 */
 463static int ttymajor = 0;
 464
 465/*
 466 * Array of user specified options for ISA adapters.
 467 */
 468static int debug_level = 0;
 469static int maxframe[MAX_DEVICES] = {0,};
 470
 471module_param(break_on_load, bool, 0);
 472module_param(ttymajor, int, 0);
 473module_param(debug_level, int, 0);
 474module_param_array(maxframe, int, NULL, 0);
 475
 476static char *driver_name = "SyncLink MultiPort driver";
 477static char *driver_version = "$Revision: 4.38 $";
 478
 479static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 480static void synclinkmp_remove_one(struct pci_dev *dev);
 481
 482static const struct pci_device_id synclinkmp_pci_tbl[] = {
 483        { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 484        { 0, }, /* terminate list */
 485};
 486MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 487
 488MODULE_LICENSE("GPL");
 489
 490static struct pci_driver synclinkmp_pci_driver = {
 491        .name           = "synclinkmp",
 492        .id_table       = synclinkmp_pci_tbl,
 493        .probe          = synclinkmp_init_one,
 494        .remove         = synclinkmp_remove_one,
 495};
 496
 497
 498static struct tty_driver *serial_driver;
 499
 500/* number of characters left in xmit buffer before we ask for more */
 501#define WAKEUP_CHARS 256
 502
 503
 504/* tty callbacks */
 505
 506static int  open(struct tty_struct *tty, struct file * filp);
 507static void close(struct tty_struct *tty, struct file * filp);
 508static void hangup(struct tty_struct *tty);
 509static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 510
 511static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 512static int put_char(struct tty_struct *tty, unsigned char ch);
 513static void send_xchar(struct tty_struct *tty, char ch);
 514static void wait_until_sent(struct tty_struct *tty, int timeout);
 515static int  write_room(struct tty_struct *tty);
 516static void flush_chars(struct tty_struct *tty);
 517static void flush_buffer(struct tty_struct *tty);
 518static void tx_hold(struct tty_struct *tty);
 519static void tx_release(struct tty_struct *tty);
 520
 521static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 522static int  chars_in_buffer(struct tty_struct *tty);
 523static void throttle(struct tty_struct * tty);
 524static void unthrottle(struct tty_struct * tty);
 525static int set_break(struct tty_struct *tty, int break_state);
 526
 527#if SYNCLINK_GENERIC_HDLC
 528#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 529static void hdlcdev_tx_done(SLMP_INFO *info);
 530static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 531static int  hdlcdev_init(SLMP_INFO *info);
 532static void hdlcdev_exit(SLMP_INFO *info);
 533#endif
 534
 535/* ioctl handlers */
 536
 537static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 538static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 539static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 540static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 541static int  set_txidle(SLMP_INFO *info, int idle_mode);
 542static int  tx_enable(SLMP_INFO *info, int enable);
 543static int  tx_abort(SLMP_INFO *info);
 544static int  rx_enable(SLMP_INFO *info, int enable);
 545static int  modem_input_wait(SLMP_INFO *info,int arg);
 546static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 547static int  tiocmget(struct tty_struct *tty);
 548static int  tiocmset(struct tty_struct *tty,
 549                        unsigned int set, unsigned int clear);
 550static int  set_break(struct tty_struct *tty, int break_state);
 551
 552static int  add_device(SLMP_INFO *info);
 553static int  device_init(int adapter_num, struct pci_dev *pdev);
 554static int  claim_resources(SLMP_INFO *info);
 555static void release_resources(SLMP_INFO *info);
 556
 557static int  startup(SLMP_INFO *info);
 558static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 559static int carrier_raised(struct tty_port *port);
 560static void shutdown(SLMP_INFO *info);
 561static void program_hw(SLMP_INFO *info);
 562static void change_params(SLMP_INFO *info);
 563
 564static bool init_adapter(SLMP_INFO *info);
 565static bool register_test(SLMP_INFO *info);
 566static bool irq_test(SLMP_INFO *info);
 567static bool loopback_test(SLMP_INFO *info);
 568static int  adapter_test(SLMP_INFO *info);
 569static bool memory_test(SLMP_INFO *info);
 570
 571static void reset_adapter(SLMP_INFO *info);
 572static void reset_port(SLMP_INFO *info);
 573static void async_mode(SLMP_INFO *info);
 574static void hdlc_mode(SLMP_INFO *info);
 575
 576static void rx_stop(SLMP_INFO *info);
 577static void rx_start(SLMP_INFO *info);
 578static void rx_reset_buffers(SLMP_INFO *info);
 579static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 580static bool rx_get_frame(SLMP_INFO *info);
 581
 582static void tx_start(SLMP_INFO *info);
 583static void tx_stop(SLMP_INFO *info);
 584static void tx_load_fifo(SLMP_INFO *info);
 585static void tx_set_idle(SLMP_INFO *info);
 586static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 587
 588static void get_signals(SLMP_INFO *info);
 589static void set_signals(SLMP_INFO *info);
 590static void enable_loopback(SLMP_INFO *info, int enable);
 591static void set_rate(SLMP_INFO *info, u32 data_rate);
 592
 593static int  bh_action(SLMP_INFO *info);
 594static void bh_handler(struct work_struct *work);
 595static void bh_receive(SLMP_INFO *info);
 596static void bh_transmit(SLMP_INFO *info);
 597static void bh_status(SLMP_INFO *info);
 598static void isr_timer(SLMP_INFO *info);
 599static void isr_rxint(SLMP_INFO *info);
 600static void isr_rxrdy(SLMP_INFO *info);
 601static void isr_txint(SLMP_INFO *info);
 602static void isr_txrdy(SLMP_INFO *info);
 603static void isr_rxdmaok(SLMP_INFO *info);
 604static void isr_rxdmaerror(SLMP_INFO *info);
 605static void isr_txdmaok(SLMP_INFO *info);
 606static void isr_txdmaerror(SLMP_INFO *info);
 607static void isr_io_pin(SLMP_INFO *info, u16 status);
 608
 609static int  alloc_dma_bufs(SLMP_INFO *info);
 610static void free_dma_bufs(SLMP_INFO *info);
 611static int  alloc_buf_list(SLMP_INFO *info);
 612static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 613static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 614static void free_tmp_rx_buf(SLMP_INFO *info);
 615
 616static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 617static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 618static void tx_timeout(struct timer_list *t);
 619static void status_timeout(struct timer_list *t);
 620
 621static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 622static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 623static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 624static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 625static unsigned char read_status_reg(SLMP_INFO * info);
 626static void write_control_reg(SLMP_INFO * info);
 627
 628
 629static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 630static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 631static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 632
 633static u32 misc_ctrl_value = 0x007e4040;
 634static u32 lcr1_brdr_value = 0x00800028;
 635
 636static u32 read_ahead_count = 8;
 637
 638/* DPCR, DMA Priority Control
 639 *
 640 * 07..05  Not used, must be 0
 641 * 04      BRC, bus release condition: 0=all transfers complete
 642 *              1=release after 1 xfer on all channels
 643 * 03      CCC, channel change condition: 0=every cycle
 644 *              1=after each channel completes all xfers
 645 * 02..00  PR<2..0>, priority 100=round robin
 646 *
 647 * 00000100 = 0x00
 648 */
 649static unsigned char dma_priority = 0x04;
 650
 651// Number of bytes that can be written to shared RAM
 652// in a single write operation
 653static u32 sca_pci_load_interval = 64;
 654
 655/*
 656 * 1st function defined in .text section. Calling this function in
 657 * init_module() followed by a breakpoint allows a remote debugger
 658 * (gdb) to get the .text address for the add-symbol-file command.
 659 * This allows remote debugging of dynamically loadable modules.
 660 */
 661static void* synclinkmp_get_text_ptr(void);
 662static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 663
 664static inline int sanity_check(SLMP_INFO *info,
 665                               char *name, const char *routine)
 666{
 667#ifdef SANITY_CHECK
 668        static const char *badmagic =
 669                "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 670        static const char *badinfo =
 671                "Warning: null synclinkmp_struct for (%s) in %s\n";
 672
 673        if (!info) {
 674                printk(badinfo, name, routine);
 675                return 1;
 676        }
 677        if (info->magic != MGSL_MAGIC) {
 678                printk(badmagic, name, routine);
 679                return 1;
 680        }
 681#else
 682        if (!info)
 683                return 1;
 684#endif
 685        return 0;
 686}
 687
 688/**
 689 * line discipline callback wrappers
 690 *
 691 * The wrappers maintain line discipline references
 692 * while calling into the line discipline.
 693 *
 694 * ldisc_receive_buf  - pass receive data to line discipline
 695 */
 696
 697static void ldisc_receive_buf(struct tty_struct *tty,
 698                              const __u8 *data, char *flags, int count)
 699{
 700        struct tty_ldisc *ld;
 701        if (!tty)
 702                return;
 703        ld = tty_ldisc_ref(tty);
 704        if (ld) {
 705                if (ld->ops->receive_buf)
 706                        ld->ops->receive_buf(tty, data, flags, count);
 707                tty_ldisc_deref(ld);
 708        }
 709}
 710
 711/* tty callbacks */
 712
 713static int install(struct tty_driver *driver, struct tty_struct *tty)
 714{
 715        SLMP_INFO *info;
 716        int line = tty->index;
 717
 718        if (line >= synclinkmp_device_count) {
 719                printk("%s(%d): open with invalid line #%d.\n",
 720                        __FILE__,__LINE__,line);
 721                return -ENODEV;
 722        }
 723
 724        info = synclinkmp_device_list;
 725        while (info && info->line != line)
 726                info = info->next_device;
 727        if (sanity_check(info, tty->name, "open"))
 728                return -ENODEV;
 729        if (info->init_error) {
 730                printk("%s(%d):%s device is not allocated, init error=%d\n",
 731                        __FILE__, __LINE__, info->device_name,
 732                        info->init_error);
 733                return -ENODEV;
 734        }
 735
 736        tty->driver_data = info;
 737
 738        return tty_port_install(&info->port, driver, tty);
 739}
 740
 741/* Called when a port is opened.  Init and enable port.
 742 */
 743static int open(struct tty_struct *tty, struct file *filp)
 744{
 745        SLMP_INFO *info = tty->driver_data;
 746        unsigned long flags;
 747        int retval;
 748
 749        info->port.tty = tty;
 750
 751        if (debug_level >= DEBUG_LEVEL_INFO)
 752                printk("%s(%d):%s open(), old ref count = %d\n",
 753                         __FILE__,__LINE__,tty->driver->name, info->port.count);
 754
 755        info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 756
 757        spin_lock_irqsave(&info->netlock, flags);
 758        if (info->netcount) {
 759                retval = -EBUSY;
 760                spin_unlock_irqrestore(&info->netlock, flags);
 761                goto cleanup;
 762        }
 763        info->port.count++;
 764        spin_unlock_irqrestore(&info->netlock, flags);
 765
 766        if (info->port.count == 1) {
 767                /* 1st open on this device, init hardware */
 768                retval = startup(info);
 769                if (retval < 0)
 770                        goto cleanup;
 771        }
 772
 773        retval = block_til_ready(tty, filp, info);
 774        if (retval) {
 775                if (debug_level >= DEBUG_LEVEL_INFO)
 776                        printk("%s(%d):%s block_til_ready() returned %d\n",
 777                                 __FILE__,__LINE__, info->device_name, retval);
 778                goto cleanup;
 779        }
 780
 781        if (debug_level >= DEBUG_LEVEL_INFO)
 782                printk("%s(%d):%s open() success\n",
 783                         __FILE__,__LINE__, info->device_name);
 784        retval = 0;
 785
 786cleanup:
 787        if (retval) {
 788                if (tty->count == 1)
 789                        info->port.tty = NULL; /* tty layer will release tty struct */
 790                if(info->port.count)
 791                        info->port.count--;
 792        }
 793
 794        return retval;
 795}
 796
 797/* Called when port is closed. Wait for remaining data to be
 798 * sent. Disable port and free resources.
 799 */
 800static void close(struct tty_struct *tty, struct file *filp)
 801{
 802        SLMP_INFO * info = tty->driver_data;
 803
 804        if (sanity_check(info, tty->name, "close"))
 805                return;
 806
 807        if (debug_level >= DEBUG_LEVEL_INFO)
 808                printk("%s(%d):%s close() entry, count=%d\n",
 809                         __FILE__,__LINE__, info->device_name, info->port.count);
 810
 811        if (tty_port_close_start(&info->port, tty, filp) == 0)
 812                goto cleanup;
 813
 814        mutex_lock(&info->port.mutex);
 815        if (tty_port_initialized(&info->port))
 816                wait_until_sent(tty, info->timeout);
 817
 818        flush_buffer(tty);
 819        tty_ldisc_flush(tty);
 820        shutdown(info);
 821        mutex_unlock(&info->port.mutex);
 822
 823        tty_port_close_end(&info->port, tty);
 824        info->port.tty = NULL;
 825cleanup:
 826        if (debug_level >= DEBUG_LEVEL_INFO)
 827                printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 828                        tty->driver->name, info->port.count);
 829}
 830
 831/* Called by tty_hangup() when a hangup is signaled.
 832 * This is the same as closing all open descriptors for the port.
 833 */
 834static void hangup(struct tty_struct *tty)
 835{
 836        SLMP_INFO *info = tty->driver_data;
 837        unsigned long flags;
 838
 839        if (debug_level >= DEBUG_LEVEL_INFO)
 840                printk("%s(%d):%s hangup()\n",
 841                         __FILE__,__LINE__, info->device_name );
 842
 843        if (sanity_check(info, tty->name, "hangup"))
 844                return;
 845
 846        mutex_lock(&info->port.mutex);
 847        flush_buffer(tty);
 848        shutdown(info);
 849
 850        spin_lock_irqsave(&info->port.lock, flags);
 851        info->port.count = 0;
 852        info->port.tty = NULL;
 853        spin_unlock_irqrestore(&info->port.lock, flags);
 854        tty_port_set_active(&info->port, 1);
 855        mutex_unlock(&info->port.mutex);
 856
 857        wake_up_interruptible(&info->port.open_wait);
 858}
 859
 860/* Set new termios settings
 861 */
 862static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 863{
 864        SLMP_INFO *info = tty->driver_data;
 865        unsigned long flags;
 866
 867        if (debug_level >= DEBUG_LEVEL_INFO)
 868                printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 869                        tty->driver->name );
 870
 871        change_params(info);
 872
 873        /* Handle transition to B0 status */
 874        if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 875                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 876                spin_lock_irqsave(&info->lock,flags);
 877                set_signals(info);
 878                spin_unlock_irqrestore(&info->lock,flags);
 879        }
 880
 881        /* Handle transition away from B0 status */
 882        if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 883                info->serial_signals |= SerialSignal_DTR;
 884                if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 885                        info->serial_signals |= SerialSignal_RTS;
 886                spin_lock_irqsave(&info->lock,flags);
 887                set_signals(info);
 888                spin_unlock_irqrestore(&info->lock,flags);
 889        }
 890
 891        /* Handle turning off CRTSCTS */
 892        if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
 893                tty->hw_stopped = 0;
 894                tx_release(tty);
 895        }
 896}
 897
 898/* Send a block of data
 899 *
 900 * Arguments:
 901 *
 902 *      tty             pointer to tty information structure
 903 *      buf             pointer to buffer containing send data
 904 *      count           size of send data in bytes
 905 *
 906 * Return Value:        number of characters written
 907 */
 908static int write(struct tty_struct *tty,
 909                 const unsigned char *buf, int count)
 910{
 911        int     c, ret = 0;
 912        SLMP_INFO *info = tty->driver_data;
 913        unsigned long flags;
 914
 915        if (debug_level >= DEBUG_LEVEL_INFO)
 916                printk("%s(%d):%s write() count=%d\n",
 917                       __FILE__,__LINE__,info->device_name,count);
 918
 919        if (sanity_check(info, tty->name, "write"))
 920                goto cleanup;
 921
 922        if (!info->tx_buf)
 923                goto cleanup;
 924
 925        if (info->params.mode == MGSL_MODE_HDLC) {
 926                if (count > info->max_frame_size) {
 927                        ret = -EIO;
 928                        goto cleanup;
 929                }
 930                if (info->tx_active)
 931                        goto cleanup;
 932                if (info->tx_count) {
 933                        /* send accumulated data from send_char() calls */
 934                        /* as frame and wait before accepting more data. */
 935                        tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 936                        goto start;
 937                }
 938                ret = info->tx_count = count;
 939                tx_load_dma_buffer(info, buf, count);
 940                goto start;
 941        }
 942
 943        for (;;) {
 944                c = min_t(int, count,
 945                        min(info->max_frame_size - info->tx_count - 1,
 946                            info->max_frame_size - info->tx_put));
 947                if (c <= 0)
 948                        break;
 949                        
 950                memcpy(info->tx_buf + info->tx_put, buf, c);
 951
 952                spin_lock_irqsave(&info->lock,flags);
 953                info->tx_put += c;
 954                if (info->tx_put >= info->max_frame_size)
 955                        info->tx_put -= info->max_frame_size;
 956                info->tx_count += c;
 957                spin_unlock_irqrestore(&info->lock,flags);
 958
 959                buf += c;
 960                count -= c;
 961                ret += c;
 962        }
 963
 964        if (info->params.mode == MGSL_MODE_HDLC) {
 965                if (count) {
 966                        ret = info->tx_count = 0;
 967                        goto cleanup;
 968                }
 969                tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 970        }
 971start:
 972        if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 973                spin_lock_irqsave(&info->lock,flags);
 974                if (!info->tx_active)
 975                        tx_start(info);
 976                spin_unlock_irqrestore(&info->lock,flags);
 977        }
 978
 979cleanup:
 980        if (debug_level >= DEBUG_LEVEL_INFO)
 981                printk( "%s(%d):%s write() returning=%d\n",
 982                        __FILE__,__LINE__,info->device_name,ret);
 983        return ret;
 984}
 985
 986/* Add a character to the transmit buffer.
 987 */
 988static int put_char(struct tty_struct *tty, unsigned char ch)
 989{
 990        SLMP_INFO *info = tty->driver_data;
 991        unsigned long flags;
 992        int ret = 0;
 993
 994        if ( debug_level >= DEBUG_LEVEL_INFO ) {
 995                printk( "%s(%d):%s put_char(%d)\n",
 996                        __FILE__,__LINE__,info->device_name,ch);
 997        }
 998
 999        if (sanity_check(info, tty->name, "put_char"))
1000                return 0;
1001
1002        if (!info->tx_buf)
1003                return 0;
1004
1005        spin_lock_irqsave(&info->lock,flags);
1006
1007        if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008             !info->tx_active ) {
1009
1010                if (info->tx_count < info->max_frame_size - 1) {
1011                        info->tx_buf[info->tx_put++] = ch;
1012                        if (info->tx_put >= info->max_frame_size)
1013                                info->tx_put -= info->max_frame_size;
1014                        info->tx_count++;
1015                        ret = 1;
1016                }
1017        }
1018
1019        spin_unlock_irqrestore(&info->lock,flags);
1020        return ret;
1021}
1022
1023/* Send a high-priority XON/XOFF character
1024 */
1025static void send_xchar(struct tty_struct *tty, char ch)
1026{
1027        SLMP_INFO *info = tty->driver_data;
1028        unsigned long flags;
1029
1030        if (debug_level >= DEBUG_LEVEL_INFO)
1031                printk("%s(%d):%s send_xchar(%d)\n",
1032                         __FILE__,__LINE__, info->device_name, ch );
1033
1034        if (sanity_check(info, tty->name, "send_xchar"))
1035                return;
1036
1037        info->x_char = ch;
1038        if (ch) {
1039                /* Make sure transmit interrupts are on */
1040                spin_lock_irqsave(&info->lock,flags);
1041                if (!info->tx_enabled)
1042                        tx_start(info);
1043                spin_unlock_irqrestore(&info->lock,flags);
1044        }
1045}
1046
1047/* Wait until the transmitter is empty.
1048 */
1049static void wait_until_sent(struct tty_struct *tty, int timeout)
1050{
1051        SLMP_INFO * info = tty->driver_data;
1052        unsigned long orig_jiffies, char_time;
1053
1054        if (!info )
1055                return;
1056
1057        if (debug_level >= DEBUG_LEVEL_INFO)
1058                printk("%s(%d):%s wait_until_sent() entry\n",
1059                         __FILE__,__LINE__, info->device_name );
1060
1061        if (sanity_check(info, tty->name, "wait_until_sent"))
1062                return;
1063
1064        if (!tty_port_initialized(&info->port))
1065                goto exit;
1066
1067        orig_jiffies = jiffies;
1068
1069        /* Set check interval to 1/5 of estimated time to
1070         * send a character, and make it at least 1. The check
1071         * interval should also be less than the timeout.
1072         * Note: use tight timings here to satisfy the NIST-PCTS.
1073         */
1074
1075        if ( info->params.data_rate ) {
1076                char_time = info->timeout/(32 * 5);
1077                if (!char_time)
1078                        char_time++;
1079        } else
1080                char_time = 1;
1081
1082        if (timeout)
1083                char_time = min_t(unsigned long, char_time, timeout);
1084
1085        if ( info->params.mode == MGSL_MODE_HDLC ) {
1086                while (info->tx_active) {
1087                        msleep_interruptible(jiffies_to_msecs(char_time));
1088                        if (signal_pending(current))
1089                                break;
1090                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091                                break;
1092                }
1093        } else {
1094                /*
1095                 * TODO: determine if there is something similar to USC16C32
1096                 *       TXSTATUS_ALL_SENT status
1097                 */
1098                while ( info->tx_active && info->tx_enabled) {
1099                        msleep_interruptible(jiffies_to_msecs(char_time));
1100                        if (signal_pending(current))
1101                                break;
1102                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103                                break;
1104                }
1105        }
1106
1107exit:
1108        if (debug_level >= DEBUG_LEVEL_INFO)
1109                printk("%s(%d):%s wait_until_sent() exit\n",
1110                         __FILE__,__LINE__, info->device_name );
1111}
1112
1113/* Return the count of free bytes in transmit buffer
1114 */
1115static int write_room(struct tty_struct *tty)
1116{
1117        SLMP_INFO *info = tty->driver_data;
1118        int ret;
1119
1120        if (sanity_check(info, tty->name, "write_room"))
1121                return 0;
1122
1123        if (info->params.mode == MGSL_MODE_HDLC) {
1124                ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125        } else {
1126                ret = info->max_frame_size - info->tx_count - 1;
1127                if (ret < 0)
1128                        ret = 0;
1129        }
1130
1131        if (debug_level >= DEBUG_LEVEL_INFO)
1132                printk("%s(%d):%s write_room()=%d\n",
1133                       __FILE__, __LINE__, info->device_name, ret);
1134
1135        return ret;
1136}
1137
1138/* enable transmitter and send remaining buffered characters
1139 */
1140static void flush_chars(struct tty_struct *tty)
1141{
1142        SLMP_INFO *info = tty->driver_data;
1143        unsigned long flags;
1144
1145        if ( debug_level >= DEBUG_LEVEL_INFO )
1146                printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147                        __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149        if (sanity_check(info, tty->name, "flush_chars"))
1150                return;
1151
1152        if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153            !info->tx_buf)
1154                return;
1155
1156        if ( debug_level >= DEBUG_LEVEL_INFO )
1157                printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158                        __FILE__,__LINE__,info->device_name );
1159
1160        spin_lock_irqsave(&info->lock,flags);
1161
1162        if (!info->tx_active) {
1163                if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164                        info->tx_count ) {
1165                        /* operating in synchronous (frame oriented) mode */
1166                        /* copy data from circular tx_buf to */
1167                        /* transmit DMA buffer. */
1168                        tx_load_dma_buffer(info,
1169                                 info->tx_buf,info->tx_count);
1170                }
1171                tx_start(info);
1172        }
1173
1174        spin_unlock_irqrestore(&info->lock,flags);
1175}
1176
1177/* Discard all data in the send buffer
1178 */
1179static void flush_buffer(struct tty_struct *tty)
1180{
1181        SLMP_INFO *info = tty->driver_data;
1182        unsigned long flags;
1183
1184        if (debug_level >= DEBUG_LEVEL_INFO)
1185                printk("%s(%d):%s flush_buffer() entry\n",
1186                         __FILE__,__LINE__, info->device_name );
1187
1188        if (sanity_check(info, tty->name, "flush_buffer"))
1189                return;
1190
1191        spin_lock_irqsave(&info->lock,flags);
1192        info->tx_count = info->tx_put = info->tx_get = 0;
1193        del_timer(&info->tx_timer);
1194        spin_unlock_irqrestore(&info->lock,flags);
1195
1196        tty_wakeup(tty);
1197}
1198
1199/* throttle (stop) transmitter
1200 */
1201static void tx_hold(struct tty_struct *tty)
1202{
1203        SLMP_INFO *info = tty->driver_data;
1204        unsigned long flags;
1205
1206        if (sanity_check(info, tty->name, "tx_hold"))
1207                return;
1208
1209        if ( debug_level >= DEBUG_LEVEL_INFO )
1210                printk("%s(%d):%s tx_hold()\n",
1211                        __FILE__,__LINE__,info->device_name);
1212
1213        spin_lock_irqsave(&info->lock,flags);
1214        if (info->tx_enabled)
1215                tx_stop(info);
1216        spin_unlock_irqrestore(&info->lock,flags);
1217}
1218
1219/* release (start) transmitter
1220 */
1221static void tx_release(struct tty_struct *tty)
1222{
1223        SLMP_INFO *info = tty->driver_data;
1224        unsigned long flags;
1225
1226        if (sanity_check(info, tty->name, "tx_release"))
1227                return;
1228
1229        if ( debug_level >= DEBUG_LEVEL_INFO )
1230                printk("%s(%d):%s tx_release()\n",
1231                        __FILE__,__LINE__,info->device_name);
1232
1233        spin_lock_irqsave(&info->lock,flags);
1234        if (!info->tx_enabled)
1235                tx_start(info);
1236        spin_unlock_irqrestore(&info->lock,flags);
1237}
1238
1239/* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 *      tty     pointer to tty instance data
1244 *      cmd     IOCTL command code
1245 *      arg     command argument/context
1246 *
1247 * Return Value:        0 if success, otherwise error code
1248 */
1249static int ioctl(struct tty_struct *tty,
1250                 unsigned int cmd, unsigned long arg)
1251{
1252        SLMP_INFO *info = tty->driver_data;
1253        void __user *argp = (void __user *)arg;
1254
1255        if (debug_level >= DEBUG_LEVEL_INFO)
1256                printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257                        info->device_name, cmd );
1258
1259        if (sanity_check(info, tty->name, "ioctl"))
1260                return -ENODEV;
1261
1262        if (cmd != TIOCMIWAIT) {
1263                if (tty_io_error(tty))
1264                    return -EIO;
1265        }
1266
1267        switch (cmd) {
1268        case MGSL_IOCGPARAMS:
1269                return get_params(info, argp);
1270        case MGSL_IOCSPARAMS:
1271                return set_params(info, argp);
1272        case MGSL_IOCGTXIDLE:
1273                return get_txidle(info, argp);
1274        case MGSL_IOCSTXIDLE:
1275                return set_txidle(info, (int)arg);
1276        case MGSL_IOCTXENABLE:
1277                return tx_enable(info, (int)arg);
1278        case MGSL_IOCRXENABLE:
1279                return rx_enable(info, (int)arg);
1280        case MGSL_IOCTXABORT:
1281                return tx_abort(info);
1282        case MGSL_IOCGSTATS:
1283                return get_stats(info, argp);
1284        case MGSL_IOCWAITEVENT:
1285                return wait_mgsl_event(info, argp);
1286        case MGSL_IOCLOOPTXDONE:
1287                return 0; // TODO: Not supported, need to document
1288                /* Wait for modem input (DCD,RI,DSR,CTS) change
1289                 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1290                 */
1291        case TIOCMIWAIT:
1292                return modem_input_wait(info,(int)arg);
1293                
1294                /*
1295                 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1296                 * Return: write counters to the user passed counter struct
1297                 * NB: both 1->0 and 0->1 transitions are counted except for
1298                 *     RI where only 0->1 is counted.
1299                 */
1300        default:
1301                return -ENOIOCTLCMD;
1302        }
1303        return 0;
1304}
1305
1306static int get_icount(struct tty_struct *tty,
1307                                struct serial_icounter_struct *icount)
1308{
1309        SLMP_INFO *info = tty->driver_data;
1310        struct mgsl_icount cnow;        /* kernel counter temps */
1311        unsigned long flags;
1312
1313        spin_lock_irqsave(&info->lock,flags);
1314        cnow = info->icount;
1315        spin_unlock_irqrestore(&info->lock,flags);
1316
1317        icount->cts = cnow.cts;
1318        icount->dsr = cnow.dsr;
1319        icount->rng = cnow.rng;
1320        icount->dcd = cnow.dcd;
1321        icount->rx = cnow.rx;
1322        icount->tx = cnow.tx;
1323        icount->frame = cnow.frame;
1324        icount->overrun = cnow.overrun;
1325        icount->parity = cnow.parity;
1326        icount->brk = cnow.brk;
1327        icount->buf_overrun = cnow.buf_overrun;
1328
1329        return 0;
1330}
1331
1332/*
1333 * /proc fs routines....
1334 */
1335
1336static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1337{
1338        char    stat_buf[30];
1339        unsigned long flags;
1340
1341        seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1342                       "\tIRQ=%d MaxFrameSize=%u\n",
1343                info->device_name,
1344                info->phys_sca_base,
1345                info->phys_memory_base,
1346                info->phys_statctrl_base,
1347                info->phys_lcr_base,
1348                info->irq_level,
1349                info->max_frame_size );
1350
1351        /* output current serial signal states */
1352        spin_lock_irqsave(&info->lock,flags);
1353        get_signals(info);
1354        spin_unlock_irqrestore(&info->lock,flags);
1355
1356        stat_buf[0] = 0;
1357        stat_buf[1] = 0;
1358        if (info->serial_signals & SerialSignal_RTS)
1359                strcat(stat_buf, "|RTS");
1360        if (info->serial_signals & SerialSignal_CTS)
1361                strcat(stat_buf, "|CTS");
1362        if (info->serial_signals & SerialSignal_DTR)
1363                strcat(stat_buf, "|DTR");
1364        if (info->serial_signals & SerialSignal_DSR)
1365                strcat(stat_buf, "|DSR");
1366        if (info->serial_signals & SerialSignal_DCD)
1367                strcat(stat_buf, "|CD");
1368        if (info->serial_signals & SerialSignal_RI)
1369                strcat(stat_buf, "|RI");
1370
1371        if (info->params.mode == MGSL_MODE_HDLC) {
1372                seq_printf(m, "\tHDLC txok:%d rxok:%d",
1373                              info->icount.txok, info->icount.rxok);
1374                if (info->icount.txunder)
1375                        seq_printf(m, " txunder:%d", info->icount.txunder);
1376                if (info->icount.txabort)
1377                        seq_printf(m, " txabort:%d", info->icount.txabort);
1378                if (info->icount.rxshort)
1379                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
1380                if (info->icount.rxlong)
1381                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
1382                if (info->icount.rxover)
1383                        seq_printf(m, " rxover:%d", info->icount.rxover);
1384                if (info->icount.rxcrc)
1385                        seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1386        } else {
1387                seq_printf(m, "\tASYNC tx:%d rx:%d",
1388                              info->icount.tx, info->icount.rx);
1389                if (info->icount.frame)
1390                        seq_printf(m, " fe:%d", info->icount.frame);
1391                if (info->icount.parity)
1392                        seq_printf(m, " pe:%d", info->icount.parity);
1393                if (info->icount.brk)
1394                        seq_printf(m, " brk:%d", info->icount.brk);
1395                if (info->icount.overrun)
1396                        seq_printf(m, " oe:%d", info->icount.overrun);
1397        }
1398
1399        /* Append serial signal status to end */
1400        seq_printf(m, " %s\n", stat_buf+1);
1401
1402        seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1403         info->tx_active,info->bh_requested,info->bh_running,
1404         info->pending_bh);
1405}
1406
1407/* Called to print information about devices
1408 */
1409static int synclinkmp_proc_show(struct seq_file *m, void *v)
1410{
1411        SLMP_INFO *info;
1412
1413        seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1414
1415        info = synclinkmp_device_list;
1416        while( info ) {
1417                line_info(m, info);
1418                info = info->next_device;
1419        }
1420        return 0;
1421}
1422
1423/* Return the count of bytes in transmit buffer
1424 */
1425static int chars_in_buffer(struct tty_struct *tty)
1426{
1427        SLMP_INFO *info = tty->driver_data;
1428
1429        if (sanity_check(info, tty->name, "chars_in_buffer"))
1430                return 0;
1431
1432        if (debug_level >= DEBUG_LEVEL_INFO)
1433                printk("%s(%d):%s chars_in_buffer()=%d\n",
1434                       __FILE__, __LINE__, info->device_name, info->tx_count);
1435
1436        return info->tx_count;
1437}
1438
1439/* Signal remote device to throttle send data (our receive data)
1440 */
1441static void throttle(struct tty_struct * tty)
1442{
1443        SLMP_INFO *info = tty->driver_data;
1444        unsigned long flags;
1445
1446        if (debug_level >= DEBUG_LEVEL_INFO)
1447                printk("%s(%d):%s throttle() entry\n",
1448                         __FILE__,__LINE__, info->device_name );
1449
1450        if (sanity_check(info, tty->name, "throttle"))
1451                return;
1452
1453        if (I_IXOFF(tty))
1454                send_xchar(tty, STOP_CHAR(tty));
1455
1456        if (C_CRTSCTS(tty)) {
1457                spin_lock_irqsave(&info->lock,flags);
1458                info->serial_signals &= ~SerialSignal_RTS;
1459                set_signals(info);
1460                spin_unlock_irqrestore(&info->lock,flags);
1461        }
1462}
1463
1464/* Signal remote device to stop throttling send data (our receive data)
1465 */
1466static void unthrottle(struct tty_struct * tty)
1467{
1468        SLMP_INFO *info = tty->driver_data;
1469        unsigned long flags;
1470
1471        if (debug_level >= DEBUG_LEVEL_INFO)
1472                printk("%s(%d):%s unthrottle() entry\n",
1473                         __FILE__,__LINE__, info->device_name );
1474
1475        if (sanity_check(info, tty->name, "unthrottle"))
1476                return;
1477
1478        if (I_IXOFF(tty)) {
1479                if (info->x_char)
1480                        info->x_char = 0;
1481                else
1482                        send_xchar(tty, START_CHAR(tty));
1483        }
1484
1485        if (C_CRTSCTS(tty)) {
1486                spin_lock_irqsave(&info->lock,flags);
1487                info->serial_signals |= SerialSignal_RTS;
1488                set_signals(info);
1489                spin_unlock_irqrestore(&info->lock,flags);
1490        }
1491}
1492
1493/* set or clear transmit break condition
1494 * break_state  -1=set break condition, 0=clear
1495 */
1496static int set_break(struct tty_struct *tty, int break_state)
1497{
1498        unsigned char RegValue;
1499        SLMP_INFO * info = tty->driver_data;
1500        unsigned long flags;
1501
1502        if (debug_level >= DEBUG_LEVEL_INFO)
1503                printk("%s(%d):%s set_break(%d)\n",
1504                         __FILE__,__LINE__, info->device_name, break_state);
1505
1506        if (sanity_check(info, tty->name, "set_break"))
1507                return -EINVAL;
1508
1509        spin_lock_irqsave(&info->lock,flags);
1510        RegValue = read_reg(info, CTL);
1511        if (break_state == -1)
1512                RegValue |= BIT3;
1513        else
1514                RegValue &= ~BIT3;
1515        write_reg(info, CTL, RegValue);
1516        spin_unlock_irqrestore(&info->lock,flags);
1517        return 0;
1518}
1519
1520#if SYNCLINK_GENERIC_HDLC
1521
1522/**
1523 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1524 * set encoding and frame check sequence (FCS) options
1525 *
1526 * dev       pointer to network device structure
1527 * encoding  serial encoding setting
1528 * parity    FCS setting
1529 *
1530 * returns 0 if success, otherwise error code
1531 */
1532static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1533                          unsigned short parity)
1534{
1535        SLMP_INFO *info = dev_to_port(dev);
1536        unsigned char  new_encoding;
1537        unsigned short new_crctype;
1538
1539        /* return error if TTY interface open */
1540        if (info->port.count)
1541                return -EBUSY;
1542
1543        switch (encoding)
1544        {
1545        case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1546        case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1547        case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1548        case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1549        case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1550        default: return -EINVAL;
1551        }
1552
1553        switch (parity)
1554        {
1555        case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1556        case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1557        case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1558        default: return -EINVAL;
1559        }
1560
1561        info->params.encoding = new_encoding;
1562        info->params.crc_type = new_crctype;
1563
1564        /* if network interface up, reprogram hardware */
1565        if (info->netcount)
1566                program_hw(info);
1567
1568        return 0;
1569}
1570
1571/**
1572 * called by generic HDLC layer to send frame
1573 *
1574 * skb  socket buffer containing HDLC frame
1575 * dev  pointer to network device structure
1576 */
1577static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1578                                      struct net_device *dev)
1579{
1580        SLMP_INFO *info = dev_to_port(dev);
1581        unsigned long flags;
1582
1583        if (debug_level >= DEBUG_LEVEL_INFO)
1584                printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1585
1586        /* stop sending until this frame completes */
1587        netif_stop_queue(dev);
1588
1589        /* copy data to device buffers */
1590        info->tx_count = skb->len;
1591        tx_load_dma_buffer(info, skb->data, skb->len);
1592
1593        /* update network statistics */
1594        dev->stats.tx_packets++;
1595        dev->stats.tx_bytes += skb->len;
1596
1597        /* done with socket buffer, so free it */
1598        dev_kfree_skb(skb);
1599
1600        /* save start time for transmit timeout detection */
1601        netif_trans_update(dev);
1602
1603        /* start hardware transmitter if necessary */
1604        spin_lock_irqsave(&info->lock,flags);
1605        if (!info->tx_active)
1606                tx_start(info);
1607        spin_unlock_irqrestore(&info->lock,flags);
1608
1609        return NETDEV_TX_OK;
1610}
1611
1612/**
1613 * called by network layer when interface enabled
1614 * claim resources and initialize hardware
1615 *
1616 * dev  pointer to network device structure
1617 *
1618 * returns 0 if success, otherwise error code
1619 */
1620static int hdlcdev_open(struct net_device *dev)
1621{
1622        SLMP_INFO *info = dev_to_port(dev);
1623        int rc;
1624        unsigned long flags;
1625
1626        if (debug_level >= DEBUG_LEVEL_INFO)
1627                printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1628
1629        /* generic HDLC layer open processing */
1630        rc = hdlc_open(dev);
1631        if (rc)
1632                return rc;
1633
1634        /* arbitrate between network and tty opens */
1635        spin_lock_irqsave(&info->netlock, flags);
1636        if (info->port.count != 0 || info->netcount != 0) {
1637                printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1638                spin_unlock_irqrestore(&info->netlock, flags);
1639                return -EBUSY;
1640        }
1641        info->netcount=1;
1642        spin_unlock_irqrestore(&info->netlock, flags);
1643
1644        /* claim resources and init adapter */
1645        if ((rc = startup(info)) != 0) {
1646                spin_lock_irqsave(&info->netlock, flags);
1647                info->netcount=0;
1648                spin_unlock_irqrestore(&info->netlock, flags);
1649                return rc;
1650        }
1651
1652        /* assert RTS and DTR, apply hardware settings */
1653        info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1654        program_hw(info);
1655
1656        /* enable network layer transmit */
1657        netif_trans_update(dev);
1658        netif_start_queue(dev);
1659
1660        /* inform generic HDLC layer of current DCD status */
1661        spin_lock_irqsave(&info->lock, flags);
1662        get_signals(info);
1663        spin_unlock_irqrestore(&info->lock, flags);
1664        if (info->serial_signals & SerialSignal_DCD)
1665                netif_carrier_on(dev);
1666        else
1667                netif_carrier_off(dev);
1668        return 0;
1669}
1670
1671/**
1672 * called by network layer when interface is disabled
1673 * shutdown hardware and release resources
1674 *
1675 * dev  pointer to network device structure
1676 *
1677 * returns 0 if success, otherwise error code
1678 */
1679static int hdlcdev_close(struct net_device *dev)
1680{
1681        SLMP_INFO *info = dev_to_port(dev);
1682        unsigned long flags;
1683
1684        if (debug_level >= DEBUG_LEVEL_INFO)
1685                printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1686
1687        netif_stop_queue(dev);
1688
1689        /* shutdown adapter and release resources */
1690        shutdown(info);
1691
1692        hdlc_close(dev);
1693
1694        spin_lock_irqsave(&info->netlock, flags);
1695        info->netcount=0;
1696        spin_unlock_irqrestore(&info->netlock, flags);
1697
1698        return 0;
1699}
1700
1701/**
1702 * called by network layer to process IOCTL call to network device
1703 *
1704 * dev  pointer to network device structure
1705 * ifr  pointer to network interface request structure
1706 * cmd  IOCTL command code
1707 *
1708 * returns 0 if success, otherwise error code
1709 */
1710static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1711{
1712        const size_t size = sizeof(sync_serial_settings);
1713        sync_serial_settings new_line;
1714        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1715        SLMP_INFO *info = dev_to_port(dev);
1716        unsigned int flags;
1717
1718        if (debug_level >= DEBUG_LEVEL_INFO)
1719                printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1720
1721        /* return error if TTY interface open */
1722        if (info->port.count)
1723                return -EBUSY;
1724
1725        if (cmd != SIOCWANDEV)
1726                return hdlc_ioctl(dev, ifr, cmd);
1727
1728        switch(ifr->ifr_settings.type) {
1729        case IF_GET_IFACE: /* return current sync_serial_settings */
1730
1731                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1732                if (ifr->ifr_settings.size < size) {
1733                        ifr->ifr_settings.size = size; /* data size wanted */
1734                        return -ENOBUFS;
1735                }
1736
1737                flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1738                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1739                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1740                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1741
1742                memset(&new_line, 0, sizeof(new_line));
1743                switch (flags){
1744                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1745                case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1746                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1747                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1748                default: new_line.clock_type = CLOCK_DEFAULT;
1749                }
1750
1751                new_line.clock_rate = info->params.clock_speed;
1752                new_line.loopback   = info->params.loopback ? 1:0;
1753
1754                if (copy_to_user(line, &new_line, size))
1755                        return -EFAULT;
1756                return 0;
1757
1758        case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1759
1760                if(!capable(CAP_NET_ADMIN))
1761                        return -EPERM;
1762                if (copy_from_user(&new_line, line, size))
1763                        return -EFAULT;
1764
1765                switch (new_line.clock_type)
1766                {
1767                case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1768                case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1769                case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1770                case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1771                case CLOCK_DEFAULT:  flags = info->params.flags &
1772                                             (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1773                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1774                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1775                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1776                default: return -EINVAL;
1777                }
1778
1779                if (new_line.loopback != 0 && new_line.loopback != 1)
1780                        return -EINVAL;
1781
1782                info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1783                                        HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1784                                        HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1785                                        HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1786                info->params.flags |= flags;
1787
1788                info->params.loopback = new_line.loopback;
1789
1790                if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1791                        info->params.clock_speed = new_line.clock_rate;
1792                else
1793                        info->params.clock_speed = 0;
1794
1795                /* if network interface up, reprogram hardware */
1796                if (info->netcount)
1797                        program_hw(info);
1798                return 0;
1799
1800        default:
1801                return hdlc_ioctl(dev, ifr, cmd);
1802        }
1803}
1804
1805/**
1806 * called by network layer when transmit timeout is detected
1807 *
1808 * dev  pointer to network device structure
1809 */
1810static void hdlcdev_tx_timeout(struct net_device *dev)
1811{
1812        SLMP_INFO *info = dev_to_port(dev);
1813        unsigned long flags;
1814
1815        if (debug_level >= DEBUG_LEVEL_INFO)
1816                printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1817
1818        dev->stats.tx_errors++;
1819        dev->stats.tx_aborted_errors++;
1820
1821        spin_lock_irqsave(&info->lock,flags);
1822        tx_stop(info);
1823        spin_unlock_irqrestore(&info->lock,flags);
1824
1825        netif_wake_queue(dev);
1826}
1827
1828/**
1829 * called by device driver when transmit completes
1830 * reenable network layer transmit if stopped
1831 *
1832 * info  pointer to device instance information
1833 */
1834static void hdlcdev_tx_done(SLMP_INFO *info)
1835{
1836        if (netif_queue_stopped(info->netdev))
1837                netif_wake_queue(info->netdev);
1838}
1839
1840/**
1841 * called by device driver when frame received
1842 * pass frame to network layer
1843 *
1844 * info  pointer to device instance information
1845 * buf   pointer to buffer contianing frame data
1846 * size  count of data bytes in buf
1847 */
1848static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1849{
1850        struct sk_buff *skb = dev_alloc_skb(size);
1851        struct net_device *dev = info->netdev;
1852
1853        if (debug_level >= DEBUG_LEVEL_INFO)
1854                printk("hdlcdev_rx(%s)\n",dev->name);
1855
1856        if (skb == NULL) {
1857                printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1858                       dev->name);
1859                dev->stats.rx_dropped++;
1860                return;
1861        }
1862
1863        skb_put_data(skb, buf, size);
1864
1865        skb->protocol = hdlc_type_trans(skb, dev);
1866
1867        dev->stats.rx_packets++;
1868        dev->stats.rx_bytes += size;
1869
1870        netif_rx(skb);
1871}
1872
1873static const struct net_device_ops hdlcdev_ops = {
1874        .ndo_open       = hdlcdev_open,
1875        .ndo_stop       = hdlcdev_close,
1876        .ndo_start_xmit = hdlc_start_xmit,
1877        .ndo_do_ioctl   = hdlcdev_ioctl,
1878        .ndo_tx_timeout = hdlcdev_tx_timeout,
1879};
1880
1881/**
1882 * called by device driver when adding device instance
1883 * do generic HDLC initialization
1884 *
1885 * info  pointer to device instance information
1886 *
1887 * returns 0 if success, otherwise error code
1888 */
1889static int hdlcdev_init(SLMP_INFO *info)
1890{
1891        int rc;
1892        struct net_device *dev;
1893        hdlc_device *hdlc;
1894
1895        /* allocate and initialize network and HDLC layer objects */
1896
1897        dev = alloc_hdlcdev(info);
1898        if (!dev) {
1899                printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1900                return -ENOMEM;
1901        }
1902
1903        /* for network layer reporting purposes only */
1904        dev->mem_start = info->phys_sca_base;
1905        dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1906        dev->irq       = info->irq_level;
1907
1908        /* network layer callbacks and settings */
1909        dev->netdev_ops     = &hdlcdev_ops;
1910        dev->watchdog_timeo = 10 * HZ;
1911        dev->tx_queue_len   = 50;
1912
1913        /* generic HDLC layer callbacks and settings */
1914        hdlc         = dev_to_hdlc(dev);
1915        hdlc->attach = hdlcdev_attach;
1916        hdlc->xmit   = hdlcdev_xmit;
1917
1918        /* register objects with HDLC layer */
1919        rc = register_hdlc_device(dev);
1920        if (rc) {
1921                printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1922                free_netdev(dev);
1923                return rc;
1924        }
1925
1926        info->netdev = dev;
1927        return 0;
1928}
1929
1930/**
1931 * called by device driver when removing device instance
1932 * do generic HDLC cleanup
1933 *
1934 * info  pointer to device instance information
1935 */
1936static void hdlcdev_exit(SLMP_INFO *info)
1937{
1938        unregister_hdlc_device(info->netdev);
1939        free_netdev(info->netdev);
1940        info->netdev = NULL;
1941}
1942
1943#endif /* CONFIG_HDLC */
1944
1945
1946/* Return next bottom half action to perform.
1947 * Return Value:        BH action code or 0 if nothing to do.
1948 */
1949static int bh_action(SLMP_INFO *info)
1950{
1951        unsigned long flags;
1952        int rc = 0;
1953
1954        spin_lock_irqsave(&info->lock,flags);
1955
1956        if (info->pending_bh & BH_RECEIVE) {
1957                info->pending_bh &= ~BH_RECEIVE;
1958                rc = BH_RECEIVE;
1959        } else if (info->pending_bh & BH_TRANSMIT) {
1960                info->pending_bh &= ~BH_TRANSMIT;
1961                rc = BH_TRANSMIT;
1962        } else if (info->pending_bh & BH_STATUS) {
1963                info->pending_bh &= ~BH_STATUS;
1964                rc = BH_STATUS;
1965        }
1966
1967        if (!rc) {
1968                /* Mark BH routine as complete */
1969                info->bh_running = false;
1970                info->bh_requested = false;
1971        }
1972
1973        spin_unlock_irqrestore(&info->lock,flags);
1974
1975        return rc;
1976}
1977
1978/* Perform bottom half processing of work items queued by ISR.
1979 */
1980static void bh_handler(struct work_struct *work)
1981{
1982        SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1983        int action;
1984
1985        if ( debug_level >= DEBUG_LEVEL_BH )
1986                printk( "%s(%d):%s bh_handler() entry\n",
1987                        __FILE__,__LINE__,info->device_name);
1988
1989        info->bh_running = true;
1990
1991        while((action = bh_action(info)) != 0) {
1992
1993                /* Process work item */
1994                if ( debug_level >= DEBUG_LEVEL_BH )
1995                        printk( "%s(%d):%s bh_handler() work item action=%d\n",
1996                                __FILE__,__LINE__,info->device_name, action);
1997
1998                switch (action) {
1999
2000                case BH_RECEIVE:
2001                        bh_receive(info);
2002                        break;
2003                case BH_TRANSMIT:
2004                        bh_transmit(info);
2005                        break;
2006                case BH_STATUS:
2007                        bh_status(info);
2008                        break;
2009                default:
2010                        /* unknown work item ID */
2011                        printk("%s(%d):%s Unknown work item ID=%08X!\n",
2012                                __FILE__,__LINE__,info->device_name,action);
2013                        break;
2014                }
2015        }
2016
2017        if ( debug_level >= DEBUG_LEVEL_BH )
2018                printk( "%s(%d):%s bh_handler() exit\n",
2019                        __FILE__,__LINE__,info->device_name);
2020}
2021
2022static void bh_receive(SLMP_INFO *info)
2023{
2024        if ( debug_level >= DEBUG_LEVEL_BH )
2025                printk( "%s(%d):%s bh_receive()\n",
2026                        __FILE__,__LINE__,info->device_name);
2027
2028        while( rx_get_frame(info) );
2029}
2030
2031static void bh_transmit(SLMP_INFO *info)
2032{
2033        struct tty_struct *tty = info->port.tty;
2034
2035        if ( debug_level >= DEBUG_LEVEL_BH )
2036                printk( "%s(%d):%s bh_transmit() entry\n",
2037                        __FILE__,__LINE__,info->device_name);
2038
2039        if (tty)
2040                tty_wakeup(tty);
2041}
2042
2043static void bh_status(SLMP_INFO *info)
2044{
2045        if ( debug_level >= DEBUG_LEVEL_BH )
2046                printk( "%s(%d):%s bh_status() entry\n",
2047                        __FILE__,__LINE__,info->device_name);
2048
2049        info->ri_chkcount = 0;
2050        info->dsr_chkcount = 0;
2051        info->dcd_chkcount = 0;
2052        info->cts_chkcount = 0;
2053}
2054
2055static void isr_timer(SLMP_INFO * info)
2056{
2057        unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2058
2059        /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2060        write_reg(info, IER2, 0);
2061
2062        /* TMCS, Timer Control/Status Register
2063         *
2064         * 07      CMF, Compare match flag (read only) 1=match
2065         * 06      ECMI, CMF Interrupt Enable: 0=disabled
2066         * 05      Reserved, must be 0
2067         * 04      TME, Timer Enable
2068         * 03..00  Reserved, must be 0
2069         *
2070         * 0000 0000
2071         */
2072        write_reg(info, (unsigned char)(timer + TMCS), 0);
2073
2074        info->irq_occurred = true;
2075
2076        if ( debug_level >= DEBUG_LEVEL_ISR )
2077                printk("%s(%d):%s isr_timer()\n",
2078                        __FILE__,__LINE__,info->device_name);
2079}
2080
2081static void isr_rxint(SLMP_INFO * info)
2082{
2083        struct tty_struct *tty = info->port.tty;
2084        struct  mgsl_icount *icount = &info->icount;
2085        unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2086        unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2087
2088        /* clear status bits */
2089        if (status)
2090                write_reg(info, SR1, status);
2091
2092        if (status2)
2093                write_reg(info, SR2, status2);
2094        
2095        if ( debug_level >= DEBUG_LEVEL_ISR )
2096                printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2097                        __FILE__,__LINE__,info->device_name,status,status2);
2098
2099        if (info->params.mode == MGSL_MODE_ASYNC) {
2100                if (status & BRKD) {
2101                        icount->brk++;
2102
2103                        /* process break detection if tty control
2104                         * is not set to ignore it
2105                         */
2106                        if (!(status & info->ignore_status_mask1)) {
2107                                if (info->read_status_mask1 & BRKD) {
2108                                        tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2109                                        if (tty && (info->port.flags & ASYNC_SAK))
2110                                                do_SAK(tty);
2111                                }
2112                        }
2113                }
2114        }
2115        else {
2116                if (status & (FLGD|IDLD)) {
2117                        if (status & FLGD)
2118                                info->icount.exithunt++;
2119                        else if (status & IDLD)
2120                                info->icount.rxidle++;
2121                        wake_up_interruptible(&info->event_wait_q);
2122                }
2123        }
2124
2125        if (status & CDCD) {
2126                /* simulate a common modem status change interrupt
2127                 * for our handler
2128                 */
2129                get_signals( info );
2130                isr_io_pin(info,
2131                        MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2132        }
2133}
2134
2135/*
2136 * handle async rx data interrupts
2137 */
2138static void isr_rxrdy(SLMP_INFO * info)
2139{
2140        u16 status;
2141        unsigned char DataByte;
2142        struct  mgsl_icount *icount = &info->icount;
2143
2144        if ( debug_level >= DEBUG_LEVEL_ISR )
2145                printk("%s(%d):%s isr_rxrdy\n",
2146                        __FILE__,__LINE__,info->device_name);
2147
2148        while((status = read_reg(info,CST0)) & BIT0)
2149        {
2150                int flag = 0;
2151                bool over = false;
2152                DataByte = read_reg(info,TRB);
2153
2154                icount->rx++;
2155
2156                if ( status & (PE + FRME + OVRN) ) {
2157                        printk("%s(%d):%s rxerr=%04X\n",
2158                                __FILE__,__LINE__,info->device_name,status);
2159
2160                        /* update error statistics */
2161                        if (status & PE)
2162                                icount->parity++;
2163                        else if (status & FRME)
2164                                icount->frame++;
2165                        else if (status & OVRN)
2166                                icount->overrun++;
2167
2168                        /* discard char if tty control flags say so */
2169                        if (status & info->ignore_status_mask2)
2170                                continue;
2171
2172                        status &= info->read_status_mask2;
2173
2174                        if (status & PE)
2175                                flag = TTY_PARITY;
2176                        else if (status & FRME)
2177                                flag = TTY_FRAME;
2178                        if (status & OVRN) {
2179                                /* Overrun is special, since it's
2180                                 * reported immediately, and doesn't
2181                                 * affect the current character
2182                                 */
2183                                over = true;
2184                        }
2185                }       /* end of if (error) */
2186
2187                tty_insert_flip_char(&info->port, DataByte, flag);
2188                if (over)
2189                        tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2190        }
2191
2192        if ( debug_level >= DEBUG_LEVEL_ISR ) {
2193                printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2194                        __FILE__,__LINE__,info->device_name,
2195                        icount->rx,icount->brk,icount->parity,
2196                        icount->frame,icount->overrun);
2197        }
2198
2199        tty_flip_buffer_push(&info->port);
2200}
2201
2202static void isr_txeom(SLMP_INFO * info, unsigned char status)
2203{
2204        if ( debug_level >= DEBUG_LEVEL_ISR )
2205                printk("%s(%d):%s isr_txeom status=%02x\n",
2206                        __FILE__,__LINE__,info->device_name,status);
2207
2208        write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2209        write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2210        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2211
2212        if (status & UDRN) {
2213                write_reg(info, CMD, TXRESET);
2214                write_reg(info, CMD, TXENABLE);
2215        } else
2216                write_reg(info, CMD, TXBUFCLR);
2217
2218        /* disable and clear tx interrupts */
2219        info->ie0_value &= ~TXRDYE;
2220        info->ie1_value &= ~(IDLE + UDRN);
2221        write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2222        write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2223
2224        if ( info->tx_active ) {
2225                if (info->params.mode != MGSL_MODE_ASYNC) {
2226                        if (status & UDRN)
2227                                info->icount.txunder++;
2228                        else if (status & IDLE)
2229                                info->icount.txok++;
2230                }
2231
2232                info->tx_active = false;
2233                info->tx_count = info->tx_put = info->tx_get = 0;
2234
2235                del_timer(&info->tx_timer);
2236
2237                if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2238                        info->serial_signals &= ~SerialSignal_RTS;
2239                        info->drop_rts_on_tx_done = false;
2240                        set_signals(info);
2241                }
2242
2243#if SYNCLINK_GENERIC_HDLC
2244                if (info->netcount)
2245                        hdlcdev_tx_done(info);
2246                else
2247#endif
2248                {
2249                        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2250                                tx_stop(info);
2251                                return;
2252                        }
2253                        info->pending_bh |= BH_TRANSMIT;
2254                }
2255        }
2256}
2257
2258
2259/*
2260 * handle tx status interrupts
2261 */
2262static void isr_txint(SLMP_INFO * info)
2263{
2264        unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2265
2266        /* clear status bits */
2267        write_reg(info, SR1, status);
2268
2269        if ( debug_level >= DEBUG_LEVEL_ISR )
2270                printk("%s(%d):%s isr_txint status=%02x\n",
2271                        __FILE__,__LINE__,info->device_name,status);
2272
2273        if (status & (UDRN + IDLE))
2274                isr_txeom(info, status);
2275
2276        if (status & CCTS) {
2277                /* simulate a common modem status change interrupt
2278                 * for our handler
2279                 */
2280                get_signals( info );
2281                isr_io_pin(info,
2282                        MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2283
2284        }
2285}
2286
2287/*
2288 * handle async tx data interrupts
2289 */
2290static void isr_txrdy(SLMP_INFO * info)
2291{
2292        if ( debug_level >= DEBUG_LEVEL_ISR )
2293                printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2294                        __FILE__,__LINE__,info->device_name,info->tx_count);
2295
2296        if (info->params.mode != MGSL_MODE_ASYNC) {
2297                /* disable TXRDY IRQ, enable IDLE IRQ */
2298                info->ie0_value &= ~TXRDYE;
2299                info->ie1_value |= IDLE;
2300                write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2301                return;
2302        }
2303
2304        if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2305                tx_stop(info);
2306                return;
2307        }
2308
2309        if ( info->tx_count )
2310                tx_load_fifo( info );
2311        else {
2312                info->tx_active = false;
2313                info->ie0_value &= ~TXRDYE;
2314                write_reg(info, IE0, info->ie0_value);
2315        }
2316
2317        if (info->tx_count < WAKEUP_CHARS)
2318                info->pending_bh |= BH_TRANSMIT;
2319}
2320
2321static void isr_rxdmaok(SLMP_INFO * info)
2322{
2323        /* BIT7 = EOT (end of transfer)
2324         * BIT6 = EOM (end of message/frame)
2325         */
2326        unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2327
2328        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2329        write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2330
2331        if ( debug_level >= DEBUG_LEVEL_ISR )
2332                printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2333                        __FILE__,__LINE__,info->device_name,status);
2334
2335        info->pending_bh |= BH_RECEIVE;
2336}
2337
2338static void isr_rxdmaerror(SLMP_INFO * info)
2339{
2340        /* BIT5 = BOF (buffer overflow)
2341         * BIT4 = COF (counter overflow)
2342         */
2343        unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2344
2345        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2346        write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2347
2348        if ( debug_level >= DEBUG_LEVEL_ISR )
2349                printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2350                        __FILE__,__LINE__,info->device_name,status);
2351
2352        info->rx_overflow = true;
2353        info->pending_bh |= BH_RECEIVE;
2354}
2355
2356static void isr_txdmaok(SLMP_INFO * info)
2357{
2358        unsigned char status_reg1 = read_reg(info, SR1);
2359
2360        write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2361        write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2362        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2363
2364        if ( debug_level >= DEBUG_LEVEL_ISR )
2365                printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2366                        __FILE__,__LINE__,info->device_name,status_reg1);
2367
2368        /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2369        write_reg16(info, TRC0, 0);
2370        info->ie0_value |= TXRDYE;
2371        write_reg(info, IE0, info->ie0_value);
2372}
2373
2374static void isr_txdmaerror(SLMP_INFO * info)
2375{
2376        /* BIT5 = BOF (buffer overflow)
2377         * BIT4 = COF (counter overflow)
2378         */
2379        unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2380
2381        /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2382        write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2383
2384        if ( debug_level >= DEBUG_LEVEL_ISR )
2385                printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2386                        __FILE__,__LINE__,info->device_name,status);
2387}
2388
2389/* handle input serial signal changes
2390 */
2391static void isr_io_pin( SLMP_INFO *info, u16 status )
2392{
2393        struct  mgsl_icount *icount;
2394
2395        if ( debug_level >= DEBUG_LEVEL_ISR )
2396                printk("%s(%d):isr_io_pin status=%04X\n",
2397                        __FILE__,__LINE__,status);
2398
2399        if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2400                      MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2401                icount = &info->icount;
2402                /* update input line counters */
2403                if (status & MISCSTATUS_RI_LATCHED) {
2404                        icount->rng++;
2405                        if ( status & SerialSignal_RI )
2406                                info->input_signal_events.ri_up++;
2407                        else
2408                                info->input_signal_events.ri_down++;
2409                }
2410                if (status & MISCSTATUS_DSR_LATCHED) {
2411                        icount->dsr++;
2412                        if ( status & SerialSignal_DSR )
2413                                info->input_signal_events.dsr_up++;
2414                        else
2415                                info->input_signal_events.dsr_down++;
2416                }
2417                if (status & MISCSTATUS_DCD_LATCHED) {
2418                        if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2419                                info->ie1_value &= ~CDCD;
2420                                write_reg(info, IE1, info->ie1_value);
2421                        }
2422                        icount->dcd++;
2423                        if (status & SerialSignal_DCD) {
2424                                info->input_signal_events.dcd_up++;
2425                        } else
2426                                info->input_signal_events.dcd_down++;
2427#if SYNCLINK_GENERIC_HDLC
2428                        if (info->netcount) {
2429                                if (status & SerialSignal_DCD)
2430                                        netif_carrier_on(info->netdev);
2431                                else
2432                                        netif_carrier_off(info->netdev);
2433                        }
2434#endif
2435                }
2436                if (status & MISCSTATUS_CTS_LATCHED)
2437                {
2438                        if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2439                                info->ie1_value &= ~CCTS;
2440                                write_reg(info, IE1, info->ie1_value);
2441                        }
2442                        icount->cts++;
2443                        if ( status & SerialSignal_CTS )
2444                                info->input_signal_events.cts_up++;
2445                        else
2446                                info->input_signal_events.cts_down++;
2447                }
2448                wake_up_interruptible(&info->status_event_wait_q);
2449                wake_up_interruptible(&info->event_wait_q);
2450
2451                if (tty_port_check_carrier(&info->port) &&
2452                     (status & MISCSTATUS_DCD_LATCHED) ) {
2453                        if ( debug_level >= DEBUG_LEVEL_ISR )
2454                                printk("%s CD now %s...", info->device_name,
2455                                       (status & SerialSignal_DCD) ? "on" : "off");
2456                        if (status & SerialSignal_DCD)
2457                                wake_up_interruptible(&info->port.open_wait);
2458                        else {
2459                                if ( debug_level >= DEBUG_LEVEL_ISR )
2460                                        printk("doing serial hangup...");
2461                                if (info->port.tty)
2462                                        tty_hangup(info->port.tty);
2463                        }
2464                }
2465
2466                if (tty_port_cts_enabled(&info->port) &&
2467                     (status & MISCSTATUS_CTS_LATCHED) ) {
2468                        if ( info->port.tty ) {
2469                                if (info->port.tty->hw_stopped) {
2470                                        if (status & SerialSignal_CTS) {
2471                                                if ( debug_level >= DEBUG_LEVEL_ISR )
2472                                                        printk("CTS tx start...");
2473                                                info->port.tty->hw_stopped = 0;
2474                                                tx_start(info);
2475                                                info->pending_bh |= BH_TRANSMIT;
2476                                                return;
2477                                        }
2478                                } else {
2479                                        if (!(status & SerialSignal_CTS)) {
2480                                                if ( debug_level >= DEBUG_LEVEL_ISR )
2481                                                        printk("CTS tx stop...");
2482                                                info->port.tty->hw_stopped = 1;
2483                                                tx_stop(info);
2484                                        }
2485                                }
2486                        }
2487                }
2488        }
2489
2490        info->pending_bh |= BH_STATUS;
2491}
2492
2493/* Interrupt service routine entry point.
2494 *
2495 * Arguments:
2496 *      irq             interrupt number that caused interrupt
2497 *      dev_id          device ID supplied during interrupt registration
2498 *      regs            interrupted processor context
2499 */
2500static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2501{
2502        SLMP_INFO *info = dev_id;
2503        unsigned char status, status0, status1=0;
2504        unsigned char dmastatus, dmastatus0, dmastatus1=0;
2505        unsigned char timerstatus0, timerstatus1=0;
2506        unsigned char shift;
2507        unsigned int i;
2508        unsigned short tmp;
2509
2510        if ( debug_level >= DEBUG_LEVEL_ISR )
2511                printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2512                        __FILE__, __LINE__, info->irq_level);
2513
2514        spin_lock(&info->lock);
2515
2516        for(;;) {
2517
2518                /* get status for SCA0 (ports 0-1) */
2519                tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2520                status0 = (unsigned char)tmp;
2521                dmastatus0 = (unsigned char)(tmp>>8);
2522                timerstatus0 = read_reg(info, ISR2);
2523
2524                if ( debug_level >= DEBUG_LEVEL_ISR )
2525                        printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2526                                __FILE__, __LINE__, info->device_name,
2527                                status0, dmastatus0, timerstatus0);
2528
2529                if (info->port_count == 4) {
2530                        /* get status for SCA1 (ports 2-3) */
2531                        tmp = read_reg16(info->port_array[2], ISR0);
2532                        status1 = (unsigned char)tmp;
2533                        dmastatus1 = (unsigned char)(tmp>>8);
2534                        timerstatus1 = read_reg(info->port_array[2], ISR2);
2535
2536                        if ( debug_level >= DEBUG_LEVEL_ISR )
2537                                printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2538                                        __FILE__,__LINE__,info->device_name,
2539                                        status1,dmastatus1,timerstatus1);
2540                }
2541
2542                if (!status0 && !dmastatus0 && !timerstatus0 &&
2543                         !status1 && !dmastatus1 && !timerstatus1)
2544                        break;
2545
2546                for(i=0; i < info->port_count ; i++) {
2547                        if (info->port_array[i] == NULL)
2548                                continue;
2549                        if (i < 2) {
2550                                status = status0;
2551                                dmastatus = dmastatus0;
2552                        } else {
2553                                status = status1;
2554                                dmastatus = dmastatus1;
2555                        }
2556
2557                        shift = i & 1 ? 4 :0;
2558
2559                        if (status & BIT0 << shift)
2560                                isr_rxrdy(info->port_array[i]);
2561                        if (status & BIT1 << shift)
2562                                isr_txrdy(info->port_array[i]);
2563                        if (status & BIT2 << shift)
2564                                isr_rxint(info->port_array[i]);
2565                        if (status & BIT3 << shift)
2566                                isr_txint(info->port_array[i]);
2567
2568                        if (dmastatus & BIT0 << shift)
2569                                isr_rxdmaerror(info->port_array[i]);
2570                        if (dmastatus & BIT1 << shift)
2571                                isr_rxdmaok(info->port_array[i]);
2572                        if (dmastatus & BIT2 << shift)
2573                                isr_txdmaerror(info->port_array[i]);
2574                        if (dmastatus & BIT3 << shift)
2575                                isr_txdmaok(info->port_array[i]);
2576                }
2577
2578                if (timerstatus0 & (BIT5 | BIT4))
2579                        isr_timer(info->port_array[0]);
2580                if (timerstatus0 & (BIT7 | BIT6))
2581                        isr_timer(info->port_array[1]);
2582                if (timerstatus1 & (BIT5 | BIT4))
2583                        isr_timer(info->port_array[2]);
2584                if (timerstatus1 & (BIT7 | BIT6))
2585                        isr_timer(info->port_array[3]);
2586        }
2587
2588        for(i=0; i < info->port_count ; i++) {
2589                SLMP_INFO * port = info->port_array[i];
2590
2591                /* Request bottom half processing if there's something
2592                 * for it to do and the bh is not already running.
2593                 *
2594                 * Note: startup adapter diags require interrupts.
2595                 * do not request bottom half processing if the
2596                 * device is not open in a normal mode.
2597                 */
2598                if ( port && (port->port.count || port->netcount) &&
2599                     port->pending_bh && !port->bh_running &&
2600                     !port->bh_requested ) {
2601                        if ( debug_level >= DEBUG_LEVEL_ISR )
2602                                printk("%s(%d):%s queueing bh task.\n",
2603                                        __FILE__,__LINE__,port->device_name);
2604                        schedule_work(&port->task);
2605                        port->bh_requested = true;
2606                }
2607        }
2608
2609        spin_unlock(&info->lock);
2610
2611        if ( debug_level >= DEBUG_LEVEL_ISR )
2612                printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2613                        __FILE__, __LINE__, info->irq_level);
2614        return IRQ_HANDLED;
2615}
2616
2617/* Initialize and start device.
2618 */
2619static int startup(SLMP_INFO * info)
2620{
2621        if ( debug_level >= DEBUG_LEVEL_INFO )
2622                printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2623
2624        if (tty_port_initialized(&info->port))
2625                return 0;
2626
2627        if (!info->tx_buf) {
2628                info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2629                if (!info->tx_buf) {
2630                        printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2631                                __FILE__,__LINE__,info->device_name);
2632                        return -ENOMEM;
2633                }
2634        }
2635
2636        info->pending_bh = 0;
2637
2638        memset(&info->icount, 0, sizeof(info->icount));
2639
2640        /* program hardware for current parameters */
2641        reset_port(info);
2642
2643        change_params(info);
2644
2645        mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2646
2647        if (info->port.tty)
2648                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2649
2650        tty_port_set_initialized(&info->port, 1);
2651
2652        return 0;
2653}
2654
2655/* Called by close() and hangup() to shutdown hardware
2656 */
2657static void shutdown(SLMP_INFO * info)
2658{
2659        unsigned long flags;
2660
2661        if (!tty_port_initialized(&info->port))
2662                return;
2663
2664        if (debug_level >= DEBUG_LEVEL_INFO)
2665                printk("%s(%d):%s synclinkmp_shutdown()\n",
2666                         __FILE__,__LINE__, info->device_name );
2667
2668        /* clear status wait queue because status changes */
2669        /* can't happen after shutting down the hardware */
2670        wake_up_interruptible(&info->status_event_wait_q);
2671        wake_up_interruptible(&info->event_wait_q);
2672
2673        del_timer(&info->tx_timer);
2674        del_timer(&info->status_timer);
2675
2676        kfree(info->tx_buf);
2677        info->tx_buf = NULL;
2678
2679        spin_lock_irqsave(&info->lock,flags);
2680
2681        reset_port(info);
2682
2683        if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2684                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2685                set_signals(info);
2686        }
2687
2688        spin_unlock_irqrestore(&info->lock,flags);
2689
2690        if (info->port.tty)
2691                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2692
2693        tty_port_set_initialized(&info->port, 0);
2694}
2695
2696static void program_hw(SLMP_INFO *info)
2697{
2698        unsigned long flags;
2699
2700        spin_lock_irqsave(&info->lock,flags);
2701
2702        rx_stop(info);
2703        tx_stop(info);
2704
2705        info->tx_count = info->tx_put = info->tx_get = 0;
2706
2707        if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2708                hdlc_mode(info);
2709        else
2710                async_mode(info);
2711
2712        set_signals(info);
2713
2714        info->dcd_chkcount = 0;
2715        info->cts_chkcount = 0;
2716        info->ri_chkcount = 0;
2717        info->dsr_chkcount = 0;
2718
2719        info->ie1_value |= (CDCD|CCTS);
2720        write_reg(info, IE1, info->ie1_value);
2721
2722        get_signals(info);
2723
2724        if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2725                rx_start(info);
2726
2727        spin_unlock_irqrestore(&info->lock,flags);
2728}
2729
2730/* Reconfigure adapter based on new parameters
2731 */
2732static void change_params(SLMP_INFO *info)
2733{
2734        unsigned cflag;
2735        int bits_per_char;
2736
2737        if (!info->port.tty)
2738                return;
2739
2740        if (debug_level >= DEBUG_LEVEL_INFO)
2741                printk("%s(%d):%s change_params()\n",
2742                         __FILE__,__LINE__, info->device_name );
2743
2744        cflag = info->port.tty->termios.c_cflag;
2745
2746        /* if B0 rate (hangup) specified then negate RTS and DTR */
2747        /* otherwise assert RTS and DTR */
2748        if (cflag & CBAUD)
2749                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2750        else
2751                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2752
2753        /* byte size and parity */
2754
2755        switch (cflag & CSIZE) {
2756              case CS5: info->params.data_bits = 5; break;
2757              case CS6: info->params.data_bits = 6; break;
2758              case CS7: info->params.data_bits = 7; break;
2759              case CS8: info->params.data_bits = 8; break;
2760              /* Never happens, but GCC is too dumb to figure it out */
2761              default:  info->params.data_bits = 7; break;
2762              }
2763
2764        if (cflag & CSTOPB)
2765                info->params.stop_bits = 2;
2766        else
2767                info->params.stop_bits = 1;
2768
2769        info->params.parity = ASYNC_PARITY_NONE;
2770        if (cflag & PARENB) {
2771                if (cflag & PARODD)
2772                        info->params.parity = ASYNC_PARITY_ODD;
2773                else
2774                        info->params.parity = ASYNC_PARITY_EVEN;
2775#ifdef CMSPAR
2776                if (cflag & CMSPAR)
2777                        info->params.parity = ASYNC_PARITY_SPACE;
2778#endif
2779        }
2780
2781        /* calculate number of jiffies to transmit a full
2782         * FIFO (32 bytes) at specified data rate
2783         */
2784        bits_per_char = info->params.data_bits +
2785                        info->params.stop_bits + 1;
2786
2787        /* if port data rate is set to 460800 or less then
2788         * allow tty settings to override, otherwise keep the
2789         * current data rate.
2790         */
2791        if (info->params.data_rate <= 460800) {
2792                info->params.data_rate = tty_get_baud_rate(info->port.tty);
2793        }
2794
2795        if ( info->params.data_rate ) {
2796                info->timeout = (32*HZ*bits_per_char) /
2797                                info->params.data_rate;
2798        }
2799        info->timeout += HZ/50;         /* Add .02 seconds of slop */
2800
2801        tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2802        tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2803
2804        /* process tty input control flags */
2805
2806        info->read_status_mask2 = OVRN;
2807        if (I_INPCK(info->port.tty))
2808                info->read_status_mask2 |= PE | FRME;
2809        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2810                info->read_status_mask1 |= BRKD;
2811        if (I_IGNPAR(info->port.tty))
2812                info->ignore_status_mask2 |= PE | FRME;
2813        if (I_IGNBRK(info->port.tty)) {
2814                info->ignore_status_mask1 |= BRKD;
2815                /* If ignoring parity and break indicators, ignore
2816                 * overruns too.  (For real raw support).
2817                 */
2818                if (I_IGNPAR(info->port.tty))
2819                        info->ignore_status_mask2 |= OVRN;
2820        }
2821
2822        program_hw(info);
2823}
2824
2825static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2826{
2827        int err;
2828
2829        if (debug_level >= DEBUG_LEVEL_INFO)
2830                printk("%s(%d):%s get_params()\n",
2831                         __FILE__,__LINE__, info->device_name);
2832
2833        if (!user_icount) {
2834                memset(&info->icount, 0, sizeof(info->icount));
2835        } else {
2836                mutex_lock(&info->port.mutex);
2837                COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2838                mutex_unlock(&info->port.mutex);
2839                if (err)
2840                        return -EFAULT;
2841        }
2842
2843        return 0;
2844}
2845
2846static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2847{
2848        int err;
2849        if (debug_level >= DEBUG_LEVEL_INFO)
2850                printk("%s(%d):%s get_params()\n",
2851                         __FILE__,__LINE__, info->device_name);
2852
2853        mutex_lock(&info->port.mutex);
2854        COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2855        mutex_unlock(&info->port.mutex);
2856        if (err) {
2857                if ( debug_level >= DEBUG_LEVEL_INFO )
2858                        printk( "%s(%d):%s get_params() user buffer copy failed\n",
2859                                __FILE__,__LINE__,info->device_name);
2860                return -EFAULT;
2861        }
2862
2863        return 0;
2864}
2865
2866static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2867{
2868        unsigned long flags;
2869        MGSL_PARAMS tmp_params;
2870        int err;
2871
2872        if (debug_level >= DEBUG_LEVEL_INFO)
2873                printk("%s(%d):%s set_params\n",
2874                        __FILE__,__LINE__,info->device_name );
2875        COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2876        if (err) {
2877                if ( debug_level >= DEBUG_LEVEL_INFO )
2878                        printk( "%s(%d):%s set_params() user buffer copy failed\n",
2879                                __FILE__,__LINE__,info->device_name);
2880                return -EFAULT;
2881        }
2882
2883        mutex_lock(&info->port.mutex);
2884        spin_lock_irqsave(&info->lock,flags);
2885        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2886        spin_unlock_irqrestore(&info->lock,flags);
2887
2888        change_params(info);
2889        mutex_unlock(&info->port.mutex);
2890
2891        return 0;
2892}
2893
2894static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2895{
2896        int err;
2897
2898        if (debug_level >= DEBUG_LEVEL_INFO)
2899                printk("%s(%d):%s get_txidle()=%d\n",
2900                         __FILE__,__LINE__, info->device_name, info->idle_mode);
2901
2902        COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2903        if (err) {
2904                if ( debug_level >= DEBUG_LEVEL_INFO )
2905                        printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2906                                __FILE__,__LINE__,info->device_name);
2907                return -EFAULT;
2908        }
2909
2910        return 0;
2911}
2912
2913static int set_txidle(SLMP_INFO * info, int idle_mode)
2914{
2915        unsigned long flags;
2916
2917        if (debug_level >= DEBUG_LEVEL_INFO)
2918                printk("%s(%d):%s set_txidle(%d)\n",
2919                        __FILE__,__LINE__,info->device_name, idle_mode );
2920
2921        spin_lock_irqsave(&info->lock,flags);
2922        info->idle_mode = idle_mode;
2923        tx_set_idle( info );
2924        spin_unlock_irqrestore(&info->lock,flags);
2925        return 0;
2926}
2927
2928static int tx_enable(SLMP_INFO * info, int enable)
2929{
2930        unsigned long flags;
2931
2932        if (debug_level >= DEBUG_LEVEL_INFO)
2933                printk("%s(%d):%s tx_enable(%d)\n",
2934                        __FILE__,__LINE__,info->device_name, enable);
2935
2936        spin_lock_irqsave(&info->lock,flags);
2937        if ( enable ) {
2938                if ( !info->tx_enabled ) {
2939                        tx_start(info);
2940                }
2941        } else {
2942                if ( info->tx_enabled )
2943                        tx_stop(info);
2944        }
2945        spin_unlock_irqrestore(&info->lock,flags);
2946        return 0;
2947}
2948
2949/* abort send HDLC frame
2950 */
2951static int tx_abort(SLMP_INFO * info)
2952{
2953        unsigned long flags;
2954
2955        if (debug_level >= DEBUG_LEVEL_INFO)
2956                printk("%s(%d):%s tx_abort()\n",
2957                        __FILE__,__LINE__,info->device_name);
2958
2959        spin_lock_irqsave(&info->lock,flags);
2960        if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2961                info->ie1_value &= ~UDRN;
2962                info->ie1_value |= IDLE;
2963                write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2964                write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
2965
2966                write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
2967                write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2968
2969                write_reg(info, CMD, TXABORT);
2970        }
2971        spin_unlock_irqrestore(&info->lock,flags);
2972        return 0;
2973}
2974
2975static int rx_enable(SLMP_INFO * info, int enable)
2976{
2977        unsigned long flags;
2978
2979        if (debug_level >= DEBUG_LEVEL_INFO)
2980                printk("%s(%d):%s rx_enable(%d)\n",
2981                        __FILE__,__LINE__,info->device_name,enable);
2982
2983        spin_lock_irqsave(&info->lock,flags);
2984        if ( enable ) {
2985                if ( !info->rx_enabled )
2986                        rx_start(info);
2987        } else {
2988                if ( info->rx_enabled )
2989                        rx_stop(info);
2990        }
2991        spin_unlock_irqrestore(&info->lock,flags);
2992        return 0;
2993}
2994
2995/* wait for specified event to occur
2996 */
2997static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2998{
2999        unsigned long flags;
3000        int s;
3001        int rc=0;
3002        struct mgsl_icount cprev, cnow;
3003        int events;
3004        int mask;
3005        struct  _input_signal_events oldsigs, newsigs;
3006        DECLARE_WAITQUEUE(wait, current);
3007
3008        COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3009        if (rc) {
3010                return  -EFAULT;
3011        }
3012
3013        if (debug_level >= DEBUG_LEVEL_INFO)
3014                printk("%s(%d):%s wait_mgsl_event(%d)\n",
3015                        __FILE__,__LINE__,info->device_name,mask);
3016
3017        spin_lock_irqsave(&info->lock,flags);
3018
3019        /* return immediately if state matches requested events */
3020        get_signals(info);
3021        s = info->serial_signals;
3022
3023        events = mask &
3024                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3025                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3026                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3027                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3028        if (events) {
3029                spin_unlock_irqrestore(&info->lock,flags);
3030                goto exit;
3031        }
3032
3033        /* save current irq counts */
3034        cprev = info->icount;
3035        oldsigs = info->input_signal_events;
3036
3037        /* enable hunt and idle irqs if needed */
3038        if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3039                unsigned char oldval = info->ie1_value;
3040                unsigned char newval = oldval +
3041                         (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3042                         (mask & MgslEvent_IdleReceived ? IDLD:0);
3043                if ( oldval != newval ) {
3044                        info->ie1_value = newval;
3045                        write_reg(info, IE1, info->ie1_value);
3046                }
3047        }
3048
3049        set_current_state(TASK_INTERRUPTIBLE);
3050        add_wait_queue(&info->event_wait_q, &wait);
3051
3052        spin_unlock_irqrestore(&info->lock,flags);
3053
3054        for(;;) {
3055                schedule();
3056                if (signal_pending(current)) {
3057                        rc = -ERESTARTSYS;
3058                        break;
3059                }
3060
3061                /* get current irq counts */
3062                spin_lock_irqsave(&info->lock,flags);
3063                cnow = info->icount;
3064                newsigs = info->input_signal_events;
3065                set_current_state(TASK_INTERRUPTIBLE);
3066                spin_unlock_irqrestore(&info->lock,flags);
3067
3068                /* if no change, wait aborted for some reason */
3069                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3070                    newsigs.dsr_down == oldsigs.dsr_down &&
3071                    newsigs.dcd_up   == oldsigs.dcd_up   &&
3072                    newsigs.dcd_down == oldsigs.dcd_down &&
3073                    newsigs.cts_up   == oldsigs.cts_up   &&
3074                    newsigs.cts_down == oldsigs.cts_down &&
3075                    newsigs.ri_up    == oldsigs.ri_up    &&
3076                    newsigs.ri_down  == oldsigs.ri_down  &&
3077                    cnow.exithunt    == cprev.exithunt   &&
3078                    cnow.rxidle      == cprev.rxidle) {
3079                        rc = -EIO;
3080                        break;
3081                }
3082
3083                events = mask &
3084                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3085                          (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3086                          (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3087                          (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3088                          (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3089                          (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3090                          (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3091                          (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3092                          (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3093                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3094                if (events)
3095                        break;
3096
3097                cprev = cnow;
3098                oldsigs = newsigs;
3099        }
3100
3101        remove_wait_queue(&info->event_wait_q, &wait);
3102        set_current_state(TASK_RUNNING);
3103
3104
3105        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3106                spin_lock_irqsave(&info->lock,flags);
3107                if (!waitqueue_active(&info->event_wait_q)) {
3108                        /* disable enable exit hunt mode/idle rcvd IRQs */
3109                        info->ie1_value &= ~(FLGD|IDLD);
3110                        write_reg(info, IE1, info->ie1_value);
3111                }
3112                spin_unlock_irqrestore(&info->lock,flags);
3113        }
3114exit:
3115        if ( rc == 0 )
3116                PUT_USER(rc, events, mask_ptr);
3117
3118        return rc;
3119}
3120
3121static int modem_input_wait(SLMP_INFO *info,int arg)
3122{
3123        unsigned long flags;
3124        int rc;
3125        struct mgsl_icount cprev, cnow;
3126        DECLARE_WAITQUEUE(wait, current);
3127
3128        /* save current irq counts */
3129        spin_lock_irqsave(&info->lock,flags);
3130        cprev = info->icount;
3131        add_wait_queue(&info->status_event_wait_q, &wait);
3132        set_current_state(TASK_INTERRUPTIBLE);
3133        spin_unlock_irqrestore(&info->lock,flags);
3134
3135        for(;;) {
3136                schedule();
3137                if (signal_pending(current)) {
3138                        rc = -ERESTARTSYS;
3139                        break;
3140                }
3141
3142                /* get new irq counts */
3143                spin_lock_irqsave(&info->lock,flags);
3144                cnow = info->icount;
3145                set_current_state(TASK_INTERRUPTIBLE);
3146                spin_unlock_irqrestore(&info->lock,flags);
3147
3148                /* if no change, wait aborted for some reason */
3149                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3150                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3151                        rc = -EIO;
3152                        break;
3153                }
3154
3155                /* check for change in caller specified modem input */
3156                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3157                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3158                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3159                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3160                        rc = 0;
3161                        break;
3162                }
3163
3164                cprev = cnow;
3165        }
3166        remove_wait_queue(&info->status_event_wait_q, &wait);
3167        set_current_state(TASK_RUNNING);
3168        return rc;
3169}
3170
3171/* return the state of the serial control and status signals
3172 */
3173static int tiocmget(struct tty_struct *tty)
3174{
3175        SLMP_INFO *info = tty->driver_data;
3176        unsigned int result;
3177        unsigned long flags;
3178
3179        spin_lock_irqsave(&info->lock,flags);
3180        get_signals(info);
3181        spin_unlock_irqrestore(&info->lock,flags);
3182
3183        result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3184                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3185                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3186                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG : 0) |
3187                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3188                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3189
3190        if (debug_level >= DEBUG_LEVEL_INFO)
3191                printk("%s(%d):%s tiocmget() value=%08X\n",
3192                         __FILE__,__LINE__, info->device_name, result );
3193        return result;
3194}
3195
3196/* set modem control signals (DTR/RTS)
3197 */
3198static int tiocmset(struct tty_struct *tty,
3199                                        unsigned int set, unsigned int clear)
3200{
3201        SLMP_INFO *info = tty->driver_data;
3202        unsigned long flags;
3203
3204        if (debug_level >= DEBUG_LEVEL_INFO)
3205                printk("%s(%d):%s tiocmset(%x,%x)\n",
3206                        __FILE__,__LINE__,info->device_name, set, clear);
3207
3208        if (set & TIOCM_RTS)
3209                info->serial_signals |= SerialSignal_RTS;
3210        if (set & TIOCM_DTR)
3211                info->serial_signals |= SerialSignal_DTR;
3212        if (clear & TIOCM_RTS)
3213                info->serial_signals &= ~SerialSignal_RTS;
3214        if (clear & TIOCM_DTR)
3215                info->serial_signals &= ~SerialSignal_DTR;
3216
3217        spin_lock_irqsave(&info->lock,flags);
3218        set_signals(info);
3219        spin_unlock_irqrestore(&info->lock,flags);
3220
3221        return 0;
3222}
3223
3224static int carrier_raised(struct tty_port *port)
3225{
3226        SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3227        unsigned long flags;
3228
3229        spin_lock_irqsave(&info->lock,flags);
3230        get_signals(info);
3231        spin_unlock_irqrestore(&info->lock,flags);
3232
3233        return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3234}
3235
3236static void dtr_rts(struct tty_port *port, int on)
3237{
3238        SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3239        unsigned long flags;
3240
3241        spin_lock_irqsave(&info->lock,flags);
3242        if (on)
3243                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3244        else
3245                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3246        set_signals(info);
3247        spin_unlock_irqrestore(&info->lock,flags);
3248}
3249
3250/* Block the current process until the specified port is ready to open.
3251 */
3252static int block_til_ready(struct tty_struct *tty, struct file *filp,
3253                           SLMP_INFO *info)
3254{
3255        DECLARE_WAITQUEUE(wait, current);
3256        int             retval;
3257        bool            do_clocal = false;
3258        unsigned long   flags;
3259        int             cd;
3260        struct tty_port *port = &info->port;
3261
3262        if (debug_level >= DEBUG_LEVEL_INFO)
3263                printk("%s(%d):%s block_til_ready()\n",
3264                         __FILE__,__LINE__, tty->driver->name );
3265
3266        if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3267                /* nonblock mode is set or port is not enabled */
3268                /* just verify that callout device is not active */
3269                tty_port_set_active(port, 1);
3270                return 0;
3271        }
3272
3273        if (C_CLOCAL(tty))
3274                do_clocal = true;
3275
3276        /* Wait for carrier detect and the line to become
3277         * free (i.e., not in use by the callout).  While we are in
3278         * this loop, port->count is dropped by one, so that
3279         * close() knows when to free things.  We restore it upon
3280         * exit, either normal or abnormal.
3281         */
3282
3283        retval = 0;
3284        add_wait_queue(&port->open_wait, &wait);
3285
3286        if (debug_level >= DEBUG_LEVEL_INFO)
3287                printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3288                         __FILE__,__LINE__, tty->driver->name, port->count );
3289
3290        spin_lock_irqsave(&info->lock, flags);
3291        port->count--;
3292        spin_unlock_irqrestore(&info->lock, flags);
3293        port->blocked_open++;
3294
3295        while (1) {
3296                if (C_BAUD(tty) && tty_port_initialized(port))
3297                        tty_port_raise_dtr_rts(port);
3298
3299                set_current_state(TASK_INTERRUPTIBLE);
3300
3301                if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3302                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3303                                        -EAGAIN : -ERESTARTSYS;
3304                        break;
3305                }
3306
3307                cd = tty_port_carrier_raised(port);
3308                if (do_clocal || cd)
3309                        break;
3310
3311                if (signal_pending(current)) {
3312                        retval = -ERESTARTSYS;
3313                        break;
3314                }
3315
3316                if (debug_level >= DEBUG_LEVEL_INFO)
3317                        printk("%s(%d):%s block_til_ready() count=%d\n",
3318                                 __FILE__,__LINE__, tty->driver->name, port->count );
3319
3320                tty_unlock(tty);
3321                schedule();
3322                tty_lock(tty);
3323        }
3324
3325        set_current_state(TASK_RUNNING);
3326        remove_wait_queue(&port->open_wait, &wait);
3327        if (!tty_hung_up_p(filp))
3328                port->count++;
3329        port->blocked_open--;
3330
3331        if (debug_level >= DEBUG_LEVEL_INFO)
3332                printk("%s(%d):%s block_til_ready() after, count=%d\n",
3333                         __FILE__,__LINE__, tty->driver->name, port->count );
3334
3335        if (!retval)
3336                tty_port_set_active(port, 1);
3337
3338        return retval;
3339}
3340
3341static int alloc_dma_bufs(SLMP_INFO *info)
3342{
3343        unsigned short BuffersPerFrame;
3344        unsigned short BufferCount;
3345
3346        // Force allocation to start at 64K boundary for each port.
3347        // This is necessary because *all* buffer descriptors for a port
3348        // *must* be in the same 64K block. All descriptors on a port
3349        // share a common 'base' address (upper 8 bits of 24 bits) programmed
3350        // into the CBP register.
3351        info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3352
3353        /* Calculate the number of DMA buffers necessary to hold the */
3354        /* largest allowable frame size. Note: If the max frame size is */
3355        /* not an even multiple of the DMA buffer size then we need to */
3356        /* round the buffer count per frame up one. */
3357
3358        BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3359        if ( info->max_frame_size % SCABUFSIZE )
3360                BuffersPerFrame++;
3361
3362        /* calculate total number of data buffers (SCABUFSIZE) possible
3363         * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3364         * for the descriptor list (BUFFERLISTSIZE).
3365         */
3366        BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3367
3368        /* limit number of buffers to maximum amount of descriptors */
3369        if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3370                BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3371
3372        /* use enough buffers to transmit one max size frame */
3373        info->tx_buf_count = BuffersPerFrame + 1;
3374
3375        /* never use more than half the available buffers for transmit */
3376        if (info->tx_buf_count > (BufferCount/2))
3377                info->tx_buf_count = BufferCount/2;
3378
3379        if (info->tx_buf_count > SCAMAXDESC)
3380                info->tx_buf_count = SCAMAXDESC;
3381
3382        /* use remaining buffers for receive */
3383        info->rx_buf_count = BufferCount - info->tx_buf_count;
3384
3385        if (info->rx_buf_count > SCAMAXDESC)
3386                info->rx_buf_count = SCAMAXDESC;
3387
3388        if ( debug_level >= DEBUG_LEVEL_INFO )
3389                printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3390                        __FILE__,__LINE__, info->device_name,
3391                        info->tx_buf_count,info->rx_buf_count);
3392
3393        if ( alloc_buf_list( info ) < 0 ||
3394                alloc_frame_bufs(info,
3395                                        info->rx_buf_list,
3396                                        info->rx_buf_list_ex,
3397                                        info->rx_buf_count) < 0 ||
3398                alloc_frame_bufs(info,
3399                                        info->tx_buf_list,
3400                                        info->tx_buf_list_ex,
3401                                        info->tx_buf_count) < 0 ||
3402                alloc_tmp_rx_buf(info) < 0 ) {
3403                printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3404                        __FILE__,__LINE__, info->device_name);
3405                return -ENOMEM;
3406        }
3407
3408        rx_reset_buffers( info );
3409
3410        return 0;
3411}
3412
3413/* Allocate DMA buffers for the transmit and receive descriptor lists.
3414 */
3415static int alloc_buf_list(SLMP_INFO *info)
3416{
3417        unsigned int i;
3418
3419        /* build list in adapter shared memory */
3420        info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3421        info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3422        info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3423
3424        memset(info->buffer_list, 0, BUFFERLISTSIZE);
3425
3426        /* Save virtual address pointers to the receive and */
3427        /* transmit buffer lists. (Receive 1st). These pointers will */
3428        /* be used by the processor to access the lists. */
3429        info->rx_buf_list = (SCADESC *)info->buffer_list;
3430
3431        info->tx_buf_list = (SCADESC *)info->buffer_list;
3432        info->tx_buf_list += info->rx_buf_count;
3433
3434        /* Build links for circular buffer entry lists (tx and rx)
3435         *
3436         * Note: links are physical addresses read by the SCA device
3437         * to determine the next buffer entry to use.
3438         */
3439
3440        for ( i = 0; i < info->rx_buf_count; i++ ) {
3441                /* calculate and store physical address of this buffer entry */
3442                info->rx_buf_list_ex[i].phys_entry =
3443                        info->buffer_list_phys + (i * SCABUFSIZE);
3444
3445                /* calculate and store physical address of */
3446                /* next entry in cirular list of entries */
3447                info->rx_buf_list[i].next = info->buffer_list_phys;
3448                if ( i < info->rx_buf_count - 1 )
3449                        info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3450
3451                info->rx_buf_list[i].length = SCABUFSIZE;
3452        }
3453
3454        for ( i = 0; i < info->tx_buf_count; i++ ) {
3455                /* calculate and store physical address of this buffer entry */
3456                info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3457                        ((info->rx_buf_count + i) * sizeof(SCADESC));
3458
3459                /* calculate and store physical address of */
3460                /* next entry in cirular list of entries */
3461
3462                info->tx_buf_list[i].next = info->buffer_list_phys +
3463                        info->rx_buf_count * sizeof(SCADESC);
3464
3465                if ( i < info->tx_buf_count - 1 )
3466                        info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3467        }
3468
3469        return 0;
3470}
3471
3472/* Allocate the frame DMA buffers used by the specified buffer list.
3473 */
3474static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3475{
3476        int i;
3477        unsigned long phys_addr;
3478
3479        for ( i = 0; i < count; i++ ) {
3480                buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3481                phys_addr = info->port_array[0]->last_mem_alloc;
3482                info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3483
3484                buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3485                buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3486        }
3487
3488        return 0;
3489}
3490
3491static void free_dma_bufs(SLMP_INFO *info)
3492{
3493        info->buffer_list = NULL;
3494        info->rx_buf_list = NULL;
3495        info->tx_buf_list = NULL;
3496}
3497
3498/* allocate buffer large enough to hold max_frame_size.
3499 * This buffer is used to pass an assembled frame to the line discipline.
3500 */
3501static int alloc_tmp_rx_buf(SLMP_INFO *info)
3502{
3503        info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3504        if (info->tmp_rx_buf == NULL)
3505                return -ENOMEM;
3506        /* unused flag buffer to satisfy receive_buf calling interface */
3507        info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3508        if (!info->flag_buf) {
3509                kfree(info->tmp_rx_buf);
3510                info->tmp_rx_buf = NULL;
3511                return -ENOMEM;
3512        }
3513        return 0;
3514}
3515
3516static void free_tmp_rx_buf(SLMP_INFO *info)
3517{
3518        kfree(info->tmp_rx_buf);
3519        info->tmp_rx_buf = NULL;
3520        kfree(info->flag_buf);
3521        info->flag_buf = NULL;
3522}
3523
3524static int claim_resources(SLMP_INFO *info)
3525{
3526        if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3527                printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3528                        __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3529                info->init_error = DiagStatus_AddressConflict;
3530                goto errout;
3531        }
3532        else
3533                info->shared_mem_requested = true;
3534
3535        if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3536                printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3537                        __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3538                info->init_error = DiagStatus_AddressConflict;
3539                goto errout;
3540        }
3541        else
3542                info->lcr_mem_requested = true;
3543
3544        if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3545                printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3546                        __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3547                info->init_error = DiagStatus_AddressConflict;
3548                goto errout;
3549        }
3550        else
3551                info->sca_base_requested = true;
3552
3553        if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3554                printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3555                        __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3556                info->init_error = DiagStatus_AddressConflict;
3557                goto errout;
3558        }
3559        else
3560                info->sca_statctrl_requested = true;
3561
3562        info->memory_base = ioremap_nocache(info->phys_memory_base,
3563                                                                SCA_MEM_SIZE);
3564        if (!info->memory_base) {
3565                printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3566                        __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3567                info->init_error = DiagStatus_CantAssignPciResources;
3568                goto errout;
3569        }
3570
3571        info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3572        if (!info->lcr_base) {
3573                printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3574                        __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3575                info->init_error = DiagStatus_CantAssignPciResources;
3576                goto errout;
3577        }
3578        info->lcr_base += info->lcr_offset;
3579
3580        info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3581        if (!info->sca_base) {
3582                printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3583                        __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3584                info->init_error = DiagStatus_CantAssignPciResources;
3585                goto errout;
3586        }
3587        info->sca_base += info->sca_offset;
3588
3589        info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3590                                                                PAGE_SIZE);
3591        if (!info->statctrl_base) {
3592                printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3593                        __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3594                info->init_error = DiagStatus_CantAssignPciResources;
3595                goto errout;
3596        }
3597        info->statctrl_base += info->statctrl_offset;
3598
3599        if ( !memory_test(info) ) {
3600                printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3601                        __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3602                info->init_error = DiagStatus_MemoryError;
3603                goto errout;
3604        }
3605
3606        return 0;
3607
3608errout:
3609        release_resources( info );
3610        return -ENODEV;
3611}
3612
3613static void release_resources(SLMP_INFO *info)
3614{
3615        if ( debug_level >= DEBUG_LEVEL_INFO )
3616                printk( "%s(%d):%s release_resources() entry\n",
3617                        __FILE__,__LINE__,info->device_name );
3618
3619        if ( info->irq_requested ) {
3620                free_irq(info->irq_level, info);
3621                info->irq_requested = false;
3622        }
3623
3624        if ( info->shared_mem_requested ) {
3625                release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3626                info->shared_mem_requested = false;
3627        }
3628        if ( info->lcr_mem_requested ) {
3629                release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3630                info->lcr_mem_requested = false;
3631        }
3632        if ( info->sca_base_requested ) {
3633                release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3634                info->sca_base_requested = false;
3635        }
3636        if ( info->sca_statctrl_requested ) {
3637                release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3638                info->sca_statctrl_requested = false;
3639        }
3640
3641        if (info->memory_base){
3642                iounmap(info->memory_base);
3643                info->memory_base = NULL;
3644        }
3645
3646        if (info->sca_base) {
3647                iounmap(info->sca_base - info->sca_offset);
3648                info->sca_base=NULL;
3649        }
3650
3651        if (info->statctrl_base) {
3652                iounmap(info->statctrl_base - info->statctrl_offset);
3653                info->statctrl_base=NULL;
3654        }
3655
3656        if (info->lcr_base){
3657                iounmap(info->lcr_base - info->lcr_offset);
3658                info->lcr_base = NULL;
3659        }
3660
3661        if ( debug_level >= DEBUG_LEVEL_INFO )
3662                printk( "%s(%d):%s release_resources() exit\n",
3663                        __FILE__,__LINE__,info->device_name );
3664}
3665
3666/* Add the specified device instance data structure to the
3667 * global linked list of devices and increment the device count.
3668 */
3669static int add_device(SLMP_INFO *info)
3670{
3671        info->next_device = NULL;
3672        info->line = synclinkmp_device_count;
3673        sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3674
3675        if (info->line < MAX_DEVICES) {
3676                if (maxframe[info->line])
3677                        info->max_frame_size = maxframe[info->line];
3678        }
3679
3680        synclinkmp_device_count++;
3681
3682        if ( !synclinkmp_device_list )
3683                synclinkmp_device_list = info;
3684        else {
3685                SLMP_INFO *current_dev = synclinkmp_device_list;
3686                while( current_dev->next_device )
3687                        current_dev = current_dev->next_device;
3688                current_dev->next_device = info;
3689        }
3690
3691        if ( info->max_frame_size < 4096 )
3692                info->max_frame_size = 4096;
3693        else if ( info->max_frame_size > 65535 )
3694                info->max_frame_size = 65535;
3695
3696        printk( "SyncLink MultiPort %s: "
3697                "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3698                info->device_name,
3699                info->phys_sca_base,
3700                info->phys_memory_base,
3701                info->phys_statctrl_base,
3702                info->phys_lcr_base,
3703                info->irq_level,
3704                info->max_frame_size );
3705
3706#if SYNCLINK_GENERIC_HDLC
3707        return hdlcdev_init(info);
3708#else
3709        return 0;
3710#endif
3711}
3712
3713static const struct tty_port_operations port_ops = {
3714        .carrier_raised = carrier_raised,
3715        .dtr_rts = dtr_rts,
3716};
3717
3718/* Allocate and initialize a device instance structure
3719 *
3720 * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3721 */
3722static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3723{
3724        SLMP_INFO *info;
3725
3726        info = kzalloc(sizeof(SLMP_INFO),
3727                 GFP_KERNEL);
3728
3729        if (!info) {
3730                printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3731                        __FILE__,__LINE__, adapter_num, port_num);
3732        } else {
3733                tty_port_init(&info->port);
3734                info->port.ops = &port_ops;
3735                info->magic = MGSL_MAGIC;
3736                INIT_WORK(&info->task, bh_handler);
3737                info->max_frame_size = 4096;
3738                info->port.close_delay = 5*HZ/10;
3739                info->port.closing_wait = 30*HZ;
3740                init_waitqueue_head(&info->status_event_wait_q);
3741                init_waitqueue_head(&info->event_wait_q);
3742                spin_lock_init(&info->netlock);
3743                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3744                info->idle_mode = HDLC_TXIDLE_FLAGS;
3745                info->adapter_num = adapter_num;
3746                info->port_num = port_num;
3747
3748                /* Copy configuration info to device instance data */
3749                info->irq_level = pdev->irq;
3750                info->phys_lcr_base = pci_resource_start(pdev,0);
3751                info->phys_sca_base = pci_resource_start(pdev,2);
3752                info->phys_memory_base = pci_resource_start(pdev,3);
3753                info->phys_statctrl_base = pci_resource_start(pdev,4);
3754
3755                /* Because veremap only works on page boundaries we must map
3756                 * a larger area than is actually implemented for the LCR
3757                 * memory range. We map a full page starting at the page boundary.
3758                 */
3759                info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3760                info->phys_lcr_base &= ~(PAGE_SIZE-1);
3761
3762                info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3763                info->phys_sca_base &= ~(PAGE_SIZE-1);
3764
3765                info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3766                info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3767
3768                info->bus_type = MGSL_BUS_TYPE_PCI;
3769                info->irq_flags = IRQF_SHARED;
3770
3771                timer_setup(&info->tx_timer, tx_timeout, 0);
3772                timer_setup(&info->status_timer, status_timeout, 0);
3773
3774                /* Store the PCI9050 misc control register value because a flaw
3775                 * in the PCI9050 prevents LCR registers from being read if
3776                 * BIOS assigns an LCR base address with bit 7 set.
3777                 *
3778                 * Only the misc control register is accessed for which only
3779                 * write access is needed, so set an initial value and change
3780                 * bits to the device instance data as we write the value
3781                 * to the actual misc control register.
3782                 */
3783                info->misc_ctrl_value = 0x087e4546;
3784
3785                /* initial port state is unknown - if startup errors
3786                 * occur, init_error will be set to indicate the
3787                 * problem. Once the port is fully initialized,
3788                 * this value will be set to 0 to indicate the
3789                 * port is available.
3790                 */
3791                info->init_error = -1;
3792        }
3793
3794        return info;
3795}
3796
3797static int device_init(int adapter_num, struct pci_dev *pdev)
3798{
3799        SLMP_INFO *port_array[SCA_MAX_PORTS];
3800        int port, rc;
3801
3802        /* allocate device instances for up to SCA_MAX_PORTS devices */
3803        for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3804                port_array[port] = alloc_dev(adapter_num,port,pdev);
3805                if( port_array[port] == NULL ) {
3806                        for (--port; port >= 0; --port) {
3807                                tty_port_destroy(&port_array[port]->port);
3808                                kfree(port_array[port]);
3809                        }
3810                        return -ENOMEM;
3811                }
3812        }
3813
3814        /* give copy of port_array to all ports and add to device list  */
3815        for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3816                memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3817                rc = add_device( port_array[port] );
3818                if (rc)
3819                        goto err_add;
3820                spin_lock_init(&port_array[port]->lock);
3821        }
3822
3823        /* Allocate and claim adapter resources */
3824        if ( !claim_resources(port_array[0]) ) {
3825
3826                alloc_dma_bufs(port_array[0]);
3827
3828                /* copy resource information from first port to others */
3829                for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3830                        port_array[port]->lock  = port_array[0]->lock;
3831                        port_array[port]->irq_level     = port_array[0]->irq_level;
3832                        port_array[port]->memory_base   = port_array[0]->memory_base;
3833                        port_array[port]->sca_base      = port_array[0]->sca_base;
3834                        port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3835                        port_array[port]->lcr_base      = port_array[0]->lcr_base;
3836                        alloc_dma_bufs(port_array[port]);
3837                }
3838
3839                rc = request_irq(port_array[0]->irq_level,
3840                                        synclinkmp_interrupt,
3841                                        port_array[0]->irq_flags,
3842                                        port_array[0]->device_name,
3843                                        port_array[0]);
3844                if ( rc ) {
3845                        printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3846                                __FILE__,__LINE__,
3847                                port_array[0]->device_name,
3848                                port_array[0]->irq_level );
3849                        goto err_irq;
3850                }
3851                port_array[0]->irq_requested = true;
3852                adapter_test(port_array[0]);
3853        }
3854        return 0;
3855err_irq:
3856        release_resources( port_array[0] );
3857err_add:
3858        for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3859                tty_port_destroy(&port_array[port]->port);
3860                kfree(port_array[port]);
3861        }
3862        return rc;
3863}
3864
3865static const struct tty_operations ops = {
3866        .install = install,
3867        .open = open,
3868        .close = close,
3869        .write = write,
3870        .put_char = put_char,
3871        .flush_chars = flush_chars,
3872        .write_room = write_room,
3873        .chars_in_buffer = chars_in_buffer,
3874        .flush_buffer = flush_buffer,
3875        .ioctl = ioctl,
3876        .throttle = throttle,
3877        .unthrottle = unthrottle,
3878        .send_xchar = send_xchar,
3879        .break_ctl = set_break,
3880        .wait_until_sent = wait_until_sent,
3881        .set_termios = set_termios,
3882        .stop = tx_hold,
3883        .start = tx_release,
3884        .hangup = hangup,
3885        .tiocmget = tiocmget,
3886        .tiocmset = tiocmset,
3887        .get_icount = get_icount,
3888        .proc_show = synclinkmp_proc_show,
3889};
3890
3891
3892static void synclinkmp_cleanup(void)
3893{
3894        int rc;
3895        SLMP_INFO *info;
3896        SLMP_INFO *tmp;
3897
3898        printk("Unloading %s %s\n", driver_name, driver_version);
3899
3900        if (serial_driver) {
3901                rc = tty_unregister_driver(serial_driver);
3902                if (rc)
3903                        printk("%s(%d) failed to unregister tty driver err=%d\n",
3904                               __FILE__,__LINE__,rc);
3905                put_tty_driver(serial_driver);
3906        }
3907
3908        /* reset devices */
3909        info = synclinkmp_device_list;
3910        while(info) {
3911                reset_port(info);
3912                info = info->next_device;
3913        }
3914
3915        /* release devices */
3916        info = synclinkmp_device_list;
3917        while(info) {
3918#if SYNCLINK_GENERIC_HDLC
3919                hdlcdev_exit(info);
3920#endif
3921                free_dma_bufs(info);
3922                free_tmp_rx_buf(info);
3923                if ( info->port_num == 0 ) {
3924                        if (info->sca_base)
3925                                write_reg(info, LPR, 1); /* set low power mode */
3926                        release_resources(info);
3927                }
3928                tmp = info;
3929                info = info->next_device;
3930                tty_port_destroy(&tmp->port);
3931                kfree(tmp);
3932        }
3933
3934        pci_unregister_driver(&synclinkmp_pci_driver);
3935}
3936
3937/* Driver initialization entry point.
3938 */
3939
3940static int __init synclinkmp_init(void)
3941{
3942        int rc;
3943
3944        if (break_on_load) {
3945                synclinkmp_get_text_ptr();
3946                BREAKPOINT();
3947        }
3948
3949        printk("%s %s\n", driver_name, driver_version);
3950
3951        if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3952                printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3953                return rc;
3954        }
3955
3956        serial_driver = alloc_tty_driver(128);
3957        if (!serial_driver) {
3958                rc = -ENOMEM;
3959                goto error;
3960        }
3961
3962        /* Initialize the tty_driver structure */
3963
3964        serial_driver->driver_name = "synclinkmp";
3965        serial_driver->name = "ttySLM";
3966        serial_driver->major = ttymajor;
3967        serial_driver->minor_start = 64;
3968        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3969        serial_driver->subtype = SERIAL_TYPE_NORMAL;
3970        serial_driver->init_termios = tty_std_termios;
3971        serial_driver->init_termios.c_cflag =
3972                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3973        serial_driver->init_termios.c_ispeed = 9600;
3974        serial_driver->init_termios.c_ospeed = 9600;
3975        serial_driver->flags = TTY_DRIVER_REAL_RAW;
3976        tty_set_operations(serial_driver, &ops);
3977        if ((rc = tty_register_driver(serial_driver)) < 0) {
3978                printk("%s(%d):Couldn't register serial driver\n",
3979                        __FILE__,__LINE__);
3980                put_tty_driver(serial_driver);
3981                serial_driver = NULL;
3982                goto error;
3983        }
3984
3985        printk("%s %s, tty major#%d\n",
3986                driver_name, driver_version,
3987                serial_driver->major);
3988
3989        return 0;
3990
3991error:
3992        synclinkmp_cleanup();
3993        return rc;
3994}
3995
3996static void __exit synclinkmp_exit(void)
3997{
3998        synclinkmp_cleanup();
3999}
4000
4001module_init(synclinkmp_init);
4002module_exit(synclinkmp_exit);
4003
4004/* Set the port for internal loopback mode.
4005 * The TxCLK and RxCLK signals are generated from the BRG and
4006 * the TxD is looped back to the RxD internally.
4007 */
4008static void enable_loopback(SLMP_INFO *info, int enable)
4009{
4010        if (enable) {
4011                /* MD2 (Mode Register 2)
4012                 * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4013                 */
4014                write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4015
4016                /* degate external TxC clock source */
4017                info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4018                write_control_reg(info);
4019
4020                /* RXS/TXS (Rx/Tx clock source)
4021                 * 07      Reserved, must be 0
4022                 * 06..04  Clock Source, 100=BRG
4023                 * 03..00  Clock Divisor, 0000=1
4024                 */
4025                write_reg(info, RXS, 0x40);
4026                write_reg(info, TXS, 0x40);
4027
4028        } else {
4029                /* MD2 (Mode Register 2)
4030                 * 01..00  CNCT<1..0> Channel connection, 0=normal
4031                 */
4032                write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4033
4034                /* RXS/TXS (Rx/Tx clock source)
4035                 * 07      Reserved, must be 0
4036                 * 06..04  Clock Source, 000=RxC/TxC Pin
4037                 * 03..00  Clock Divisor, 0000=1
4038                 */
4039                write_reg(info, RXS, 0x00);
4040                write_reg(info, TXS, 0x00);
4041        }
4042
4043        /* set LinkSpeed if available, otherwise default to 2Mbps */
4044        if (info->params.clock_speed)
4045                set_rate(info, info->params.clock_speed);
4046        else
4047                set_rate(info, 3686400);
4048}
4049
4050/* Set the baud rate register to the desired speed
4051 *
4052 *      data_rate       data rate of clock in bits per second
4053 *                      A data rate of 0 disables the AUX clock.
4054 */
4055static void set_rate( SLMP_INFO *info, u32 data_rate )
4056{
4057        u32 TMCValue;
4058        unsigned char BRValue;
4059        u32 Divisor=0;
4060
4061        /* fBRG = fCLK/(TMC * 2^BR)
4062         */
4063        if (data_rate != 0) {
4064                Divisor = 14745600/data_rate;
4065                if (!Divisor)
4066                        Divisor = 1;
4067
4068                TMCValue = Divisor;
4069
4070                BRValue = 0;
4071                if (TMCValue != 1 && TMCValue != 2) {
4072                        /* BRValue of 0 provides 50/50 duty cycle *only* when
4073                         * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4074                         * 50/50 duty cycle.
4075                         */
4076                        BRValue = 1;
4077                        TMCValue >>= 1;
4078                }
4079
4080                /* while TMCValue is too big for TMC register, divide
4081                 * by 2 and increment BR exponent.
4082                 */
4083                for(; TMCValue > 256 && BRValue < 10; BRValue++)
4084                        TMCValue >>= 1;
4085
4086                write_reg(info, TXS,
4087                        (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4088                write_reg(info, RXS,
4089                        (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4090                write_reg(info, TMC, (unsigned char)TMCValue);
4091        }
4092        else {
4093                write_reg(info, TXS,0);
4094                write_reg(info, RXS,0);
4095                write_reg(info, TMC, 0);
4096        }
4097}
4098
4099/* Disable receiver
4100 */
4101static void rx_stop(SLMP_INFO *info)
4102{
4103        if (debug_level >= DEBUG_LEVEL_ISR)
4104                printk("%s(%d):%s rx_stop()\n",
4105                         __FILE__,__LINE__, info->device_name );
4106
4107        write_reg(info, CMD, RXRESET);
4108
4109        info->ie0_value &= ~RXRDYE;
4110        write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4111
4112        write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4113        write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4114        write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4115
4116        info->rx_enabled = false;
4117        info->rx_overflow = false;
4118}
4119
4120/* enable the receiver
4121 */
4122static void rx_start(SLMP_INFO *info)
4123{
4124        int i;
4125
4126        if (debug_level >= DEBUG_LEVEL_ISR)
4127                printk("%s(%d):%s rx_start()\n",
4128                         __FILE__,__LINE__, info->device_name );
4129
4130        write_reg(info, CMD, RXRESET);
4131
4132        if ( info->params.mode == MGSL_MODE_HDLC ) {
4133                /* HDLC, disabe IRQ on rxdata */
4134                info->ie0_value &= ~RXRDYE;
4135                write_reg(info, IE0, info->ie0_value);
4136
4137                /* Reset all Rx DMA buffers and program rx dma */
4138                write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4139                write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4140
4141                for (i = 0; i < info->rx_buf_count; i++) {
4142                        info->rx_buf_list[i].status = 0xff;
4143
4144                        // throttle to 4 shared memory writes at a time to prevent
4145                        // hogging local bus (keep latency time for DMA requests low).
4146                        if (!(i % 4))
4147                                read_status_reg(info);
4148                }
4149                info->current_rx_buf = 0;
4150
4151                /* set current/1st descriptor address */
4152                write_reg16(info, RXDMA + CDA,
4153                        info->rx_buf_list_ex[0].phys_entry);
4154
4155                /* set new last rx descriptor address */
4156                write_reg16(info, RXDMA + EDA,
4157                        info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4158
4159                /* set buffer length (shared by all rx dma data buffers) */
4160                write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4161
4162                write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4163                write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4164        } else {
4165                /* async, enable IRQ on rxdata */
4166                info->ie0_value |= RXRDYE;
4167                write_reg(info, IE0, info->ie0_value);
4168        }
4169
4170        write_reg(info, CMD, RXENABLE);
4171
4172        info->rx_overflow = false;
4173        info->rx_enabled = true;
4174}
4175
4176/* Enable the transmitter and send a transmit frame if
4177 * one is loaded in the DMA buffers.
4178 */
4179static void tx_start(SLMP_INFO *info)
4180{
4181        if (debug_level >= DEBUG_LEVEL_ISR)
4182                printk("%s(%d):%s tx_start() tx_count=%d\n",
4183                         __FILE__,__LINE__, info->device_name,info->tx_count );
4184
4185        if (!info->tx_enabled ) {
4186                write_reg(info, CMD, TXRESET);
4187                write_reg(info, CMD, TXENABLE);
4188                info->tx_enabled = true;
4189        }
4190
4191        if ( info->tx_count ) {
4192
4193                /* If auto RTS enabled and RTS is inactive, then assert */
4194                /* RTS and set a flag indicating that the driver should */
4195                /* negate RTS when the transmission completes. */
4196
4197                info->drop_rts_on_tx_done = false;
4198
4199                if (info->params.mode != MGSL_MODE_ASYNC) {
4200
4201                        if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4202                                get_signals( info );
4203                                if ( !(info->serial_signals & SerialSignal_RTS) ) {
4204                                        info->serial_signals |= SerialSignal_RTS;
4205                                        set_signals( info );
4206                                        info->drop_rts_on_tx_done = true;
4207                                }
4208                        }
4209
4210                        write_reg16(info, TRC0,
4211                                (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4212
4213                        write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4214                        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4215        
4216                        /* set TX CDA (current descriptor address) */
4217                        write_reg16(info, TXDMA + CDA,
4218                                info->tx_buf_list_ex[0].phys_entry);
4219        
4220                        /* set TX EDA (last descriptor address) */
4221                        write_reg16(info, TXDMA + EDA,
4222                                info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4223        
4224                        /* enable underrun IRQ */
4225                        info->ie1_value &= ~IDLE;
4226                        info->ie1_value |= UDRN;
4227                        write_reg(info, IE1, info->ie1_value);
4228                        write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4229        
4230                        write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4231                        write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4232        
4233                        mod_timer(&info->tx_timer, jiffies +
4234                                        msecs_to_jiffies(5000));
4235                }
4236                else {
4237                        tx_load_fifo(info);
4238                        /* async, enable IRQ on txdata */
4239                        info->ie0_value |= TXRDYE;
4240                        write_reg(info, IE0, info->ie0_value);
4241                }
4242
4243                info->tx_active = true;
4244        }
4245}
4246
4247/* stop the transmitter and DMA
4248 */
4249static void tx_stop( SLMP_INFO *info )
4250{
4251        if (debug_level >= DEBUG_LEVEL_ISR)
4252                printk("%s(%d):%s tx_stop()\n",
4253                         __FILE__,__LINE__, info->device_name );
4254
4255        del_timer(&info->tx_timer);
4256
4257        write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4258        write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4259
4260        write_reg(info, CMD, TXRESET);
4261
4262        info->ie1_value &= ~(UDRN + IDLE);
4263        write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4264        write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4265
4266        info->ie0_value &= ~TXRDYE;
4267        write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4268
4269        info->tx_enabled = false;
4270        info->tx_active = false;
4271}
4272
4273/* Fill the transmit FIFO until the FIFO is full or
4274 * there is no more data to load.
4275 */
4276static void tx_load_fifo(SLMP_INFO *info)
4277{
4278        u8 TwoBytes[2];
4279
4280        /* do nothing is now tx data available and no XON/XOFF pending */
4281
4282        if ( !info->tx_count && !info->x_char )
4283                return;
4284
4285        /* load the Transmit FIFO until FIFOs full or all data sent */
4286
4287        while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4288
4289                /* there is more space in the transmit FIFO and */
4290                /* there is more data in transmit buffer */
4291
4292                if ( (info->tx_count > 1) && !info->x_char ) {
4293                        /* write 16-bits */
4294                        TwoBytes[0] = info->tx_buf[info->tx_get++];
4295                        if (info->tx_get >= info->max_frame_size)
4296                                info->tx_get -= info->max_frame_size;
4297                        TwoBytes[1] = info->tx_buf[info->tx_get++];
4298                        if (info->tx_get >= info->max_frame_size)
4299                                info->tx_get -= info->max_frame_size;
4300
4301                        write_reg16(info, TRB, *((u16 *)TwoBytes));
4302
4303                        info->tx_count -= 2;
4304                        info->icount.tx += 2;
4305                } else {
4306                        /* only 1 byte left to transmit or 1 FIFO slot left */
4307
4308                        if (info->x_char) {
4309                                /* transmit pending high priority char */
4310                                write_reg(info, TRB, info->x_char);
4311                                info->x_char = 0;
4312                        } else {
4313                                write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4314                                if (info->tx_get >= info->max_frame_size)
4315                                        info->tx_get -= info->max_frame_size;
4316                                info->tx_count--;
4317                        }
4318                        info->icount.tx++;
4319                }
4320        }
4321}
4322
4323/* Reset a port to a known state
4324 */
4325static void reset_port(SLMP_INFO *info)
4326{
4327        if (info->sca_base) {
4328
4329                tx_stop(info);
4330                rx_stop(info);
4331
4332                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4333                set_signals(info);
4334
4335                /* disable all port interrupts */
4336                info->ie0_value = 0;
4337                info->ie1_value = 0;
4338                info->ie2_value = 0;
4339                write_reg(info, IE0, info->ie0_value);
4340                write_reg(info, IE1, info->ie1_value);
4341                write_reg(info, IE2, info->ie2_value);
4342
4343                write_reg(info, CMD, CHRESET);
4344        }
4345}
4346
4347/* Reset all the ports to a known state.
4348 */
4349static void reset_adapter(SLMP_INFO *info)
4350{
4351        int i;
4352
4353        for ( i=0; i < SCA_MAX_PORTS; ++i) {
4354                if (info->port_array[i])
4355                        reset_port(info->port_array[i]);
4356        }
4357}
4358
4359/* Program port for asynchronous communications.
4360 */
4361static void async_mode(SLMP_INFO *info)
4362{
4363
4364        unsigned char RegValue;
4365
4366        tx_stop(info);
4367        rx_stop(info);
4368
4369        /* MD0, Mode Register 0
4370         *
4371         * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4372         * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4373         * 03      Reserved, must be 0
4374         * 02      CRCCC, CRC Calculation, 0=disabled
4375         * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4376         *
4377         * 0000 0000
4378         */
4379        RegValue = 0x00;
4380        if (info->params.stop_bits != 1)
4381                RegValue |= BIT1;
4382        write_reg(info, MD0, RegValue);
4383
4384        /* MD1, Mode Register 1
4385         *
4386         * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4387         * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4388         * 03..02  RXCHR<1..0>, rx char size
4389         * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4390         *
4391         * 0100 0000
4392         */
4393        RegValue = 0x40;
4394        switch (info->params.data_bits) {
4395        case 7: RegValue |= BIT4 + BIT2; break;
4396        case 6: RegValue |= BIT5 + BIT3; break;
4397        case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4398        }
4399        if (info->params.parity != ASYNC_PARITY_NONE) {
4400                RegValue |= BIT1;
4401                if (info->params.parity == ASYNC_PARITY_ODD)
4402                        RegValue |= BIT0;
4403        }
4404        write_reg(info, MD1, RegValue);
4405
4406        /* MD2, Mode Register 2
4407         *
4408         * 07..02  Reserved, must be 0
4409         * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4410         *
4411         * 0000 0000
4412         */
4413        RegValue = 0x00;
4414        if (info->params.loopback)
4415                RegValue |= (BIT1 + BIT0);
4416        write_reg(info, MD2, RegValue);
4417
4418        /* RXS, Receive clock source
4419         *
4420         * 07      Reserved, must be 0
4421         * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4422         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4423         */
4424        RegValue=BIT6;
4425        write_reg(info, RXS, RegValue);
4426
4427        /* TXS, Transmit clock source
4428         *
4429         * 07      Reserved, must be 0
4430         * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4431         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4432         */
4433        RegValue=BIT6;
4434        write_reg(info, TXS, RegValue);
4435
4436        /* Control Register
4437         *
4438         * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4439         */
4440        info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4441        write_control_reg(info);
4442
4443        tx_set_idle(info);
4444
4445        /* RRC Receive Ready Control 0
4446         *
4447         * 07..05  Reserved, must be 0
4448         * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4449         */
4450        write_reg(info, RRC, 0x00);
4451
4452        /* TRC0 Transmit Ready Control 0
4453         *
4454         * 07..05  Reserved, must be 0
4455         * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4456         */
4457        write_reg(info, TRC0, 0x10);
4458
4459        /* TRC1 Transmit Ready Control 1
4460         *
4461         * 07..05  Reserved, must be 0
4462         * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4463         */
4464        write_reg(info, TRC1, 0x1e);
4465
4466        /* CTL, MSCI control register
4467         *
4468         * 07..06  Reserved, set to 0
4469         * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4470         * 04      IDLC, idle control, 0=mark 1=idle register
4471         * 03      BRK, break, 0=off 1 =on (async)
4472         * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4473         * 01      GOP, go active on poll (LOOP mode) 1=enabled
4474         * 00      RTS, RTS output control, 0=active 1=inactive
4475         *
4476         * 0001 0001
4477         */
4478        RegValue = 0x10;
4479        if (!(info->serial_signals & SerialSignal_RTS))
4480                RegValue |= 0x01;
4481        write_reg(info, CTL, RegValue);
4482
4483        /* enable status interrupts */
4484        info->ie0_value |= TXINTE + RXINTE;
4485        write_reg(info, IE0, info->ie0_value);
4486
4487        /* enable break detect interrupt */
4488        info->ie1_value = BRKD;
4489        write_reg(info, IE1, info->ie1_value);
4490
4491        /* enable rx overrun interrupt */
4492        info->ie2_value = OVRN;
4493        write_reg(info, IE2, info->ie2_value);
4494
4495        set_rate( info, info->params.data_rate * 16 );
4496}
4497
4498/* Program the SCA for HDLC communications.
4499 */
4500static void hdlc_mode(SLMP_INFO *info)
4501{
4502        unsigned char RegValue;
4503        u32 DpllDivisor;
4504
4505        // Can't use DPLL because SCA outputs recovered clock on RxC when
4506        // DPLL mode selected. This causes output contention with RxC receiver.
4507        // Use of DPLL would require external hardware to disable RxC receiver
4508        // when DPLL mode selected.
4509        info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4510
4511        /* disable DMA interrupts */
4512        write_reg(info, TXDMA + DIR, 0);
4513        write_reg(info, RXDMA + DIR, 0);
4514
4515        /* MD0, Mode Register 0
4516         *
4517         * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4518         * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4519         * 03      Reserved, must be 0
4520         * 02      CRCCC, CRC Calculation, 1=enabled
4521         * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4522         * 00      CRC0, CRC initial value, 1 = all 1s
4523         *
4524         * 1000 0001
4525         */
4526        RegValue = 0x81;
4527        if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4528                RegValue |= BIT4;
4529        if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4530                RegValue |= BIT4;
4531        if (info->params.crc_type == HDLC_CRC_16_CCITT)
4532                RegValue |= BIT2 + BIT1;
4533        write_reg(info, MD0, RegValue);
4534
4535        /* MD1, Mode Register 1
4536         *
4537         * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4538         * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4539         * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4540         * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4541         *
4542         * 0000 0000
4543         */
4544        RegValue = 0x00;
4545        write_reg(info, MD1, RegValue);
4546
4547        /* MD2, Mode Register 2
4548         *
4549         * 07      NRZFM, 0=NRZ, 1=FM
4550         * 06..05  CODE<1..0> Encoding, 00=NRZ
4551         * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4552         * 02      Reserved, must be 0
4553         * 01..00  CNCT<1..0> Channel connection, 0=normal
4554         *
4555         * 0000 0000
4556         */
4557        RegValue = 0x00;
4558        switch(info->params.encoding) {
4559        case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4560        case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4561        case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4562        case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4563#if 0
4564        case HDLC_ENCODING_NRZB:                                        /* not supported */
4565        case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4566        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4567#endif
4568        }
4569        if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4570                DpllDivisor = 16;
4571                RegValue |= BIT3;
4572        } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4573                DpllDivisor = 8;
4574        } else {
4575                DpllDivisor = 32;
4576                RegValue |= BIT4;
4577        }
4578        write_reg(info, MD2, RegValue);
4579
4580
4581        /* RXS, Receive clock source
4582         *
4583         * 07      Reserved, must be 0
4584         * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4585         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4586         */
4587        RegValue=0;
4588        if (info->params.flags & HDLC_FLAG_RXC_BRG)
4589                RegValue |= BIT6;
4590        if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4591                RegValue |= BIT6 + BIT5;
4592        write_reg(info, RXS, RegValue);
4593
4594        /* TXS, Transmit clock source
4595         *
4596         * 07      Reserved, must be 0
4597         * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4598         * 03..00  RXBR<3..0>, rate divisor, 0000=1
4599         */
4600        RegValue=0;
4601        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4602                RegValue |= BIT6;
4603        if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4604                RegValue |= BIT6 + BIT5;
4605        write_reg(info, TXS, RegValue);
4606
4607        if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4608                set_rate(info, info->params.clock_speed * DpllDivisor);
4609        else
4610                set_rate(info, info->params.clock_speed);
4611
4612        /* GPDATA (General Purpose I/O Data Register)
4613         *
4614         * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4615         */
4616        if (info->params.flags & HDLC_FLAG_TXC_BRG)
4617                info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4618        else
4619                info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4620        write_control_reg(info);
4621
4622        /* RRC Receive Ready Control 0
4623         *
4624         * 07..05  Reserved, must be 0
4625         * 04..00  RRC<4..0> Rx FIFO trigger active
4626         */
4627        write_reg(info, RRC, rx_active_fifo_level);
4628
4629        /* TRC0 Transmit Ready Control 0
4630         *
4631         * 07..05  Reserved, must be 0
4632         * 04..00  TRC<4..0> Tx FIFO trigger active
4633         */
4634        write_reg(info, TRC0, tx_active_fifo_level);
4635
4636        /* TRC1 Transmit Ready Control 1
4637         *
4638         * 07..05  Reserved, must be 0
4639         * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4640         */
4641        write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4642
4643        /* DMR, DMA Mode Register
4644         *
4645         * 07..05  Reserved, must be 0
4646         * 04      TMOD, Transfer Mode: 1=chained-block
4647         * 03      Reserved, must be 0
4648         * 02      NF, Number of Frames: 1=multi-frame
4649         * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4650         * 00      Reserved, must be 0
4651         *
4652         * 0001 0100
4653         */
4654        write_reg(info, TXDMA + DMR, 0x14);
4655        write_reg(info, RXDMA + DMR, 0x14);
4656
4657        /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4658        write_reg(info, RXDMA + CPB,
4659                (unsigned char)(info->buffer_list_phys >> 16));
4660
4661        /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4662        write_reg(info, TXDMA + CPB,
4663                (unsigned char)(info->buffer_list_phys >> 16));
4664
4665        /* enable status interrupts. other code enables/disables
4666         * the individual sources for these two interrupt classes.
4667         */
4668        info->ie0_value |= TXINTE + RXINTE;
4669        write_reg(info, IE0, info->ie0_value);
4670
4671        /* CTL, MSCI control register
4672         *
4673         * 07..06  Reserved, set to 0
4674         * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4675         * 04      IDLC, idle control, 0=mark 1=idle register
4676         * 03      BRK, break, 0=off 1 =on (async)
4677         * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4678         * 01      GOP, go active on poll (LOOP mode) 1=enabled
4679         * 00      RTS, RTS output control, 0=active 1=inactive
4680         *
4681         * 0001 0001
4682         */
4683        RegValue = 0x10;
4684        if (!(info->serial_signals & SerialSignal_RTS))
4685                RegValue |= 0x01;
4686        write_reg(info, CTL, RegValue);
4687
4688        /* preamble not supported ! */
4689
4690        tx_set_idle(info);
4691        tx_stop(info);
4692        rx_stop(info);
4693
4694        set_rate(info, info->params.clock_speed);
4695
4696        if (info->params.loopback)
4697                enable_loopback(info,1);
4698}
4699
4700/* Set the transmit HDLC idle mode
4701 */
4702static void tx_set_idle(SLMP_INFO *info)
4703{
4704        unsigned char RegValue = 0xff;
4705
4706        /* Map API idle mode to SCA register bits */
4707        switch(info->idle_mode) {
4708        case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4709        case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4710        case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4711        case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4712        case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4713        case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4714        case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4715        }
4716
4717        write_reg(info, IDL, RegValue);
4718}
4719
4720/* Query the adapter for the state of the V24 status (input) signals.
4721 */
4722static void get_signals(SLMP_INFO *info)
4723{
4724        u16 status = read_reg(info, SR3);
4725        u16 gpstatus = read_status_reg(info);
4726        u16 testbit;
4727
4728        /* clear all serial signals except RTS and DTR */
4729        info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4730
4731        /* set serial signal bits to reflect MISR */
4732
4733        if (!(status & BIT3))
4734                info->serial_signals |= SerialSignal_CTS;
4735
4736        if ( !(status & BIT2))
4737                info->serial_signals |= SerialSignal_DCD;
4738
4739        testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4740        if (!(gpstatus & testbit))
4741                info->serial_signals |= SerialSignal_RI;
4742
4743        testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4744        if (!(gpstatus & testbit))
4745                info->serial_signals |= SerialSignal_DSR;
4746}
4747
4748/* Set the state of RTS and DTR based on contents of
4749 * serial_signals member of device context.
4750 */
4751static void set_signals(SLMP_INFO *info)
4752{
4753        unsigned char RegValue;
4754        u16 EnableBit;
4755
4756        RegValue = read_reg(info, CTL);
4757        if (info->serial_signals & SerialSignal_RTS)
4758                RegValue &= ~BIT0;
4759        else
4760                RegValue |= BIT0;
4761        write_reg(info, CTL, RegValue);
4762
4763        // Port 0..3 DTR is ctrl reg <1,3,5,7>
4764        EnableBit = BIT1 << (info->port_num*2);
4765        if (info->serial_signals & SerialSignal_DTR)
4766                info->port_array[0]->ctrlreg_value &= ~EnableBit;
4767        else
4768                info->port_array[0]->ctrlreg_value |= EnableBit;
4769        write_control_reg(info);
4770}
4771
4772/*******************/
4773/* DMA Buffer Code */
4774/*******************/
4775
4776/* Set the count for all receive buffers to SCABUFSIZE
4777 * and set the current buffer to the first buffer. This effectively
4778 * makes all buffers free and discards any data in buffers.
4779 */
4780static void rx_reset_buffers(SLMP_INFO *info)
4781{
4782        rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4783}
4784
4785/* Free the buffers used by a received frame
4786 *
4787 * info   pointer to device instance data
4788 * first  index of 1st receive buffer of frame
4789 * last   index of last receive buffer of frame
4790 */
4791static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4792{
4793        bool done = false;
4794
4795        while(!done) {
4796                /* reset current buffer for reuse */
4797                info->rx_buf_list[first].status = 0xff;
4798
4799                if (first == last) {
4800                        done = true;
4801                        /* set new last rx descriptor address */
4802                        write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4803                }
4804
4805                first++;
4806                if (first == info->rx_buf_count)
4807                        first = 0;
4808        }
4809
4810        /* set current buffer to next buffer after last buffer of frame */
4811        info->current_rx_buf = first;
4812}
4813
4814/* Return a received frame from the receive DMA buffers.
4815 * Only frames received without errors are returned.
4816 *
4817 * Return Value:        true if frame returned, otherwise false
4818 */
4819static bool rx_get_frame(SLMP_INFO *info)
4820{
4821        unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4822        unsigned short status;
4823        unsigned int framesize = 0;
4824        bool ReturnCode = false;
4825        unsigned long flags;
4826        struct tty_struct *tty = info->port.tty;
4827        unsigned char addr_field = 0xff;
4828        SCADESC *desc;
4829        SCADESC_EX *desc_ex;
4830
4831CheckAgain:
4832        /* assume no frame returned, set zero length */
4833        framesize = 0;
4834        addr_field = 0xff;
4835
4836        /*
4837         * current_rx_buf points to the 1st buffer of the next available
4838         * receive frame. To find the last buffer of the frame look for
4839         * a non-zero status field in the buffer entries. (The status
4840         * field is set by the 16C32 after completing a receive frame.
4841         */
4842        StartIndex = EndIndex = info->current_rx_buf;
4843
4844        for ( ;; ) {
4845                desc = &info->rx_buf_list[EndIndex];
4846                desc_ex = &info->rx_buf_list_ex[EndIndex];
4847
4848                if (desc->status == 0xff)
4849                        goto Cleanup;   /* current desc still in use, no frames available */
4850
4851                if (framesize == 0 && info->params.addr_filter != 0xff)
4852                        addr_field = desc_ex->virt_addr[0];
4853
4854                framesize += desc->length;
4855
4856                /* Status != 0 means last buffer of frame */
4857                if (desc->status)
4858                        break;
4859
4860                EndIndex++;
4861                if (EndIndex == info->rx_buf_count)
4862                        EndIndex = 0;
4863
4864                if (EndIndex == info->current_rx_buf) {
4865                        /* all buffers have been 'used' but none mark      */
4866                        /* the end of a frame. Reset buffers and receiver. */
4867                        if ( info->rx_enabled ){
4868                                spin_lock_irqsave(&info->lock,flags);
4869                                rx_start(info);
4870                                spin_unlock_irqrestore(&info->lock,flags);
4871                        }
4872                        goto Cleanup;
4873                }
4874
4875        }
4876
4877        /* check status of receive frame */
4878
4879        /* frame status is byte stored after frame data
4880         *
4881         * 7 EOM (end of msg), 1 = last buffer of frame
4882         * 6 Short Frame, 1 = short frame
4883         * 5 Abort, 1 = frame aborted
4884         * 4 Residue, 1 = last byte is partial
4885         * 3 Overrun, 1 = overrun occurred during frame reception
4886         * 2 CRC,     1 = CRC error detected
4887         *
4888         */
4889        status = desc->status;
4890
4891        /* ignore CRC bit if not using CRC (bit is undefined) */
4892        /* Note:CRC is not save to data buffer */
4893        if (info->params.crc_type == HDLC_CRC_NONE)
4894                status &= ~BIT2;
4895
4896        if (framesize == 0 ||
4897                 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4898                /* discard 0 byte frames, this seems to occur sometime
4899                 * when remote is idling flags.
4900                 */
4901                rx_free_frame_buffers(info, StartIndex, EndIndex);
4902                goto CheckAgain;
4903        }
4904
4905        if (framesize < 2)
4906                status |= BIT6;
4907
4908        if (status & (BIT6+BIT5+BIT3+BIT2)) {
4909                /* received frame has errors,
4910                 * update counts and mark frame size as 0
4911                 */
4912                if (status & BIT6)
4913                        info->icount.rxshort++;
4914                else if (status & BIT5)
4915                        info->icount.rxabort++;
4916                else if (status & BIT3)
4917                        info->icount.rxover++;
4918                else
4919                        info->icount.rxcrc++;
4920
4921                framesize = 0;
4922#if SYNCLINK_GENERIC_HDLC
4923                {
4924                        info->netdev->stats.rx_errors++;
4925                        info->netdev->stats.rx_frame_errors++;
4926                }
4927#endif
4928        }
4929
4930        if ( debug_level >= DEBUG_LEVEL_BH )
4931                printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4932                        __FILE__,__LINE__,info->device_name,status,framesize);
4933
4934        if ( debug_level >= DEBUG_LEVEL_DATA )
4935                trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4936                        min_t(unsigned int, framesize, SCABUFSIZE), 0);
4937
4938        if (framesize) {
4939                if (framesize > info->max_frame_size)
4940                        info->icount.rxlong++;
4941                else {
4942                        /* copy dma buffer(s) to contiguous intermediate buffer */
4943                        int copy_count = framesize;
4944                        int index = StartIndex;
4945                        unsigned char *ptmp = info->tmp_rx_buf;
4946                        info->tmp_rx_buf_count = framesize;
4947
4948                        info->icount.rxok++;
4949
4950                        while(copy_count) {
4951                                int partial_count = min(copy_count,SCABUFSIZE);
4952                                memcpy( ptmp,
4953                                        info->rx_buf_list_ex[index].virt_addr,
4954                                        partial_count );
4955                                ptmp += partial_count;
4956                                copy_count -= partial_count;
4957
4958                                if ( ++index == info->rx_buf_count )
4959                                        index = 0;
4960                        }
4961
4962#if SYNCLINK_GENERIC_HDLC
4963                        if (info->netcount)
4964                                hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4965                        else
4966#endif
4967                                ldisc_receive_buf(tty,info->tmp_rx_buf,
4968                                                  info->flag_buf, framesize);
4969                }
4970        }
4971        /* Free the buffers used by this frame. */
4972        rx_free_frame_buffers( info, StartIndex, EndIndex );
4973
4974        ReturnCode = true;
4975
4976Cleanup:
4977        if ( info->rx_enabled && info->rx_overflow ) {
4978                /* Receiver is enabled, but needs to restarted due to
4979                 * rx buffer overflow. If buffers are empty, restart receiver.
4980                 */
4981                if (info->rx_buf_list[EndIndex].status == 0xff) {
4982                        spin_lock_irqsave(&info->lock,flags);
4983                        rx_start(info);
4984                        spin_unlock_irqrestore(&info->lock,flags);
4985                }
4986        }
4987
4988        return ReturnCode;
4989}
4990
4991/* load the transmit DMA buffer with data
4992 */
4993static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4994{
4995        unsigned short copy_count;
4996        unsigned int i = 0;
4997        SCADESC *desc;
4998        SCADESC_EX *desc_ex;
4999
5000        if ( debug_level >= DEBUG_LEVEL_DATA )
5001                trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5002
5003        /* Copy source buffer to one or more DMA buffers, starting with
5004         * the first transmit dma buffer.
5005         */
5006        for(i=0;;)
5007        {
5008                copy_count = min_t(unsigned int, count, SCABUFSIZE);
5009
5010                desc = &info->tx_buf_list[i];
5011                desc_ex = &info->tx_buf_list_ex[i];
5012
5013                load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5014
5015                desc->length = copy_count;
5016                desc->status = 0;
5017
5018                buf += copy_count;
5019                count -= copy_count;
5020
5021                if (!count)
5022                        break;
5023
5024                i++;
5025                if (i >= info->tx_buf_count)
5026                        i = 0;
5027        }
5028
5029        info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5030        info->last_tx_buf = ++i;
5031}
5032
5033static bool register_test(SLMP_INFO *info)
5034{
5035        static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5036        static unsigned int count = ARRAY_SIZE(testval);
5037        unsigned int i;
5038        bool rc = true;
5039        unsigned long flags;
5040
5041        spin_lock_irqsave(&info->lock,flags);
5042        reset_port(info);
5043
5044        /* assume failure */
5045        info->init_error = DiagStatus_AddressFailure;
5046
5047        /* Write bit patterns to various registers but do it out of */
5048        /* sync, then read back and verify values. */
5049
5050        for (i = 0 ; i < count ; i++) {
5051                write_reg(info, TMC, testval[i]);
5052                write_reg(info, IDL, testval[(i+1)%count]);
5053                write_reg(info, SA0, testval[(i+2)%count]);
5054                write_reg(info, SA1, testval[(i+3)%count]);
5055
5056                if ( (read_reg(info, TMC) != testval[i]) ||
5057                          (read_reg(info, IDL) != testval[(i+1)%count]) ||
5058                          (read_reg(info, SA0) != testval[(i+2)%count]) ||
5059                          (read_reg(info, SA1) != testval[(i+3)%count]) )
5060                {
5061                        rc = false;
5062                        break;
5063                }
5064        }
5065
5066        reset_port(info);
5067        spin_unlock_irqrestore(&info->lock,flags);
5068
5069        return rc;
5070}
5071
5072static bool irq_test(SLMP_INFO *info)
5073{
5074        unsigned long timeout;
5075        unsigned long flags;
5076
5077        unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5078
5079        spin_lock_irqsave(&info->lock,flags);
5080        reset_port(info);
5081
5082        /* assume failure */
5083        info->init_error = DiagStatus_IrqFailure;
5084        info->irq_occurred = false;
5085
5086        /* setup timer0 on SCA0 to interrupt */
5087
5088        /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5089        write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5090
5091        write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5092        write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5093
5094
5095        /* TMCS, Timer Control/Status Register
5096         *
5097         * 07      CMF, Compare match flag (read only) 1=match
5098         * 06      ECMI, CMF Interrupt Enable: 1=enabled
5099         * 05      Reserved, must be 0
5100         * 04      TME, Timer Enable
5101         * 03..00  Reserved, must be 0
5102         *
5103         * 0101 0000
5104         */
5105        write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5106
5107        spin_unlock_irqrestore(&info->lock,flags);
5108
5109        timeout=100;
5110        while( timeout-- && !info->irq_occurred ) {
5111                msleep_interruptible(10);
5112        }
5113
5114        spin_lock_irqsave(&info->lock,flags);
5115        reset_port(info);
5116        spin_unlock_irqrestore(&info->lock,flags);
5117
5118        return info->irq_occurred;
5119}
5120
5121/* initialize individual SCA device (2 ports)
5122 */
5123static bool sca_init(SLMP_INFO *info)
5124{
5125        /* set wait controller to single mem partition (low), no wait states */
5126        write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5127        write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5128        write_reg(info, WCRL, 0);       /* wait controller low range */
5129        write_reg(info, WCRM, 0);       /* wait controller mid range */
5130        write_reg(info, WCRH, 0);       /* wait controller high range */
5131
5132        /* DPCR, DMA Priority Control
5133         *
5134         * 07..05  Not used, must be 0
5135         * 04      BRC, bus release condition: 0=all transfers complete
5136         * 03      CCC, channel change condition: 0=every cycle
5137         * 02..00  PR<2..0>, priority 100=round robin
5138         *
5139         * 00000100 = 0x04
5140         */
5141        write_reg(info, DPCR, dma_priority);
5142
5143        /* DMA Master Enable, BIT7: 1=enable all channels */
5144        write_reg(info, DMER, 0x80);
5145
5146        /* enable all interrupt classes */
5147        write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5148        write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5149        write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5150
5151        /* ITCR, interrupt control register
5152         * 07      IPC, interrupt priority, 0=MSCI->DMA
5153         * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5154         * 04      VOS, Vector Output, 0=unmodified vector
5155         * 03..00  Reserved, must be 0
5156         */
5157        write_reg(info, ITCR, 0);
5158
5159        return true;
5160}
5161
5162/* initialize adapter hardware
5163 */
5164static bool init_adapter(SLMP_INFO *info)
5165{
5166        int i;
5167
5168        /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5169        volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5170        u32 readval;
5171
5172        info->misc_ctrl_value |= BIT30;
5173        *MiscCtrl = info->misc_ctrl_value;
5174
5175        /*
5176         * Force at least 170ns delay before clearing
5177         * reset bit. Each read from LCR takes at least
5178         * 30ns so 10 times for 300ns to be safe.
5179         */
5180        for(i=0;i<10;i++)
5181                readval = *MiscCtrl;
5182
5183        info->misc_ctrl_value &= ~BIT30;
5184        *MiscCtrl = info->misc_ctrl_value;
5185
5186        /* init control reg (all DTRs off, all clksel=input) */
5187        info->ctrlreg_value = 0xaa;
5188        write_control_reg(info);
5189
5190        {
5191                volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5192                lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5193
5194                switch(read_ahead_count)
5195                {
5196                case 16:
5197                        lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5198                        break;
5199                case 8:
5200                        lcr1_brdr_value |= BIT5 + BIT4;
5201                        break;
5202                case 4:
5203                        lcr1_brdr_value |= BIT5 + BIT3;
5204                        break;
5205                case 0:
5206                        lcr1_brdr_value |= BIT5;
5207                        break;
5208                }
5209
5210                *LCR1BRDR = lcr1_brdr_value;
5211                *MiscCtrl = misc_ctrl_value;
5212        }
5213
5214        sca_init(info->port_array[0]);
5215        sca_init(info->port_array[2]);
5216
5217        return true;
5218}
5219
5220/* Loopback an HDLC frame to test the hardware
5221 * interrupt and DMA functions.
5222 */
5223static bool loopback_test(SLMP_INFO *info)
5224{
5225#define TESTFRAMESIZE 20
5226
5227        unsigned long timeout;
5228        u16 count = TESTFRAMESIZE;
5229        unsigned char buf[TESTFRAMESIZE];
5230        bool rc = false;
5231        unsigned long flags;
5232
5233        struct tty_struct *oldtty = info->port.tty;
5234        u32 speed = info->params.clock_speed;
5235
5236        info->params.clock_speed = 3686400;
5237        info->port.tty = NULL;
5238
5239        /* assume failure */
5240        info->init_error = DiagStatus_DmaFailure;
5241
5242        /* build and send transmit frame */
5243        for (count = 0; count < TESTFRAMESIZE;++count)
5244                buf[count] = (unsigned char)count;
5245
5246        memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5247
5248        /* program hardware for HDLC and enabled receiver */
5249        spin_lock_irqsave(&info->lock,flags);
5250        hdlc_mode(info);
5251        enable_loopback(info,1);
5252        rx_start(info);
5253        info->tx_count = count;
5254        tx_load_dma_buffer(info,buf,count);
5255        tx_start(info);
5256        spin_unlock_irqrestore(&info->lock,flags);
5257
5258        /* wait for receive complete */
5259        /* Set a timeout for waiting for interrupt. */
5260        for ( timeout = 100; timeout; --timeout ) {
5261                msleep_interruptible(10);
5262
5263                if (rx_get_frame(info)) {
5264                        rc = true;
5265                        break;
5266                }
5267        }
5268
5269        /* verify received frame length and contents */
5270        if (rc &&
5271            ( info->tmp_rx_buf_count != count ||
5272              memcmp(buf, info->tmp_rx_buf,count))) {
5273                rc = false;
5274        }
5275
5276        spin_lock_irqsave(&info->lock,flags);
5277        reset_adapter(info);
5278        spin_unlock_irqrestore(&info->lock,flags);
5279
5280        info->params.clock_speed = speed;
5281        info->port.tty = oldtty;
5282
5283        return rc;
5284}
5285
5286/* Perform diagnostics on hardware
5287 */
5288static int adapter_test( SLMP_INFO *info )
5289{
5290        unsigned long flags;
5291        if ( debug_level >= DEBUG_LEVEL_INFO )
5292                printk( "%s(%d):Testing device %s\n",
5293                        __FILE__,__LINE__,info->device_name );
5294
5295        spin_lock_irqsave(&info->lock,flags);
5296        init_adapter(info);
5297        spin_unlock_irqrestore(&info->lock,flags);
5298
5299        info->port_array[0]->port_count = 0;
5300
5301        if ( register_test(info->port_array[0]) &&
5302                register_test(info->port_array[1])) {
5303
5304                info->port_array[0]->port_count = 2;
5305
5306                if ( register_test(info->port_array[2]) &&
5307                        register_test(info->port_array[3]) )
5308                        info->port_array[0]->port_count += 2;
5309        }
5310        else {
5311                printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5312                        __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5313                return -ENODEV;
5314        }
5315
5316        if ( !irq_test(info->port_array[0]) ||
5317                !irq_test(info->port_array[1]) ||
5318                 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5319                 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5320                printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5321                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5322                return -ENODEV;
5323        }
5324
5325        if (!loopback_test(info->port_array[0]) ||
5326                !loopback_test(info->port_array[1]) ||
5327                 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5328                 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5329                printk( "%s(%d):DMA test failure for device %s\n",
5330                        __FILE__,__LINE__,info->device_name);
5331                return -ENODEV;
5332        }
5333
5334        if ( debug_level >= DEBUG_LEVEL_INFO )
5335                printk( "%s(%d):device %s passed diagnostics\n",
5336                        __FILE__,__LINE__,info->device_name );
5337
5338        info->port_array[0]->init_error = 0;
5339        info->port_array[1]->init_error = 0;
5340        if ( info->port_count > 2 ) {
5341                info->port_array[2]->init_error = 0;
5342                info->port_array[3]->init_error = 0;
5343        }
5344
5345        return 0;
5346}
5347
5348/* Test the shared memory on a PCI adapter.
5349 */
5350static bool memory_test(SLMP_INFO *info)
5351{
5352        static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5353                0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5354        unsigned long count = ARRAY_SIZE(testval);
5355        unsigned long i;
5356        unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5357        unsigned long * addr = (unsigned long *)info->memory_base;
5358
5359        /* Test data lines with test pattern at one location. */
5360
5361        for ( i = 0 ; i < count ; i++ ) {
5362                *addr = testval[i];
5363                if ( *addr != testval[i] )
5364                        return false;
5365        }
5366
5367        /* Test address lines with incrementing pattern over */
5368        /* entire address range. */
5369
5370        for ( i = 0 ; i < limit ; i++ ) {
5371                *addr = i * 4;
5372                addr++;
5373        }
5374
5375        addr = (unsigned long *)info->memory_base;
5376
5377        for ( i = 0 ; i < limit ; i++ ) {
5378                if ( *addr != i * 4 )
5379                        return false;
5380                addr++;
5381        }
5382
5383        memset( info->memory_base, 0, SCA_MEM_SIZE );
5384        return true;
5385}
5386
5387/* Load data into PCI adapter shared memory.
5388 *
5389 * The PCI9050 releases control of the local bus
5390 * after completing the current read or write operation.
5391 *
5392 * While the PCI9050 write FIFO not empty, the
5393 * PCI9050 treats all of the writes as a single transaction
5394 * and does not release the bus. This causes DMA latency problems
5395 * at high speeds when copying large data blocks to the shared memory.
5396 *
5397 * This function breaks a write into multiple transations by
5398 * interleaving a read which flushes the write FIFO and 'completes'
5399 * the write transation. This allows any pending DMA request to gain control
5400 * of the local bus in a timely fasion.
5401 */
5402static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5403{
5404        /* A load interval of 16 allows for 4 32-bit writes at */
5405        /* 136ns each for a maximum latency of 542ns on the local bus.*/
5406
5407        unsigned short interval = count / sca_pci_load_interval;
5408        unsigned short i;
5409
5410        for ( i = 0 ; i < interval ; i++ )
5411        {
5412                memcpy(dest, src, sca_pci_load_interval);
5413                read_status_reg(info);
5414                dest += sca_pci_load_interval;
5415                src += sca_pci_load_interval;
5416        }
5417
5418        memcpy(dest, src, count % sca_pci_load_interval);
5419}
5420
5421static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5422{
5423        int i;
5424        int linecount;
5425        if (xmit)
5426                printk("%s tx data:\n",info->device_name);
5427        else
5428                printk("%s rx data:\n",info->device_name);
5429
5430        while(count) {
5431                if (count > 16)
5432                        linecount = 16;
5433                else
5434                        linecount = count;
5435
5436                for(i=0;i<linecount;i++)
5437                        printk("%02X ",(unsigned char)data[i]);
5438                for(;i<17;i++)
5439                        printk("   ");
5440                for(i=0;i<linecount;i++) {
5441                        if (data[i]>=040 && data[i]<=0176)
5442                                printk("%c",data[i]);
5443                        else
5444                                printk(".");
5445                }
5446                printk("\n");
5447
5448                data  += linecount;
5449                count -= linecount;
5450        }
5451}       /* end of trace_block() */
5452
5453/* called when HDLC frame times out
5454 * update stats and do tx completion processing
5455 */
5456static void tx_timeout(struct timer_list *t)
5457{
5458        SLMP_INFO *info = from_timer(info, t, tx_timer);
5459        unsigned long flags;
5460
5461        if ( debug_level >= DEBUG_LEVEL_INFO )
5462                printk( "%s(%d):%s tx_timeout()\n",
5463                        __FILE__,__LINE__,info->device_name);
5464        if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5465                info->icount.txtimeout++;
5466        }
5467        spin_lock_irqsave(&info->lock,flags);
5468        info->tx_active = false;
5469        info->tx_count = info->tx_put = info->tx_get = 0;
5470
5471        spin_unlock_irqrestore(&info->lock,flags);
5472
5473#if SYNCLINK_GENERIC_HDLC
5474        if (info->netcount)
5475                hdlcdev_tx_done(info);
5476        else
5477#endif
5478                bh_transmit(info);
5479}
5480
5481/* called to periodically check the DSR/RI modem signal input status
5482 */
5483static void status_timeout(struct timer_list *t)
5484{
5485        u16 status = 0;
5486        SLMP_INFO *info = from_timer(info, t, status_timer);
5487        unsigned long flags;
5488        unsigned char delta;
5489
5490
5491        spin_lock_irqsave(&info->lock,flags);
5492        get_signals(info);
5493        spin_unlock_irqrestore(&info->lock,flags);
5494
5495        /* check for DSR/RI state change */
5496
5497        delta = info->old_signals ^ info->serial_signals;
5498        info->old_signals = info->serial_signals;
5499
5500        if (delta & SerialSignal_DSR)
5501                status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5502
5503        if (delta & SerialSignal_RI)
5504                status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5505
5506        if (delta & SerialSignal_DCD)
5507                status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5508
5509        if (delta & SerialSignal_CTS)
5510                status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5511
5512        if (status)
5513                isr_io_pin(info,status);
5514
5515        mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5516}
5517
5518
5519/* Register Access Routines -
5520 * All registers are memory mapped
5521 */
5522#define CALC_REGADDR() \
5523        unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5524        if (info->port_num > 1) \
5525                RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5526        if ( info->port_num & 1) { \
5527                if (Addr > 0x7f) \
5528                        RegAddr += 0x40;        /* DMA access */ \
5529                else if (Addr > 0x1f && Addr < 0x60) \
5530                        RegAddr += 0x20;        /* MSCI access */ \
5531        }
5532
5533
5534static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5535{
5536        CALC_REGADDR();
5537        return *RegAddr;
5538}
5539static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5540{
5541        CALC_REGADDR();
5542        *RegAddr = Value;
5543}
5544
5545static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5546{
5547        CALC_REGADDR();
5548        return *((u16 *)RegAddr);
5549}
5550
5551static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5552{
5553        CALC_REGADDR();
5554        *((u16 *)RegAddr) = Value;
5555}
5556
5557static unsigned char read_status_reg(SLMP_INFO * info)
5558{
5559        unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5560        return *RegAddr;
5561}
5562
5563static void write_control_reg(SLMP_INFO * info)
5564{
5565        unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5566        *RegAddr = info->port_array[0]->ctrlreg_value;
5567}
5568
5569
5570static int synclinkmp_init_one (struct pci_dev *dev,
5571                                          const struct pci_device_id *ent)
5572{
5573        if (pci_enable_device(dev)) {
5574                printk("error enabling pci device %p\n", dev);
5575                return -EIO;
5576        }
5577        return device_init( ++synclinkmp_adapter_count, dev );
5578}
5579
5580static void synclinkmp_remove_one (struct pci_dev *dev)
5581{
5582}
5583