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10#include <linux/acpi.h>
11#include <linux/delay.h>
12#include <linux/firmware.h>
13#include <linux/i2c.h>
14#include <linux/module.h>
15#include <linux/pci.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19
20#include <asm/unaligned.h>
21#include "ucsi.h"
22
23enum enum_fw_mode {
24 BOOT,
25 FW1,
26 FW2,
27 FW_INVALID,
28};
29
30#define CCGX_RAB_DEVICE_MODE 0x0000
31#define CCGX_RAB_INTR_REG 0x0006
32#define DEV_INT BIT(0)
33#define PORT0_INT BIT(1)
34#define PORT1_INT BIT(2)
35#define UCSI_READ_INT BIT(7)
36#define CCGX_RAB_JUMP_TO_BOOT 0x0007
37#define TO_BOOT 'J'
38#define TO_ALT_FW 'A'
39#define CCGX_RAB_RESET_REQ 0x0008
40#define RESET_SIG 'R'
41#define CMD_RESET_I2C 0x0
42#define CMD_RESET_DEV 0x1
43#define CCGX_RAB_ENTER_FLASHING 0x000A
44#define FLASH_ENTER_SIG 'P'
45#define CCGX_RAB_VALIDATE_FW 0x000B
46#define CCGX_RAB_FLASH_ROW_RW 0x000C
47#define FLASH_SIG 'F'
48#define FLASH_RD_CMD 0x0
49#define FLASH_WR_CMD 0x1
50#define FLASH_FWCT1_WR_CMD 0x2
51#define FLASH_FWCT2_WR_CMD 0x3
52#define FLASH_FWCT_SIG_WR_CMD 0x4
53#define CCGX_RAB_READ_ALL_VER 0x0010
54#define CCGX_RAB_READ_FW2_VER 0x0020
55#define CCGX_RAB_UCSI_CONTROL 0x0039
56#define CCGX_RAB_UCSI_CONTROL_START BIT(0)
57#define CCGX_RAB_UCSI_CONTROL_STOP BIT(1)
58#define CCGX_RAB_UCSI_DATA_BLOCK(offset) (0xf000 | ((offset) & 0xff))
59#define REG_FLASH_RW_MEM 0x0200
60#define DEV_REG_IDX CCGX_RAB_DEVICE_MODE
61#define CCGX_RAB_PDPORT_ENABLE 0x002C
62#define PDPORT_1 BIT(0)
63#define PDPORT_2 BIT(1)
64#define CCGX_RAB_RESPONSE 0x007E
65#define ASYNC_EVENT BIT(7)
66
67
68#define RESET_COMPLETE 0x80
69#define EVENT_INDEX RESET_COMPLETE
70#define PORT_CONNECT_DET 0x84
71#define PORT_DISCONNECT_DET 0x85
72#define ROLE_SWAP_COMPELETE 0x87
73
74
75#define CYACD_LINE_SIZE 527
76#define CCG4_ROW_SIZE 256
77#define FW1_METADATA_ROW 0x1FF
78#define FW2_METADATA_ROW 0x1FE
79#define FW_CFG_TABLE_SIG_SIZE 256
80
81static int secondary_fw_min_ver = 41;
82
83enum enum_flash_mode {
84 SECONDARY_BL,
85 PRIMARY,
86 SECONDARY,
87 FLASH_NOT_NEEDED,
88 FLASH_INVALID,
89};
90
91static const char * const ccg_fw_names[] = {
92 "ccg_boot.cyacd",
93 "ccg_primary.cyacd",
94 "ccg_secondary.cyacd"
95};
96
97struct ccg_dev_info {
98#define CCG_DEVINFO_FWMODE_SHIFT (0)
99#define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
100#define CCG_DEVINFO_PDPORTS_SHIFT (2)
101#define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
102 u8 mode;
103 u8 bl_mode;
104 __le16 silicon_id;
105 __le16 bl_last_row;
106} __packed;
107
108struct version_format {
109 __le16 build;
110 u8 patch;
111 u8 ver;
112#define CCG_VERSION_PATCH(x) ((x) << 16)
113#define CCG_VERSION(x) ((x) << 24)
114#define CCG_VERSION_MIN_SHIFT (0)
115#define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
116#define CCG_VERSION_MAJ_SHIFT (4)
117#define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
118} __packed;
119
120
121
122
123
124#define CCG_FW_BUILD_NVIDIA (('n' << 8) | 'v')
125#define CCG_OLD_FW_VERSION (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
126
127struct version_info {
128 struct version_format base;
129 struct version_format app;
130};
131
132struct fw_config_table {
133 u32 identity;
134 u16 table_size;
135 u8 fwct_version;
136 u8 is_key_change;
137 u8 guid[16];
138 struct version_format base;
139 struct version_format app;
140 u8 primary_fw_digest[32];
141 u32 key_exp_length;
142 u8 key_modulus[256];
143 u8 key_exp[4];
144};
145
146
147enum ccg_resp_code {
148 CMD_NO_RESP = 0x00,
149 CMD_SUCCESS = 0x02,
150 FLASH_DATA_AVAILABLE = 0x03,
151 CMD_INVALID = 0x05,
152 FLASH_UPDATE_FAIL = 0x07,
153 INVALID_FW = 0x08,
154 INVALID_ARG = 0x09,
155 CMD_NOT_SUPPORT = 0x0A,
156 TRANSACTION_FAIL = 0x0C,
157 PD_CMD_FAIL = 0x0D,
158 UNDEF_ERROR = 0x0F,
159 INVALID_RESP = 0x10,
160};
161
162#define CCG_EVENT_MAX (EVENT_INDEX + 43)
163
164struct ccg_cmd {
165 u16 reg;
166 u32 data;
167 int len;
168 u32 delay;
169};
170
171struct ccg_resp {
172 u8 code;
173 u8 length;
174};
175
176struct ucsi_ccg {
177 struct device *dev;
178 struct ucsi *ucsi;
179 struct i2c_client *client;
180
181 struct ccg_dev_info info;
182
183 struct version_info version[FW2 + 1];
184 u32 fw_version;
185
186 unsigned long flags;
187#define RESET_PENDING 0
188#define DEV_CMD_PENDING 1
189 struct ccg_resp dev_resp;
190 u8 cmd_resp;
191 int port_num;
192 int irq;
193 struct work_struct work;
194 struct mutex lock;
195
196
197 u16 fw_build;
198 struct work_struct pm_work;
199
200 struct completion complete;
201};
202
203static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
204{
205 struct i2c_client *client = uc->client;
206 const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
207 unsigned char buf[2];
208 struct i2c_msg msgs[] = {
209 {
210 .addr = client->addr,
211 .flags = 0x0,
212 .len = sizeof(buf),
213 .buf = buf,
214 },
215 {
216 .addr = client->addr,
217 .flags = I2C_M_RD,
218 .buf = data,
219 },
220 };
221 u32 rlen, rem_len = len, max_read_len = len;
222 int status;
223
224
225 if (quirks && quirks->max_read_len)
226 max_read_len = quirks->max_read_len;
227
228 pm_runtime_get_sync(uc->dev);
229 while (rem_len > 0) {
230 msgs[1].buf = &data[len - rem_len];
231 rlen = min_t(u16, rem_len, max_read_len);
232 msgs[1].len = rlen;
233 put_unaligned_le16(rab, buf);
234 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
235 if (status < 0) {
236 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
237 pm_runtime_put_sync(uc->dev);
238 return status;
239 }
240 rab += rlen;
241 rem_len -= rlen;
242 }
243
244 pm_runtime_put_sync(uc->dev);
245 return 0;
246}
247
248static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
249{
250 struct i2c_client *client = uc->client;
251 unsigned char *buf;
252 struct i2c_msg msgs[] = {
253 {
254 .addr = client->addr,
255 .flags = 0x0,
256 }
257 };
258 int status;
259
260 buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
261 if (!buf)
262 return -ENOMEM;
263
264 put_unaligned_le16(rab, buf);
265 memcpy(buf + sizeof(rab), data, len);
266
267 msgs[0].len = len + sizeof(rab);
268 msgs[0].buf = buf;
269
270 pm_runtime_get_sync(uc->dev);
271 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
272 if (status < 0) {
273 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
274 pm_runtime_put_sync(uc->dev);
275 kfree(buf);
276 return status;
277 }
278
279 pm_runtime_put_sync(uc->dev);
280 kfree(buf);
281 return 0;
282}
283
284static int ucsi_ccg_init(struct ucsi_ccg *uc)
285{
286 unsigned int count = 10;
287 u8 data;
288 int status;
289
290 data = CCGX_RAB_UCSI_CONTROL_STOP;
291 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
292 if (status < 0)
293 return status;
294
295 data = CCGX_RAB_UCSI_CONTROL_START;
296 status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
297 if (status < 0)
298 return status;
299
300
301
302
303
304 do {
305 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
306 if (status < 0)
307 return status;
308
309 if (!data)
310 return 0;
311
312 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
313 if (status < 0)
314 return status;
315
316 usleep_range(10000, 11000);
317 } while (--count);
318
319 return -ETIMEDOUT;
320}
321
322static int ucsi_ccg_read(struct ucsi *ucsi, unsigned int offset,
323 void *val, size_t val_len)
324{
325 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
326
327 return ccg_read(ucsi_get_drvdata(ucsi), reg, val, val_len);
328}
329
330static int ucsi_ccg_async_write(struct ucsi *ucsi, unsigned int offset,
331 const void *val, size_t val_len)
332{
333 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
334
335 return ccg_write(ucsi_get_drvdata(ucsi), reg, val, val_len);
336}
337
338static int ucsi_ccg_sync_write(struct ucsi *ucsi, unsigned int offset,
339 const void *val, size_t val_len)
340{
341 struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
342 int ret;
343
344 mutex_lock(&uc->lock);
345 pm_runtime_get_sync(uc->dev);
346 set_bit(DEV_CMD_PENDING, &uc->flags);
347
348 ret = ucsi_ccg_async_write(ucsi, offset, val, val_len);
349 if (ret)
350 goto err_clear_bit;
351
352 if (!wait_for_completion_timeout(&uc->complete, msecs_to_jiffies(5000)))
353 ret = -ETIMEDOUT;
354
355err_clear_bit:
356 clear_bit(DEV_CMD_PENDING, &uc->flags);
357 pm_runtime_put_sync(uc->dev);
358 mutex_unlock(&uc->lock);
359
360 return ret;
361}
362
363static const struct ucsi_operations ucsi_ccg_ops = {
364 .read = ucsi_ccg_read,
365 .sync_write = ucsi_ccg_sync_write,
366 .async_write = ucsi_ccg_async_write
367};
368
369static irqreturn_t ccg_irq_handler(int irq, void *data)
370{
371 u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
372 struct ucsi_ccg *uc = data;
373 u8 intr_reg;
374 u32 cci;
375 int ret;
376
377 ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
378 if (ret)
379 return ret;
380
381 ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
382 if (ret)
383 goto err_clear_irq;
384
385 if (UCSI_CCI_CONNECTOR(cci))
386 ucsi_connector_change(uc->ucsi, UCSI_CCI_CONNECTOR(cci));
387
388 if (test_bit(DEV_CMD_PENDING, &uc->flags) &&
389 cci & (UCSI_CCI_ACK_COMPLETE | UCSI_CCI_COMMAND_COMPLETE))
390 complete(&uc->complete);
391
392err_clear_irq:
393 ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
394
395 return IRQ_HANDLED;
396}
397
398static void ccg_pm_workaround_work(struct work_struct *pm_work)
399{
400 ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
401}
402
403static int get_fw_info(struct ucsi_ccg *uc)
404{
405 int err;
406
407 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
408 sizeof(uc->version));
409 if (err < 0)
410 return err;
411
412 uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
413 CCG_VERSION_PATCH(uc->version[FW2].app.patch);
414
415 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
416 sizeof(uc->info));
417 if (err < 0)
418 return err;
419
420 return 0;
421}
422
423static inline bool invalid_async_evt(int code)
424{
425 return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
426}
427
428static void ccg_process_response(struct ucsi_ccg *uc)
429{
430 struct device *dev = uc->dev;
431
432 if (uc->dev_resp.code & ASYNC_EVENT) {
433 if (uc->dev_resp.code == RESET_COMPLETE) {
434 if (test_bit(RESET_PENDING, &uc->flags))
435 uc->cmd_resp = uc->dev_resp.code;
436 get_fw_info(uc);
437 }
438 if (invalid_async_evt(uc->dev_resp.code))
439 dev_err(dev, "invalid async evt %d\n",
440 uc->dev_resp.code);
441 } else {
442 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
443 uc->cmd_resp = uc->dev_resp.code;
444 clear_bit(DEV_CMD_PENDING, &uc->flags);
445 } else {
446 dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
447 uc->dev_resp.code);
448 }
449 }
450}
451
452static int ccg_read_response(struct ucsi_ccg *uc)
453{
454 unsigned long target = jiffies + msecs_to_jiffies(1000);
455 struct device *dev = uc->dev;
456 u8 intval;
457 int status;
458
459
460 do {
461 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
462 sizeof(intval));
463 if (status < 0)
464 return status;
465
466 if (intval & DEV_INT)
467 break;
468 usleep_range(500, 600);
469 } while (time_is_after_jiffies(target));
470
471 if (time_is_before_jiffies(target)) {
472 dev_err(dev, "response timeout error\n");
473 return -ETIME;
474 }
475
476 status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
477 sizeof(uc->dev_resp));
478 if (status < 0)
479 return status;
480
481 status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
482 if (status < 0)
483 return status;
484
485 return 0;
486}
487
488
489static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
490{
491 struct device *dev = uc->dev;
492 int ret;
493
494 switch (cmd->reg & 0xF000) {
495 case DEV_REG_IDX:
496 set_bit(DEV_CMD_PENDING, &uc->flags);
497 break;
498 default:
499 dev_err(dev, "invalid cmd register\n");
500 break;
501 }
502
503 ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
504 if (ret < 0)
505 return ret;
506
507 msleep(cmd->delay);
508
509 ret = ccg_read_response(uc);
510 if (ret < 0) {
511 dev_err(dev, "response read error\n");
512 switch (cmd->reg & 0xF000) {
513 case DEV_REG_IDX:
514 clear_bit(DEV_CMD_PENDING, &uc->flags);
515 break;
516 default:
517 dev_err(dev, "invalid cmd register\n");
518 break;
519 }
520 return -EIO;
521 }
522 ccg_process_response(uc);
523
524 return uc->cmd_resp;
525}
526
527static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
528{
529 struct ccg_cmd cmd;
530 int ret;
531
532 cmd.reg = CCGX_RAB_ENTER_FLASHING;
533 cmd.data = FLASH_ENTER_SIG;
534 cmd.len = 1;
535 cmd.delay = 50;
536
537 mutex_lock(&uc->lock);
538
539 ret = ccg_send_command(uc, &cmd);
540
541 mutex_unlock(&uc->lock);
542
543 if (ret != CMD_SUCCESS) {
544 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
545 return ret;
546 }
547
548 return 0;
549}
550
551static int ccg_cmd_reset(struct ucsi_ccg *uc)
552{
553 struct ccg_cmd cmd;
554 u8 *p;
555 int ret;
556
557 p = (u8 *)&cmd.data;
558 cmd.reg = CCGX_RAB_RESET_REQ;
559 p[0] = RESET_SIG;
560 p[1] = CMD_RESET_DEV;
561 cmd.len = 2;
562 cmd.delay = 5000;
563
564 mutex_lock(&uc->lock);
565
566 set_bit(RESET_PENDING, &uc->flags);
567
568 ret = ccg_send_command(uc, &cmd);
569 if (ret != RESET_COMPLETE)
570 goto err_clear_flag;
571
572 ret = 0;
573
574err_clear_flag:
575 clear_bit(RESET_PENDING, &uc->flags);
576
577 mutex_unlock(&uc->lock);
578
579 return ret;
580}
581
582static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
583{
584 struct ccg_cmd cmd;
585 int ret;
586
587 cmd.reg = CCGX_RAB_PDPORT_ENABLE;
588 if (enable)
589 cmd.data = (uc->port_num == 1) ?
590 PDPORT_1 : (PDPORT_1 | PDPORT_2);
591 else
592 cmd.data = 0x0;
593 cmd.len = 1;
594 cmd.delay = 10;
595
596 mutex_lock(&uc->lock);
597
598 ret = ccg_send_command(uc, &cmd);
599
600 mutex_unlock(&uc->lock);
601
602 if (ret != CMD_SUCCESS) {
603 dev_err(uc->dev, "port control failed ret=%d\n", ret);
604 return ret;
605 }
606 return 0;
607}
608
609static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
610{
611 struct ccg_cmd cmd;
612 int ret;
613
614 cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
615
616 if (bl_mode)
617 cmd.data = TO_BOOT;
618 else
619 cmd.data = TO_ALT_FW;
620
621 cmd.len = 1;
622 cmd.delay = 100;
623
624 mutex_lock(&uc->lock);
625
626 set_bit(RESET_PENDING, &uc->flags);
627
628 ret = ccg_send_command(uc, &cmd);
629 if (ret != RESET_COMPLETE)
630 goto err_clear_flag;
631
632 ret = 0;
633
634err_clear_flag:
635 clear_bit(RESET_PENDING, &uc->flags);
636
637 mutex_unlock(&uc->lock);
638
639 return ret;
640}
641
642static int
643ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
644 const void *data, u8 fcmd)
645{
646 struct i2c_client *client = uc->client;
647 struct ccg_cmd cmd;
648 u8 buf[CCG4_ROW_SIZE + 2];
649 u8 *p;
650 int ret;
651
652
653 put_unaligned_le16(REG_FLASH_RW_MEM, buf);
654
655 memcpy(buf + 2, data, CCG4_ROW_SIZE);
656
657 mutex_lock(&uc->lock);
658
659 ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
660 if (ret != CCG4_ROW_SIZE + 2) {
661 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
662 mutex_unlock(&uc->lock);
663 return ret < 0 ? ret : -EIO;
664 }
665
666
667
668 p = (u8 *)&cmd.data;
669 cmd.reg = CCGX_RAB_FLASH_ROW_RW;
670 p[0] = FLASH_SIG;
671 p[1] = fcmd;
672 put_unaligned_le16(row, &p[2]);
673 cmd.len = 4;
674 cmd.delay = 50;
675 if (fcmd == FLASH_FWCT_SIG_WR_CMD)
676 cmd.delay += 400;
677 if (row == 510)
678 cmd.delay += 220;
679 ret = ccg_send_command(uc, &cmd);
680
681 mutex_unlock(&uc->lock);
682
683 if (ret != CMD_SUCCESS) {
684 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
685 return ret;
686 }
687
688 return 0;
689}
690
691static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
692{
693 struct ccg_cmd cmd;
694 int ret;
695
696 cmd.reg = CCGX_RAB_VALIDATE_FW;
697 cmd.data = fwid;
698 cmd.len = 1;
699 cmd.delay = 500;
700
701 mutex_lock(&uc->lock);
702
703 ret = ccg_send_command(uc, &cmd);
704
705 mutex_unlock(&uc->lock);
706
707 if (ret != CMD_SUCCESS)
708 return ret;
709
710 return 0;
711}
712
713static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
714 struct version_format *app,
715 struct fw_config_table *fw_cfg)
716{
717 struct device *dev = uc->dev;
718
719
720 if (le16_to_cpu(app->build) != uc->fw_build) {
721 dev_info(dev, "current fw is not from supported vendor\n");
722 return false;
723 }
724
725
726 if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
727 dev_info(dev, "new fw is not from supported vendor\n");
728 return false;
729 }
730 return true;
731}
732
733static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
734 struct version_format *app)
735{
736 const struct firmware *fw = NULL;
737 struct device *dev = uc->dev;
738 struct fw_config_table fw_cfg;
739 u32 cur_version, new_version;
740 bool is_later = false;
741
742 if (request_firmware(&fw, fw_name, dev) != 0) {
743 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
744 return false;
745 }
746
747
748
749
750
751 if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
752 goto out_release_firmware;
753
754 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
755 sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
756
757 if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
758 dev_info(dev, "not a signed image\n");
759 goto out_release_firmware;
760 }
761
762
763 cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
764 CCG_VERSION(app->ver);
765
766 new_version = le16_to_cpu(fw_cfg.app.build) |
767 CCG_VERSION_PATCH(fw_cfg.app.patch) |
768 CCG_VERSION(fw_cfg.app.ver);
769
770 if (!ccg_check_vendor_version(uc, app, &fw_cfg))
771 goto out_release_firmware;
772
773 if (new_version > cur_version)
774 is_later = true;
775
776out_release_firmware:
777 release_firmware(fw);
778 return is_later;
779}
780
781static int ccg_fw_update_needed(struct ucsi_ccg *uc,
782 enum enum_flash_mode *mode)
783{
784 struct device *dev = uc->dev;
785 int err;
786 struct version_info version[3];
787
788 err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
789 sizeof(uc->info));
790 if (err) {
791 dev_err(dev, "read device mode failed\n");
792 return err;
793 }
794
795 err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
796 sizeof(version));
797 if (err) {
798 dev_err(dev, "read device mode failed\n");
799 return err;
800 }
801
802 if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
803 sizeof(struct version_info)) == 0) {
804 dev_info(dev, "secondary fw is not flashed\n");
805 *mode = SECONDARY_BL;
806 } else if (le16_to_cpu(version[FW1].base.build) <
807 secondary_fw_min_ver) {
808 dev_info(dev, "secondary fw version is too low (< %d)\n",
809 secondary_fw_min_ver);
810 *mode = SECONDARY;
811 } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
812 sizeof(struct version_info)) == 0) {
813 dev_info(dev, "primary fw is not flashed\n");
814 *mode = PRIMARY;
815 } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
816 &version[FW2].app)) {
817 dev_info(dev, "found primary fw with later version\n");
818 *mode = PRIMARY;
819 } else {
820 dev_info(dev, "secondary and primary fw are the latest\n");
821 *mode = FLASH_NOT_NEEDED;
822 }
823 return 0;
824}
825
826static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
827{
828 struct device *dev = uc->dev;
829 const struct firmware *fw = NULL;
830 const char *p, *s;
831 const char *eof;
832 int err, row, len, line_sz, line_cnt = 0;
833 unsigned long start_time = jiffies;
834 struct fw_config_table fw_cfg;
835 u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
836 u8 *wr_buf;
837
838 err = request_firmware(&fw, ccg_fw_names[mode], dev);
839 if (err) {
840 dev_err(dev, "request %s failed err=%d\n",
841 ccg_fw_names[mode], err);
842 return err;
843 }
844
845 if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
846 CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
847 err = ccg_cmd_port_control(uc, false);
848 if (err < 0)
849 goto release_fw;
850 err = ccg_cmd_jump_boot_mode(uc, 0);
851 if (err < 0)
852 goto release_fw;
853 }
854
855 eof = fw->data + fw->size;
856
857
858
859
860
861 if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
862 goto not_signed_fw;
863
864 memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
865 sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
866
867 if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
868 dev_info(dev, "not a signed image\n");
869 goto not_signed_fw;
870 }
871 eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
872
873 memcpy((uint8_t *)&fw_cfg_sig,
874 fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
875
876
877 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
878 FLASH_FWCT1_WR_CMD);
879 if (err)
880 goto release_fw;
881
882 err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
883 FLASH_FWCT2_WR_CMD);
884 if (err)
885 goto release_fw;
886
887 err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
888 FLASH_FWCT_SIG_WR_CMD);
889 if (err)
890 goto release_fw;
891
892not_signed_fw:
893 wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
894 if (!wr_buf) {
895 err = -ENOMEM;
896 goto release_fw;
897 }
898
899 err = ccg_cmd_enter_flashing(uc);
900 if (err)
901 goto release_mem;
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919 p = strnchr(fw->data, fw->size, ':');
920 while (p < eof) {
921 s = strnchr(p + 1, eof - p - 1, ':');
922
923 if (!s)
924 s = eof;
925
926 line_sz = s - p;
927
928 if (line_sz != CYACD_LINE_SIZE) {
929 dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
930 err = -EINVAL;
931 goto release_mem;
932 }
933
934 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
935 err = -EINVAL;
936 goto release_mem;
937 }
938
939 row = get_unaligned_be16(wr_buf);
940 len = get_unaligned_be16(&wr_buf[2]);
941
942 if (len != CCG4_ROW_SIZE) {
943 err = -EINVAL;
944 goto release_mem;
945 }
946
947 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
948 FLASH_WR_CMD);
949 if (err)
950 goto release_mem;
951
952 line_cnt++;
953 p = s;
954 }
955
956 dev_info(dev, "total %d row flashed. time: %dms\n",
957 line_cnt, jiffies_to_msecs(jiffies - start_time));
958
959 err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 : FW1);
960 if (err)
961 dev_err(dev, "%s validation failed err=%d\n",
962 (mode == PRIMARY) ? "FW2" : "FW1", err);
963 else
964 dev_info(dev, "%s validated\n",
965 (mode == PRIMARY) ? "FW2" : "FW1");
966
967 err = ccg_cmd_port_control(uc, false);
968 if (err < 0)
969 goto release_mem;
970
971 err = ccg_cmd_reset(uc);
972 if (err < 0)
973 goto release_mem;
974
975 err = ccg_cmd_port_control(uc, true);
976 if (err < 0)
977 goto release_mem;
978
979release_mem:
980 kfree(wr_buf);
981
982release_fw:
983 release_firmware(fw);
984 return err;
985}
986
987
988
989
990
991
992
993static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
994{
995 int err = 0;
996
997 while (flash_mode != FLASH_NOT_NEEDED) {
998 err = do_flash(uc, flash_mode);
999 if (err < 0)
1000 return err;
1001 err = ccg_fw_update_needed(uc, &flash_mode);
1002 if (err < 0)
1003 return err;
1004 }
1005 dev_info(uc->dev, "CCG FW update successful\n");
1006
1007 return err;
1008}
1009
1010static int ccg_restart(struct ucsi_ccg *uc)
1011{
1012 struct device *dev = uc->dev;
1013 int status;
1014
1015 status = ucsi_ccg_init(uc);
1016 if (status < 0) {
1017 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
1018 return status;
1019 }
1020
1021 status = request_threaded_irq(uc->irq, NULL, ccg_irq_handler,
1022 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1023 dev_name(dev), uc);
1024 if (status < 0) {
1025 dev_err(dev, "request_threaded_irq failed - %d\n", status);
1026 return status;
1027 }
1028
1029 status = ucsi_register(uc->ucsi);
1030 if (status) {
1031 dev_err(uc->dev, "failed to register the interface\n");
1032 return status;
1033 }
1034
1035 return 0;
1036}
1037
1038static void ccg_update_firmware(struct work_struct *work)
1039{
1040 struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1041 enum enum_flash_mode flash_mode;
1042 int status;
1043
1044 status = ccg_fw_update_needed(uc, &flash_mode);
1045 if (status < 0)
1046 return;
1047
1048 if (flash_mode != FLASH_NOT_NEEDED) {
1049 ucsi_unregister(uc->ucsi);
1050 free_irq(uc->irq, uc);
1051
1052 ccg_fw_update(uc, flash_mode);
1053 ccg_restart(uc);
1054 }
1055}
1056
1057static ssize_t do_flash_store(struct device *dev,
1058 struct device_attribute *attr,
1059 const char *buf, size_t n)
1060{
1061 struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1062 bool flash;
1063
1064 if (kstrtobool(buf, &flash))
1065 return -EINVAL;
1066
1067 if (!flash)
1068 return n;
1069
1070 if (uc->fw_build == 0x0) {
1071 dev_err(dev, "fail to flash FW due to missing FW build info\n");
1072 return -EINVAL;
1073 }
1074
1075 schedule_work(&uc->work);
1076 return n;
1077}
1078
1079static DEVICE_ATTR_WO(do_flash);
1080
1081static struct attribute *ucsi_ccg_attrs[] = {
1082 &dev_attr_do_flash.attr,
1083 NULL,
1084};
1085ATTRIBUTE_GROUPS(ucsi_ccg);
1086
1087static int ucsi_ccg_probe(struct i2c_client *client,
1088 const struct i2c_device_id *id)
1089{
1090 struct device *dev = &client->dev;
1091 struct ucsi_ccg *uc;
1092 int status;
1093
1094 uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1095 if (!uc)
1096 return -ENOMEM;
1097
1098 uc->dev = dev;
1099 uc->client = client;
1100 mutex_init(&uc->lock);
1101 init_completion(&uc->complete);
1102 INIT_WORK(&uc->work, ccg_update_firmware);
1103 INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1104
1105
1106 status = device_property_read_u16(dev, "ccgx,firmware-build",
1107 &uc->fw_build);
1108 if (status)
1109 dev_err(uc->dev, "failed to get FW build information\n");
1110
1111
1112 status = ucsi_ccg_init(uc);
1113 if (status < 0) {
1114 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1115 return status;
1116 }
1117
1118 status = get_fw_info(uc);
1119 if (status < 0) {
1120 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1121 return status;
1122 }
1123
1124 uc->port_num = 1;
1125
1126 if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1127 uc->port_num++;
1128
1129 uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1130 if (IS_ERR(uc->ucsi))
1131 return PTR_ERR(uc->ucsi);
1132
1133 ucsi_set_drvdata(uc->ucsi, uc);
1134
1135 status = request_threaded_irq(client->irq, NULL, ccg_irq_handler,
1136 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1137 dev_name(dev), uc);
1138 if (status < 0) {
1139 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1140 goto out_ucsi_destroy;
1141 }
1142
1143 uc->irq = client->irq;
1144
1145 status = ucsi_register(uc->ucsi);
1146 if (status)
1147 goto out_free_irq;
1148
1149 i2c_set_clientdata(client, uc);
1150
1151 pm_runtime_set_active(uc->dev);
1152 pm_runtime_enable(uc->dev);
1153 pm_runtime_use_autosuspend(uc->dev);
1154 pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1155 pm_runtime_idle(uc->dev);
1156
1157 return 0;
1158
1159out_free_irq:
1160 free_irq(uc->irq, uc);
1161out_ucsi_destroy:
1162 ucsi_destroy(uc->ucsi);
1163
1164 return status;
1165}
1166
1167static int ucsi_ccg_remove(struct i2c_client *client)
1168{
1169 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1170
1171 cancel_work_sync(&uc->pm_work);
1172 cancel_work_sync(&uc->work);
1173 pm_runtime_disable(uc->dev);
1174 ucsi_unregister(uc->ucsi);
1175 ucsi_destroy(uc->ucsi);
1176 free_irq(uc->irq, uc);
1177
1178 return 0;
1179}
1180
1181static const struct i2c_device_id ucsi_ccg_device_id[] = {
1182 {"ccgx-ucsi", 0},
1183 {}
1184};
1185MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
1186
1187static int ucsi_ccg_resume(struct device *dev)
1188{
1189 struct i2c_client *client = to_i2c_client(dev);
1190 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1191
1192 return ucsi_resume(uc->ucsi);
1193}
1194
1195static int ucsi_ccg_runtime_suspend(struct device *dev)
1196{
1197 return 0;
1198}
1199
1200static int ucsi_ccg_runtime_resume(struct device *dev)
1201{
1202 struct i2c_client *client = to_i2c_client(dev);
1203 struct ucsi_ccg *uc = i2c_get_clientdata(client);
1204
1205
1206
1207
1208
1209
1210 if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1211 uc->fw_version <= CCG_OLD_FW_VERSION)
1212 schedule_work(&uc->pm_work);
1213
1214 return 0;
1215}
1216
1217static const struct dev_pm_ops ucsi_ccg_pm = {
1218 .resume = ucsi_ccg_resume,
1219 .runtime_suspend = ucsi_ccg_runtime_suspend,
1220 .runtime_resume = ucsi_ccg_runtime_resume,
1221};
1222
1223static struct i2c_driver ucsi_ccg_driver = {
1224 .driver = {
1225 .name = "ucsi_ccg",
1226 .pm = &ucsi_ccg_pm,
1227 .dev_groups = ucsi_ccg_groups,
1228 },
1229 .probe = ucsi_ccg_probe,
1230 .remove = ucsi_ccg_remove,
1231 .id_table = ucsi_ccg_device_id,
1232};
1233
1234module_i2c_driver(ucsi_ccg_driver);
1235
1236MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1237MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1238MODULE_LICENSE("GPL v2");
1239
