LXR linux/drivers/video/backlight/ili922x.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * (C) Copyright 2008
   4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
   5 *
   6 * This driver implements a lcd device for the ILITEK 922x display
   7 * controller. The interface to the display is SPI and the display's
   8 * memory is cyclically updated over the RGB interface.
   9 */
  10
  11#include <linux/fb.h>
  12#include <linux/delay.h>
  13#include <linux/errno.h>
  14#include <linux/init.h>
  15#include <linux/kernel.h>
  16#include <linux/lcd.h>
  17#include <linux/module.h>
  18#include <linux/of.h>
  19#include <linux/slab.h>
  20#include <linux/spi/spi.h>
  21#include <linux/string.h>
  22
  23/* Register offset, see manual section 8.2 */
  24#define REG_START_OSCILLATION                   0x00
  25#define REG_DRIVER_CODE_READ                    0x00
  26#define REG_DRIVER_OUTPUT_CONTROL               0x01
  27#define REG_LCD_AC_DRIVEING_CONTROL             0x02
  28#define REG_ENTRY_MODE                          0x03
  29#define REG_COMPARE_1                           0x04
  30#define REG_COMPARE_2                           0x05
  31#define REG_DISPLAY_CONTROL_1                   0x07
  32#define REG_DISPLAY_CONTROL_2                   0x08
  33#define REG_DISPLAY_CONTROL_3                   0x09
  34#define REG_FRAME_CYCLE_CONTROL                 0x0B
  35#define REG_EXT_INTF_CONTROL                    0x0C
  36#define REG_POWER_CONTROL_1                     0x10
  37#define REG_POWER_CONTROL_2                     0x11
  38#define REG_POWER_CONTROL_3                     0x12
  39#define REG_POWER_CONTROL_4                     0x13
  40#define REG_RAM_ADDRESS_SET                     0x21
  41#define REG_WRITE_DATA_TO_GRAM                  0x22
  42#define REG_RAM_WRITE_MASK1                     0x23
  43#define REG_RAM_WRITE_MASK2                     0x24
  44#define REG_GAMMA_CONTROL_1                     0x30
  45#define REG_GAMMA_CONTROL_2                     0x31
  46#define REG_GAMMA_CONTROL_3                     0x32
  47#define REG_GAMMA_CONTROL_4                     0x33
  48#define REG_GAMMA_CONTROL_5                     0x34
  49#define REG_GAMMA_CONTROL_6                     0x35
  50#define REG_GAMMA_CONTROL_7                     0x36
  51#define REG_GAMMA_CONTROL_8                     0x37
  52#define REG_GAMMA_CONTROL_9                     0x38
  53#define REG_GAMMA_CONTROL_10                    0x39
  54#define REG_GATE_SCAN_CONTROL                   0x40
  55#define REG_VERT_SCROLL_CONTROL                 0x41
  56#define REG_FIRST_SCREEN_DRIVE_POS              0x42
  57#define REG_SECOND_SCREEN_DRIVE_POS             0x43
  58#define REG_RAM_ADDR_POS_H                      0x44
  59#define REG_RAM_ADDR_POS_V                      0x45
  60#define REG_OSCILLATOR_CONTROL                  0x4F
  61#define REG_GPIO                                0x60
  62#define REG_OTP_VCM_PROGRAMMING                 0x61
  63#define REG_OTP_VCM_STATUS_ENABLE               0x62
  64#define REG_OTP_PROGRAMMING_ID_KEY              0x65
  65
  66/*
  67 * maximum frequency for register access
  68 * (not for the GRAM access)
  69 */
  70#define ILITEK_MAX_FREQ_REG     4000000
  71
  72/*
  73 * Device ID as found in the datasheet (supports 9221 and 9222)
  74 */
  75#define ILITEK_DEVICE_ID        0x9220
  76#define ILITEK_DEVICE_ID_MASK   0xFFF0
  77
  78/* Last two bits in the START BYTE */
  79#define START_RS_INDEX          0
  80#define START_RS_REG            1
  81#define START_RW_WRITE          0
  82#define START_RW_READ           1
  83
  84/**
  85 * START_BYTE(id, rs, rw)
  86 *
  87 * Set the start byte according to the required operation.
  88 * The start byte is defined as:
  89 *   ----------------------------------
  90 *  | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
  91 *   ----------------------------------
  92 * @id: display's id as set by the manufacturer
  93 * @rs: operation type bit, one of:
  94 *        - START_RS_INDEX      set the index register
  95 *        - START_RS_REG        write/read registers/GRAM
  96 * @rw: read/write operation
  97 *       - START_RW_WRITE       write
  98 *       - START_RW_READ        read
  99 */
 100#define START_BYTE(id, rs, rw)  \
 101        (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
 102
 103/**
 104 * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
 105 *      for the SPI transfer. According to the datasheet, the controller
 106 *      accept higher frequency for the GRAM transfer, but it requires
 107 *      lower frequency when the registers are read/written.
 108 *      The macro sets the frequency in the spi_transfer structure if
 109 *      the frequency exceeds the maximum value.
 110 */
 111#define CHECK_FREQ_REG(s, x)    \
 112        do {                    \
 113                if (s->max_speed_hz > ILITEK_MAX_FREQ_REG)      \
 114                        ((struct spi_transfer *)x)->speed_hz =  \
 115                                        ILITEK_MAX_FREQ_REG;    \
 116        } while (0)
 117
 118#define CMD_BUFSIZE             16
 119
 120#define POWER_IS_ON(pwr)        ((pwr) <= FB_BLANK_NORMAL)
 121
 122#define set_tx_byte(b)          (tx_invert ? ~(b) : b)
 123
 124/**
 125 * ili922x_id - id as set by manufacturer
 126 */
 127static int ili922x_id = 1;
 128module_param(ili922x_id, int, 0);
 129
 130static int tx_invert;
 131module_param(tx_invert, int, 0);
 132
 133/**
 134 * driver's private structure
 135 */
 136struct ili922x {
 137        struct spi_device *spi;
 138        struct lcd_device *ld;
 139        int power;
 140};
 141
 142/**
 143 * ili922x_read_status - read status register from display
 144 * @spi: spi device
 145 * @rs:  output value
 146 */
 147static int ili922x_read_status(struct spi_device *spi, u16 *rs)
 148{
 149        struct spi_message msg;
 150        struct spi_transfer xfer;
 151        unsigned char tbuf[CMD_BUFSIZE];
 152        unsigned char rbuf[CMD_BUFSIZE];
 153        int ret, i;
 154
 155        memset(&xfer, 0, sizeof(struct spi_transfer));
 156        spi_message_init(&msg);
 157        xfer.tx_buf = tbuf;
 158        xfer.rx_buf = rbuf;
 159        xfer.cs_change = 1;
 160        CHECK_FREQ_REG(spi, &xfer);
 161
 162        tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
 163                                         START_RW_READ));
 164        /*
 165         * we need 4-byte xfer here due to invalid dummy byte
 166         * received after start byte
 167         */
 168        for (i = 1; i < 4; i++)
 169                tbuf[i] = set_tx_byte(0);       /* dummy */
 170
 171        xfer.bits_per_word = 8;
 172        xfer.len = 4;
 173        spi_message_add_tail(&xfer, &msg);
 174        ret = spi_sync(spi, &msg);
 175        if (ret < 0) {
 176                dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
 177                return ret;
 178        }
 179
 180        *rs = (rbuf[2] << 8) + rbuf[3];
 181        return 0;
 182}
 183
 184/**
 185 * ili922x_read - read register from display
 186 * @spi: spi device
 187 * @reg: offset of the register to be read
 188 * @rx:  output value
 189 */
 190static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
 191{
 192        struct spi_message msg;
 193        struct spi_transfer xfer_regindex, xfer_regvalue;
 194        unsigned char tbuf[CMD_BUFSIZE];
 195        unsigned char rbuf[CMD_BUFSIZE];
 196        int ret, len = 0, send_bytes;
 197
 198        memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
 199        memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
 200        spi_message_init(&msg);
 201        xfer_regindex.tx_buf = tbuf;
 202        xfer_regindex.rx_buf = rbuf;
 203        xfer_regindex.cs_change = 1;
 204        CHECK_FREQ_REG(spi, &xfer_regindex);
 205
 206        tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
 207                                         START_RW_WRITE));
 208        tbuf[1] = set_tx_byte(0);
 209        tbuf[2] = set_tx_byte(reg);
 210        xfer_regindex.bits_per_word = 8;
 211        len = xfer_regindex.len = 3;
 212        spi_message_add_tail(&xfer_regindex, &msg);
 213
 214        send_bytes = len;
 215
 216        tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
 217                                             START_RW_READ));
 218        tbuf[len++] = set_tx_byte(0);
 219        tbuf[len] = set_tx_byte(0);
 220
 221        xfer_regvalue.cs_change = 1;
 222        xfer_regvalue.len = 3;
 223        xfer_regvalue.tx_buf = &tbuf[send_bytes];
 224        xfer_regvalue.rx_buf = &rbuf[send_bytes];
 225        CHECK_FREQ_REG(spi, &xfer_regvalue);
 226
 227        spi_message_add_tail(&xfer_regvalue, &msg);
 228        ret = spi_sync(spi, &msg);
 229        if (ret < 0) {
 230                dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
 231                return ret;
 232        }
 233
 234        *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
 235        return 0;
 236}
 237
 238/**
 239 * ili922x_write - write a controller register
 240 * @spi: struct spi_device *
 241 * @reg: offset of the register to be written
 242 * @value: value to be written
 243 */
 244static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
 245{
 246        struct spi_message msg;
 247        struct spi_transfer xfer_regindex, xfer_regvalue;
 248        unsigned char tbuf[CMD_BUFSIZE];
 249        unsigned char rbuf[CMD_BUFSIZE];
 250        int ret;
 251
 252        memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
 253        memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
 254
 255        spi_message_init(&msg);
 256        xfer_regindex.tx_buf = tbuf;
 257        xfer_regindex.rx_buf = rbuf;
 258        xfer_regindex.cs_change = 1;
 259        CHECK_FREQ_REG(spi, &xfer_regindex);
 260
 261        tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
 262                                         START_RW_WRITE));
 263        tbuf[1] = set_tx_byte(0);
 264        tbuf[2] = set_tx_byte(reg);
 265        xfer_regindex.bits_per_word = 8;
 266        xfer_regindex.len = 3;
 267        spi_message_add_tail(&xfer_regindex, &msg);
 268
 269        ret = spi_sync(spi, &msg);
 270
 271        spi_message_init(&msg);
 272        tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
 273                                         START_RW_WRITE));
 274        tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
 275        tbuf[2] = set_tx_byte(value & 0x00FF);
 276
 277        xfer_regvalue.cs_change = 1;
 278        xfer_regvalue.len = 3;
 279        xfer_regvalue.tx_buf = tbuf;
 280        xfer_regvalue.rx_buf = rbuf;
 281        CHECK_FREQ_REG(spi, &xfer_regvalue);
 282
 283        spi_message_add_tail(&xfer_regvalue, &msg);
 284
 285        ret = spi_sync(spi, &msg);
 286        if (ret < 0) {
 287                dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
 288                return ret;
 289        }
 290        return 0;
 291}
 292
 293#ifdef DEBUG
 294/**
 295 * ili922x_reg_dump - dump all registers
 296 */
 297static void ili922x_reg_dump(struct spi_device *spi)
 298{
 299        u8 reg;
 300        u16 rx;
 301
 302        dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
 303        for (reg = REG_START_OSCILLATION;
 304             reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
 305                ili922x_read(spi, reg, &rx);
 306                dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
 307        }
 308}
 309#else
 310static inline void ili922x_reg_dump(struct spi_device *spi) {}
 311#endif
 312
 313/**
 314 * set_write_to_gram_reg - initialize the display to write the GRAM
 315 * @spi: spi device
 316 */
 317static void set_write_to_gram_reg(struct spi_device *spi)
 318{
 319        struct spi_message msg;
 320        struct spi_transfer xfer;
 321        unsigned char tbuf[CMD_BUFSIZE];
 322
 323        memset(&xfer, 0, sizeof(struct spi_transfer));
 324
 325        spi_message_init(&msg);
 326        xfer.tx_buf = tbuf;
 327        xfer.rx_buf = NULL;
 328        xfer.cs_change = 1;
 329
 330        tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
 331        tbuf[1] = 0;
 332        tbuf[2] = REG_WRITE_DATA_TO_GRAM;
 333
 334        xfer.bits_per_word = 8;
 335        xfer.len = 3;
 336        spi_message_add_tail(&xfer, &msg);
 337        spi_sync(spi, &msg);
 338}
 339
 340/**
 341 * ili922x_poweron - turn the display on
 342 * @spi: spi device
 343 *
 344 * The sequence to turn on the display is taken from
 345 * the datasheet and/or the example code provided by the
 346 * manufacturer.
 347 */
 348static int ili922x_poweron(struct spi_device *spi)
 349{
 350        int ret;
 351
 352        /* Power on */
 353        ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
 354        usleep_range(10000, 10500);
 355        ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
 356        ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
 357        msleep(40);
 358        ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
 359        msleep(40);
 360        /* register 0x56 is not documented in the datasheet */
 361        ret += ili922x_write(spi, 0x56, 0x080F);
 362        ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
 363        usleep_range(10000, 10500);
 364        ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
 365        ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
 366        msleep(40);
 367        ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
 368        msleep(40);
 369
 370        return ret;
 371}
 372
 373/**
 374 * ili922x_poweroff - turn the display off
 375 * @spi: spi device
 376 */
 377static int ili922x_poweroff(struct spi_device *spi)
 378{
 379        int ret;
 380
 381        /* Power off */
 382        ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
 383        usleep_range(10000, 10500);
 384        ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
 385        ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
 386        msleep(40);
 387        ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
 388        msleep(40);
 389
 390        return ret;
 391}
 392
 393/**
 394 * ili922x_display_init - initialize the display by setting
 395 *                        the configuration registers
 396 * @spi: spi device
 397 */
 398static void ili922x_display_init(struct spi_device *spi)
 399{
 400        ili922x_write(spi, REG_START_OSCILLATION, 1);
 401        usleep_range(10000, 10500);
 402        ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
 403        ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
 404        ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
 405        ili922x_write(spi, REG_COMPARE_1, 0x0000);
 406        ili922x_write(spi, REG_COMPARE_2, 0x0000);
 407        ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
 408        ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
 409        ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
 410        ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
 411
 412        /* Set RGB interface */
 413        ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
 414
 415        ili922x_poweron(spi);
 416
 417        ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
 418        ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
 419        ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
 420        ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
 421        ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
 422        ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
 423        ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
 424        ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
 425        ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
 426        ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
 427        ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
 428        ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
 429        ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
 430        ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
 431        ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
 432        ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
 433        ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
 434        ili922x_reg_dump(spi);
 435        set_write_to_gram_reg(spi);
 436}
 437
 438static int ili922x_lcd_power(struct ili922x *lcd, int power)
 439{
 440        int ret = 0;
 441
 442        if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
 443                ret = ili922x_poweron(lcd->spi);
 444        else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
 445                ret = ili922x_poweroff(lcd->spi);
 446
 447        if (!ret)
 448                lcd->power = power;
 449
 450        return ret;
 451}
 452
 453static int ili922x_set_power(struct lcd_device *ld, int power)
 454{
 455        struct ili922x *ili = lcd_get_data(ld);
 456
 457        return ili922x_lcd_power(ili, power);
 458}
 459
 460static int ili922x_get_power(struct lcd_device *ld)
 461{
 462        struct ili922x *ili = lcd_get_data(ld);
 463
 464        return ili->power;
 465}
 466
 467static struct lcd_ops ili922x_ops = {
 468        .get_power = ili922x_get_power,
 469        .set_power = ili922x_set_power,
 470};
 471
 472static int ili922x_probe(struct spi_device *spi)
 473{
 474        struct ili922x *ili;
 475        struct lcd_device *lcd;
 476        int ret;
 477        u16 reg = 0;
 478
 479        ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
 480        if (!ili)
 481                return -ENOMEM;
 482
 483        ili->spi = spi;
 484        spi_set_drvdata(spi, ili);
 485
 486        /* check if the device is connected */
 487        ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
 488        if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
 489                dev_err(&spi->dev,
 490                        "no LCD found: Chip ID 0x%x, ret %d\n",
 491                        reg, ret);
 492                return -ENODEV;
 493        }
 494
 495        dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
 496                 reg, spi->max_speed_hz, spi->mode);
 497
 498        ret = ili922x_read_status(spi, &reg);
 499        if (ret) {
 500                dev_err(&spi->dev, "reading RS failed...\n");
 501                return ret;
 502        }
 503
 504        dev_dbg(&spi->dev, "status: 0x%x\n", reg);
 505
 506        ili922x_display_init(spi);
 507
 508        ili->power = FB_BLANK_POWERDOWN;
 509
 510        lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
 511                                        &ili922x_ops);
 512        if (IS_ERR(lcd)) {
 513                dev_err(&spi->dev, "cannot register LCD\n");
 514                return PTR_ERR(lcd);
 515        }
 516
 517        ili->ld = lcd;
 518        spi_set_drvdata(spi, ili);
 519
 520        ili922x_lcd_power(ili, FB_BLANK_UNBLANK);
 521
 522        return 0;
 523}
 524
 525static int ili922x_remove(struct spi_device *spi)
 526{
 527        ili922x_poweroff(spi);
 528        return 0;
 529}
 530
 531static struct spi_driver ili922x_driver = {
 532        .driver = {
 533                .name = "ili922x",
 534        },
 535        .probe = ili922x_probe,
 536        .remove = ili922x_remove,
 537};
 538
 539module_spi_driver(ili922x_driver);
 540
 541MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
 542MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
 543MODULE_LICENSE("GPL");
 544MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
 545MODULE_PARM_DESC(tx_invert, "invert bytes before sending");
 546