LXR linux/drivers/watchdog/lantiq

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *
   4 *  Copyright (C) 2010 John Crispin <john@phrozen.org>
   5 *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
   6 *  Based on EP93xx wdt driver
   7 */
   8
   9#include <linux/module.h>
  10#include <linux/bitops.h>
  11#include <linux/watchdog.h>
  12#include <linux/of_platform.h>
  13#include <linux/uaccess.h>
  14#include <linux/clk.h>
  15#include <linux/io.h>
  16#include <linux/regmap.h>
  17#include <linux/mfd/syscon.h>
  18
  19#include <lantiq_soc.h>
  20
  21#define LTQ_XRX_RCU_RST_STAT            0x0014
  22#define LTQ_XRX_RCU_RST_STAT_WDT        BIT(31)
  23
  24/* CPU0 Reset Source Register */
  25#define LTQ_FALCON_SYS1_CPU0RS          0x0060
  26/* reset cause mask */
  27#define LTQ_FALCON_SYS1_CPU0RS_MASK     0x0007
  28#define LTQ_FALCON_SYS1_CPU0RS_WDT      0x02
  29
  30/*
  31 * Section 3.4 of the datasheet
  32 * The password sequence protects the WDT control register from unintended
  33 * write actions, which might cause malfunction of the WDT.
  34 *
  35 * essentially the following two magic passwords need to be written to allow
  36 * IO access to the WDT core
  37 */
  38#define LTQ_WDT_CR_PW1          0x00BE0000
  39#define LTQ_WDT_CR_PW2          0x00DC0000
  40
  41#define LTQ_WDT_CR              0x0             /* watchdog control register */
  42#define  LTQ_WDT_CR_GEN         BIT(31)         /* enable bit */
  43/* Pre-warning limit set to 1/16 of max WDT period */
  44#define  LTQ_WDT_CR_PWL         (0x3 << 26)
  45/* set clock divider to 0x40000 */
  46#define  LTQ_WDT_CR_CLKDIV      (0x3 << 24)
  47#define  LTQ_WDT_CR_PW_MASK     GENMASK(23, 16) /* Password field */
  48#define  LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
  49#define LTQ_WDT_SR              0x8             /* watchdog status register */
  50#define  LTQ_WDT_SR_EN          BIT(31)         /* Enable */
  51#define  LTQ_WDT_SR_VALUE_MASK  GENMASK(15, 0)  /* Timer value */
  52
  53#define LTQ_WDT_DIVIDER         0x40000
  54
  55static bool nowayout = WATCHDOG_NOWAYOUT;
  56
  57struct ltq_wdt_hw {
  58        int (*bootstatus_get)(struct device *dev);
  59};
  60
  61struct ltq_wdt_priv {
  62        struct watchdog_device wdt;
  63        void __iomem *membase;
  64        unsigned long clk_rate;
  65};
  66
  67static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
  68{
  69        return __raw_readl(priv->membase + offset);
  70}
  71
  72static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
  73{
  74        __raw_writel(val, priv->membase + offset);
  75}
  76
  77static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
  78                         u32 offset)
  79{
  80        u32 val = ltq_wdt_r32(priv, offset);
  81
  82        val &= ~(clear);
  83        val |= set;
  84        ltq_wdt_w32(priv, val, offset);
  85}
  86
  87static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
  88{
  89        return container_of(wdt, struct ltq_wdt_priv, wdt);
  90}
  91
  92static struct watchdog_info ltq_wdt_info = {
  93        .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  94                   WDIOF_CARDRESET,
  95        .identity = "ltq_wdt",
  96};
  97
  98static int ltq_wdt_start(struct watchdog_device *wdt)
  99{
 100        struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 101        u32 timeout;
 102
 103        timeout = wdt->timeout * priv->clk_rate;
 104
 105        ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 106        /* write the second magic plus the configuration and new timeout */
 107        ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
 108                     LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
 109                     LTQ_WDT_CR_PW2 | timeout,
 110                     LTQ_WDT_CR);
 111
 112        return 0;
 113}
 114
 115static int ltq_wdt_stop(struct watchdog_device *wdt)
 116{
 117        struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 118
 119        ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 120        ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
 121                     LTQ_WDT_CR_PW2, LTQ_WDT_CR);
 122
 123        return 0;
 124}
 125
 126static int ltq_wdt_ping(struct watchdog_device *wdt)
 127{
 128        struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 129        u32 timeout;
 130
 131        timeout = wdt->timeout * priv->clk_rate;
 132
 133        ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
 134        /* write the second magic plus the configuration and new timeout */
 135        ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
 136                     LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
 137
 138        return 0;
 139}
 140
 141static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
 142{
 143        struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
 144        u64 timeout;
 145
 146        timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
 147        return do_div(timeout, priv->clk_rate);
 148}
 149
 150static const struct watchdog_ops ltq_wdt_ops = {
 151        .owner          = THIS_MODULE,
 152        .start          = ltq_wdt_start,
 153        .stop           = ltq_wdt_stop,
 154        .ping           = ltq_wdt_ping,
 155        .get_timeleft   = ltq_wdt_get_timeleft,
 156};
 157
 158static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
 159{
 160        struct regmap *rcu_regmap;
 161        u32 val;
 162        int err;
 163
 164        rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
 165        if (IS_ERR(rcu_regmap))
 166                return PTR_ERR(rcu_regmap);
 167
 168        err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
 169        if (err)
 170                return err;
 171
 172        if (val & LTQ_XRX_RCU_RST_STAT_WDT)
 173                return WDIOF_CARDRESET;
 174
 175        return 0;
 176}
 177
 178static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
 179{
 180        struct regmap *rcu_regmap;
 181        u32 val;
 182        int err;
 183
 184        rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
 185                                                     "lantiq,rcu");
 186        if (IS_ERR(rcu_regmap))
 187                return PTR_ERR(rcu_regmap);
 188
 189        err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
 190        if (err)
 191                return err;
 192
 193        if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
 194                return WDIOF_CARDRESET;
 195
 196        return 0;
 197}
 198
 199static int ltq_wdt_probe(struct platform_device *pdev)
 200{
 201        struct device *dev = &pdev->dev;
 202        struct ltq_wdt_priv *priv;
 203        struct watchdog_device *wdt;
 204        struct clk *clk;
 205        const struct ltq_wdt_hw *ltq_wdt_hw;
 206        int ret;
 207        u32 status;
 208
 209        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 210        if (!priv)
 211                return -ENOMEM;
 212
 213        priv->membase = devm_platform_ioremap_resource(pdev, 0);
 214        if (IS_ERR(priv->membase))
 215                return PTR_ERR(priv->membase);
 216
 217        /* we do not need to enable the clock as it is always running */
 218        clk = clk_get_io();
 219        priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
 220        if (!priv->clk_rate) {
 221                dev_err(dev, "clock rate less than divider %i\n",
 222                        LTQ_WDT_DIVIDER);
 223                return -EINVAL;
 224        }
 225
 226        wdt = &priv->wdt;
 227        wdt->info               = &ltq_wdt_info;
 228        wdt->ops                = &ltq_wdt_ops;
 229        wdt->min_timeout        = 1;
 230        wdt->max_timeout        = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
 231        wdt->timeout            = wdt->max_timeout;
 232        wdt->parent             = dev;
 233
 234        ltq_wdt_hw = of_device_get_match_data(dev);
 235        if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
 236                ret = ltq_wdt_hw->bootstatus_get(dev);
 237                if (ret >= 0)
 238                        wdt->bootstatus = ret;
 239        }
 240
 241        watchdog_set_nowayout(wdt, nowayout);
 242        watchdog_init_timeout(wdt, 0, dev);
 243
 244        status = ltq_wdt_r32(priv, LTQ_WDT_SR);
 245        if (status & LTQ_WDT_SR_EN) {
 246                /*
 247                 * If the watchdog is already running overwrite it with our
 248                 * new settings. Stop is not needed as the start call will
 249                 * replace all settings anyway.
 250                 */
 251                ltq_wdt_start(wdt);
 252                set_bit(WDOG_HW_RUNNING, &wdt->status);
 253        }
 254
 255        return devm_watchdog_register_device(dev, wdt);
 256}
 257
 258static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
 259        .bootstatus_get = ltq_wdt_xrx_bootstatus_get,
 260};
 261
 262static const struct ltq_wdt_hw ltq_wdt_falcon = {
 263        .bootstatus_get = ltq_wdt_falcon_bootstatus_get,
 264};
 265
 266static const struct of_device_id ltq_wdt_match[] = {
 267        { .compatible = "lantiq,wdt", .data = NULL },
 268        { .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
 269        { .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
 270        {},
 271};
 272MODULE_DEVICE_TABLE(of, ltq_wdt_match);
 273
 274static struct platform_driver ltq_wdt_driver = {
 275        .probe = ltq_wdt_probe,
 276        .driver = {
 277                .name = "wdt",
 278                .of_match_table = ltq_wdt_match,
 279        },
 280};
 281
 282module_platform_driver(ltq_wdt_driver);
 283
 284module_param(nowayout, bool, 0);
 285MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
 286MODULE_AUTHOR("John Crispin <john@phrozen.org>");
 287MODULE_DESCRIPTION("Lantiq SoC Watchdog");
 288MODULE_LICENSE("GPL");
 289