LXR linux/include/rdma/opa_port

   1/*
   2 * Copyright (c) 2014-2017 Intel Corporation.  All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#if !defined(OPA_PORT_INFO_H)
  34#define OPA_PORT_INFO_H
  35
  36#include <rdma/opa_smi.h>
  37
  38#define OPA_PORT_LINK_MODE_NOP  0               /* No change */
  39#define OPA_PORT_LINK_MODE_OPA  4               /* Port mode is OPA */
  40
  41#define OPA_PORT_PACKET_FORMAT_NOP      0               /* No change */
  42#define OPA_PORT_PACKET_FORMAT_8B       1               /* Format 8B */
  43#define OPA_PORT_PACKET_FORMAT_9B       2               /* Format 9B */
  44#define OPA_PORT_PACKET_FORMAT_10B      4               /* Format 10B */
  45#define OPA_PORT_PACKET_FORMAT_16B      8               /* Format 16B */
  46
  47#define OPA_PORT_LTP_CRC_MODE_NONE      0       /* No change */
  48#define OPA_PORT_LTP_CRC_MODE_14        1       /* 14-bit LTP CRC mode (optional) */
  49#define OPA_PORT_LTP_CRC_MODE_16        2       /* 16-bit LTP CRC mode */
  50#define OPA_PORT_LTP_CRC_MODE_48        4       /* 48-bit LTP CRC mode (optional) */
  51#define OPA_PORT_LTP_CRC_MODE_PER_LANE  8       /* 12/16-bit per lane LTP CRC mode */
  52
  53/* Link Down / Neighbor Link Down Reason; indicated as follows: */
  54#define OPA_LINKDOWN_REASON_NONE                                0       /* No specified reason */
  55#define OPA_LINKDOWN_REASON_RCV_ERROR_0                         1
  56#define OPA_LINKDOWN_REASON_BAD_PKT_LEN                         2
  57#define OPA_LINKDOWN_REASON_PKT_TOO_LONG                        3
  58#define OPA_LINKDOWN_REASON_PKT_TOO_SHORT                       4
  59#define OPA_LINKDOWN_REASON_BAD_SLID                            5
  60#define OPA_LINKDOWN_REASON_BAD_DLID                            6
  61#define OPA_LINKDOWN_REASON_BAD_L2                              7
  62#define OPA_LINKDOWN_REASON_BAD_SC                              8
  63#define OPA_LINKDOWN_REASON_RCV_ERROR_8                         9
  64#define OPA_LINKDOWN_REASON_BAD_MID_TAIL                        10
  65#define OPA_LINKDOWN_REASON_RCV_ERROR_10                        11
  66#define OPA_LINKDOWN_REASON_PREEMPT_ERROR                       12
  67#define OPA_LINKDOWN_REASON_PREEMPT_VL15                        13
  68#define OPA_LINKDOWN_REASON_BAD_VL_MARKER                       14
  69#define OPA_LINKDOWN_REASON_RCV_ERROR_14                        15
  70#define OPA_LINKDOWN_REASON_RCV_ERROR_15                        16
  71#define OPA_LINKDOWN_REASON_BAD_HEAD_DIST                       17
  72#define OPA_LINKDOWN_REASON_BAD_TAIL_DIST                       18
  73#define OPA_LINKDOWN_REASON_BAD_CTRL_DIST                       19
  74#define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK                      20
  75#define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER               21
  76#define OPA_LINKDOWN_REASON_BAD_PREEMPT                         22
  77#define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT                    23
  78#define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT              24
  79#define OPA_LINKDOWN_REASON_RCV_ERROR_24                        25
  80#define OPA_LINKDOWN_REASON_RCV_ERROR_25                        26
  81#define OPA_LINKDOWN_REASON_RCV_ERROR_26                        27
  82#define OPA_LINKDOWN_REASON_RCV_ERROR_27                        28
  83#define OPA_LINKDOWN_REASON_RCV_ERROR_28                        29
  84#define OPA_LINKDOWN_REASON_RCV_ERROR_29                        30
  85#define OPA_LINKDOWN_REASON_RCV_ERROR_30                        31
  86#define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN            32
  87#define OPA_LINKDOWN_REASON_UNKNOWN                             33
  88/* 34 -reserved */
  89#define OPA_LINKDOWN_REASON_REBOOT                              35
  90#define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN                    36
  91/* 37-38 reserved */
  92#define OPA_LINKDOWN_REASON_FM_BOUNCE                           39
  93#define OPA_LINKDOWN_REASON_SPEED_POLICY                        40
  94#define OPA_LINKDOWN_REASON_WIDTH_POLICY                        41
  95/* 42-48 reserved */
  96#define OPA_LINKDOWN_REASON_DISCONNECTED                        49
  97#define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED           50
  98#define OPA_LINKDOWN_REASON_NOT_INSTALLED                       51
  99#define OPA_LINKDOWN_REASON_CHASSIS_CONFIG                      52
 100/* 53 reserved */
 101#define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED            54
 102/* 55 reserved */
 103#define OPA_LINKDOWN_REASON_POWER_POLICY                        56
 104#define OPA_LINKDOWN_REASON_LINKSPEED_POLICY                    57
 105#define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY                    58
 106/* 59 reserved */
 107#define OPA_LINKDOWN_REASON_SWITCH_MGMT                         60
 108#define OPA_LINKDOWN_REASON_SMA_DISABLED                        61
 109/* 62 reserved */
 110#define OPA_LINKDOWN_REASON_TRANSIENT                           63
 111/* 64-255 reserved */
 112
 113/* OPA Link Init reason; indicated as follows: */
 114/* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */
 115#define OPA_LINKINIT_REASON_NOP                 0
 116#define OPA_LINKINIT_REASON_LINKUP              (1 << 4)
 117#define OPA_LINKINIT_REASON_FLAPPING            (2 << 4)
 118#define OPA_LINKINIT_REASON_CLEAR               (8 << 4)
 119#define OPA_LINKINIT_OUTSIDE_POLICY             (8 << 4)
 120#define OPA_LINKINIT_QUARANTINED                (9 << 4)
 121#define OPA_LINKINIT_INSUFIC_CAPABILITY         (10 << 4)
 122
 123#define OPA_LINK_SPEED_NOP              0x0000  /*  Reserved (1-5 Gbps) */
 124#define OPA_LINK_SPEED_12_5G            0x0001  /*  12.5 Gbps */
 125#define OPA_LINK_SPEED_25G              0x0002  /*  25.78125?  Gbps (EDR) */
 126
 127#define OPA_LINK_WIDTH_1X            0x0001
 128#define OPA_LINK_WIDTH_2X            0x0002
 129#define OPA_LINK_WIDTH_3X            0x0004
 130#define OPA_LINK_WIDTH_4X            0x0008
 131
 132#define OPA_CAP_MASK3_IsEthOnFabricSupported      (1 << 13)
 133#define OPA_CAP_MASK3_IsSnoopSupported            (1 << 7)
 134#define OPA_CAP_MASK3_IsAsyncSC2VLSupported       (1 << 6)
 135#define OPA_CAP_MASK3_IsAddrRangeConfigSupported  (1 << 5)
 136#define OPA_CAP_MASK3_IsPassThroughSupported      (1 << 4)
 137#define OPA_CAP_MASK3_IsSharedSpaceSupported      (1 << 3)
 138/* reserved (1 << 2) */
 139#define OPA_CAP_MASK3_IsVLMarkerSupported         (1 << 1)
 140#define OPA_CAP_MASK3_IsVLrSupported              (1 << 0)
 141
 142/**
 143 * new MTU values
 144 */
 145enum {
 146        OPA_MTU_8192  = 6,
 147        OPA_MTU_10240 = 7,
 148};
 149
 150enum {
 151        OPA_PORT_PHYS_CONF_DISCONNECTED = 0,
 152        OPA_PORT_PHYS_CONF_STANDARD     = 1,
 153        OPA_PORT_PHYS_CONF_FIXED        = 2,
 154        OPA_PORT_PHYS_CONF_VARIABLE     = 3,
 155        OPA_PORT_PHYS_CONF_SI_PHOTO     = 4
 156};
 157
 158enum port_info_field_masks {
 159        /* vl.cap */
 160        OPA_PI_MASK_VL_CAP                        = 0x1F,
 161        /* port_states.ledenable_offlinereason */
 162        OPA_PI_MASK_OFFLINE_REASON                = 0x0F,
 163        OPA_PI_MASK_LED_ENABLE                    = 0x40,
 164        /* port_states.unsleepstate_downdefstate */
 165        OPA_PI_MASK_UNSLEEP_STATE                 = 0xF0,
 166        OPA_PI_MASK_DOWNDEF_STATE                 = 0x0F,
 167        /* port_states.portphysstate_portstate */
 168        OPA_PI_MASK_PORT_PHYSICAL_STATE           = 0xF0,
 169        OPA_PI_MASK_PORT_STATE                    = 0x0F,
 170        /* port_phys_conf */
 171        OPA_PI_MASK_PORT_PHYSICAL_CONF            = 0x0F,
 172        /* collectivemask_multicastmask */
 173        OPA_PI_MASK_COLLECT_MASK                  = 0x38,
 174        OPA_PI_MASK_MULTICAST_MASK                = 0x07,
 175        /* mkeyprotect_lmc */
 176        OPA_PI_MASK_MKEY_PROT_BIT                 = 0xC0,
 177        OPA_PI_MASK_LMC                           = 0x0F,
 178        /* smsl */
 179        OPA_PI_MASK_SMSL                          = 0x1F,
 180        /* partenforce_filterraw */
 181        /* Filter Raw In/Out bits 1 and 2 were removed */
 182        OPA_PI_MASK_LINKINIT_REASON               = 0xF0,
 183        OPA_PI_MASK_PARTITION_ENFORCE_IN          = 0x08,
 184        OPA_PI_MASK_PARTITION_ENFORCE_OUT         = 0x04,
 185        /* operational_vls */
 186        OPA_PI_MASK_OPERATIONAL_VL                = 0x1F,
 187        /* sa_qp */
 188        OPA_PI_MASK_SA_QP                         = 0x00FFFFFF,
 189        /* sm_trap_qp */
 190        OPA_PI_MASK_SM_TRAP_QP                    = 0x00FFFFFF,
 191        /* localphy_overrun_errors */
 192        OPA_PI_MASK_LOCAL_PHY_ERRORS              = 0xF0,
 193        OPA_PI_MASK_OVERRUN_ERRORS                = 0x0F,
 194        /* clientrereg_subnettimeout */
 195        OPA_PI_MASK_CLIENT_REREGISTER             = 0x80,
 196        OPA_PI_MASK_SUBNET_TIMEOUT                = 0x1F,
 197        /* port_link_mode */
 198        OPA_PI_MASK_PORT_LINK_SUPPORTED           = (0x001F << 10),
 199        OPA_PI_MASK_PORT_LINK_ENABLED             = (0x001F <<  5),
 200        OPA_PI_MASK_PORT_LINK_ACTIVE              = (0x001F <<  0),
 201        /* port_link_crc_mode */
 202        OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED       = 0x0F00,
 203        OPA_PI_MASK_PORT_LINK_CRC_ENABLED         = 0x00F0,
 204        OPA_PI_MASK_PORT_LINK_CRC_ACTIVE          = 0x000F,
 205        /* port_mode */
 206        OPA_PI_MASK_PORT_MODE_SECURITY_CHECK      = 0x0001,
 207        OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY      = 0x0002,
 208        OPA_PI_MASK_PORT_MODE_PKEY_CONVERT        = 0x0004,
 209        OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING       = 0x0008,
 210        OPA_PI_MASK_PORT_MODE_VL_MARKER           = 0x0010,
 211        OPA_PI_MASK_PORT_PASS_THROUGH             = 0x0020,
 212        OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE          = 0x0040,
 213        /* flit_control.interleave */
 214        OPA_PI_MASK_INTERLEAVE_DIST_SUP           = (0x0003 << 12),
 215        OPA_PI_MASK_INTERLEAVE_DIST_ENABLE        = (0x0003 << 10),
 216        OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX        = (0x001F <<  5),
 217        OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX        = (0x001F <<  0),
 218
 219        /* port_error_action */
 220        OPA_PI_MASK_EX_BUFFER_OVERRUN                  = 0x80000000,
 221                /* 7 bits reserved */
 222        OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT  = 0x00800000,
 223        OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT            = 0x00400000,
 224        OPA_PI_MASK_FM_CFG_BAD_PREEMPT                 = 0x00200000,
 225        OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER       = 0x00100000,
 226        OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK                = 0x00080000,
 227        OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST               = 0x00040000,
 228        OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST               = 0x00020000,
 229        OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST               = 0x00010000,
 230                /* 2 bits reserved */
 231        OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER             = 0x00002000,
 232        OPA_PI_MASK_PORT_RCV_PREEMPT_VL15              = 0x00001000,
 233        OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR             = 0x00000800,
 234                /* 1 bit reserved */
 235        OPA_PI_MASK_PORT_RCV_BAD_MidTail               = 0x00000200,
 236                /* 1 bit reserved */
 237        OPA_PI_MASK_PORT_RCV_BAD_SC                    = 0x00000080,
 238        OPA_PI_MASK_PORT_RCV_BAD_L2                    = 0x00000040,
 239        OPA_PI_MASK_PORT_RCV_BAD_DLID                  = 0x00000020,
 240        OPA_PI_MASK_PORT_RCV_BAD_SLID                  = 0x00000010,
 241        OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT           = 0x00000008,
 242        OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG            = 0x00000004,
 243        OPA_PI_MASK_PORT_RCV_BAD_PKTLEN                = 0x00000002,
 244        OPA_PI_MASK_PORT_RCV_BAD_LT                    = 0x00000001,
 245
 246        /* pass_through.res_drctl */
 247        OPA_PI_MASK_PASS_THROUGH_DR_CONTROL       = 0x01,
 248
 249        /* buffer_units */
 250        OPA_PI_MASK_BUF_UNIT_VL15_INIT            = (0x00000FFF  << 11),
 251        OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE     = (0x0000001F  <<  6),
 252        OPA_PI_MASK_BUF_UNIT_CREDIT_ACK           = (0x00000003  <<  3),
 253        OPA_PI_MASK_BUF_UNIT_BUF_ALLOC            = (0x00000003  <<  0),
 254
 255        /* neigh_mtu.pvlx_to_mtu */
 256        OPA_PI_MASK_NEIGH_MTU_PVL0                = 0xF0,
 257        OPA_PI_MASK_NEIGH_MTU_PVL1                = 0x0F,
 258
 259        /* neigh_mtu.vlstall_hoq_life */
 260        OPA_PI_MASK_VL_STALL                      = (0x03 << 5),
 261        OPA_PI_MASK_HOQ_LIFE                      = (0x1F << 0),
 262
 263        /* port_neigh_mode */
 264        OPA_PI_MASK_NEIGH_MGMT_ALLOWED            = (0x01 << 3),
 265        OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS          = (0x01 << 2),
 266        OPA_PI_MASK_NEIGH_NODE_TYPE               = (0x03 << 0),
 267
 268        /* resptime_value */
 269        OPA_PI_MASK_RESPONSE_TIME_VALUE           = 0x1F,
 270
 271        /* mtucap */
 272        OPA_PI_MASK_MTU_CAP                       = 0x0F,
 273};
 274
 275struct opa_port_states {
 276        u8     reserved;
 277        u8     ledenable_offlinereason;   /* 1 res, 1 bit, 6 bits */
 278        u8     reserved2;
 279        u8     portphysstate_portstate;   /* 4 bits, 4 bits */
 280};
 281
 282struct opa_port_state_info {
 283        struct opa_port_states port_states;
 284        __be16 link_width_downgrade_tx_active;
 285        __be16 link_width_downgrade_rx_active;
 286};
 287
 288struct opa_port_info {
 289        __be32 lid;
 290        __be32 flow_control_mask;
 291
 292        struct {
 293                u8     res;                       /* was inittype */
 294                u8     cap;                       /* 3 res, 5 bits */
 295                __be16 high_limit;
 296                __be16 preempt_limit;
 297                u8     arb_high_cap;
 298                u8     arb_low_cap;
 299        } vl;
 300
 301        struct opa_port_states  port_states;
 302        u8     port_phys_conf;                    /* 4 res, 4 bits */
 303        u8     collectivemask_multicastmask;      /* 2 res, 3, 3 */
 304        u8     mkeyprotect_lmc;                   /* 2 bits, 2 res, 4 bits */
 305        u8     smsl;                              /* 3 res, 5 bits */
 306
 307        u8     partenforce_filterraw;             /* bit fields */
 308        u8     operational_vls;                    /* 3 res, 5 bits */
 309        __be16 pkey_8b;
 310        __be16 pkey_10b;
 311        __be16 mkey_violations;
 312
 313        __be16 pkey_violations;
 314        __be16 qkey_violations;
 315        __be32 sm_trap_qp;                        /* 8 bits, 24 bits */
 316
 317        __be32 sa_qp;                             /* 8 bits, 24 bits */
 318        u8     neigh_port_num;
 319        u8     link_down_reason;
 320        u8     neigh_link_down_reason;
 321        u8     clientrereg_subnettimeout;         /* 1 bit, 2 bits, 5 */
 322
 323        struct {
 324                __be16 supported;
 325                __be16 enabled;
 326                __be16 active;
 327        } link_speed;
 328        struct {
 329                __be16 supported;
 330                __be16 enabled;
 331                __be16 active;
 332        } link_width;
 333        struct {
 334                __be16 supported;
 335                __be16 enabled;
 336                __be16 tx_active;
 337                __be16 rx_active;
 338        } link_width_downgrade;
 339        __be16 port_link_mode;                  /* 1 res, 5 bits, 5 bits, 5 bits */
 340        __be16 port_ltp_crc_mode;               /* 4 res, 4 bits, 4 bits, 4 bits */
 341
 342        __be16 port_mode;                       /* 9 res, bit fields */
 343        struct {
 344                __be16 supported;
 345                __be16 enabled;
 346        } port_packet_format;
 347        struct {
 348                __be16 interleave;  /* 2 res, 2,2,5,5 */
 349                struct {
 350                        __be16 min_initial;
 351                        __be16 min_tail;
 352                        u8     large_pkt_limit;
 353                        u8     small_pkt_limit;
 354                        u8     max_small_pkt_limit;
 355                        u8     preemption_limit;
 356                } preemption;
 357        } flit_control;
 358
 359        __be32 reserved4;
 360        __be32 port_error_action; /* bit field */
 361
 362        struct {
 363                u8 egress_port;
 364                u8 res_drctl;                    /* 7 res, 1 */
 365        } pass_through;
 366        __be16 mkey_lease_period;
 367        __be32 buffer_units;                     /* 9 res, 12, 5, 3, 3 */
 368
 369        __be32 reserved5;
 370        __be32 sm_lid;
 371
 372        __be64 mkey;
 373
 374        __be64 subnet_prefix;
 375
 376        struct {
 377                u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */
 378        } neigh_mtu;
 379
 380        struct {
 381                u8 vlstall_hoqlife;             /* 3 bits, 5 bits */
 382        } xmit_q[OPA_MAX_VLS];
 383
 384        struct {
 385                u8 addr[16];
 386        } ipaddr_ipv6;
 387
 388        struct {
 389                u8 addr[4];
 390        } ipaddr_ipv4;
 391
 392        u32    reserved6;
 393        u32    reserved7;
 394        u32    reserved8;
 395
 396        __be64 neigh_node_guid;
 397
 398        __be32 ib_cap_mask;
 399        __be16 reserved9;                    /* was ib_cap_mask2 */
 400        __be16 opa_cap_mask;
 401
 402        __be32 reserved10;                   /* was link_roundtrip_latency */
 403        __be16 overall_buffer_space;
 404        __be16 reserved11;                   /* was max_credit_hint */
 405
 406        __be16 diag_code;
 407        struct {
 408                u8 buffer;
 409                u8 wire;
 410        } replay_depth;
 411        u8     port_neigh_mode;
 412        u8     mtucap;                          /* 4 res, 4 bits */
 413
 414        u8     resptimevalue;                   /* 3 res, 5 bits */
 415        u8     local_port_num;
 416        u8     reserved12;
 417        u8     reserved13;                       /* was guid_cap */
 418} __packed;
 419
 420#endif /* OPA_PORT_INFO_H */
 421