linux/sound/pci/azt3328.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*  azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
   3 *  Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de>
   4 *
   5 *  Framework borrowed from Bart Hartgers's als4000.c.
   6 *  Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
   7 *  found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
   8 *  Other versions are:
   9 *  PCI168 A(W), sub ID 1800
  10 *  PCI168 A/AP, sub ID 8000
  11 *  Please give me feedback in case you try my driver with one of these!!
  12 *
  13 *  Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
  14 *  (XP/Vista do not support this card at all but every Linux distribution
  15 *   has very good support out of the box;
  16 *   just to make sure that the right people hit this and get to know that,
  17 *   despite the high level of Internet ignorance - as usual :-P -
  18 *   about very good support for this card - on Linux!)
  19 *
  20 * NOTES
  21 *  Since Aztech does not provide any chipset documentation,
  22 *  even on repeated request to various addresses,
  23 *  and the answer that was finally given was negative
  24 *  (and I was stupid enough to manage to get hold of a PCI168 soundcard
  25 *  in the first place >:-P}),
  26 *  I was forced to base this driver on reverse engineering
  27 *  (3 weeks' worth of evenings filled with driver work).
  28 *  (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
  29 *
  30 *  It is quite likely that the AZF3328 chip is the PCI cousin of the
  31 *  AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
  32 *
  33 *  The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  34 *  for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
  35 *  Fincitec acquired by National Semiconductor in 2002, together with the
  36 *  Fincitec-related company ARSmikro) has the following features:
  37 *
  38 *  - compatibility & compliance:
  39 *    - Microsoft PC 97 ("PC 97 Hardware Design Guide",
  40 *                       http://www.microsoft.com/whdc/archive/pcguides.mspx)
  41 *    - Microsoft PC 98 Baseline Audio
  42 *    - MPU401 UART
  43 *    - Sound Blaster Emulation (DOS Box)
  44 *  - builtin AC97 conformant codec (SNR over 80dB)
  45 *    Note that "conformant" != "compliant"!! this chip's mixer register layout
  46 *    *differs* from the standard AC97 layout:
  47 *    they chose to not implement the headphone register (which is not a
  48 *    problem since it's merely optional), yet when doing this, they committed
  49 *    the grave sin of letting other registers follow immediately instead of
  50 *    keeping a headphone dummy register, thereby shifting the mixer register
  51 *    addresses illegally. So far unfortunately it looks like the very flexible
  52 *    ALSA AC97 support is still not enough to easily compensate for such a
  53 *    grave layout violation despite all tweaks and quirks mechanisms it offers.
  54 *    Well, not quite: now ac97 layer is much improved (bus-specific ops!),
  55 *    thus I was able to implement support - it's actually working quite well.
  56 *    An interesting item might be Aztech AMR 2800-W, since it's an AC97
  57 *    modem card which might reveal the Aztech-specific codec ID which
  58 *    we might want to pretend, too. Dito PCI168's brother, PCI368,
  59 *    where the advertising datasheet says it's AC97-based and has a
  60 *    Digital Enhanced Game Port.
  61 *  - builtin genuine OPL3 - verified to work fine, 20080506
  62 *  - full duplex 16bit playback/record at independent sampling rate
  63 *  - MPU401 (+ legacy address support, claimed by one official spec sheet)
  64 *    FIXME: how to enable legacy addr??
  65 *  - game port (legacy address support)
  66 *  - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
  67 *    features supported). - See common term "Digital Enhanced Game Port"...
  68 *    (probably DirectInput 3.0 spec - confirm)
  69 *  - builtin 3D enhancement (said to be YAMAHA Ymersion)
  70 *  - built-in General DirectX timer having a 20 bits counter
  71 *    with 1us resolution (see below!)
  72 *  - I2S serial output port for external DAC
  73 *    [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
  74 *  - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  75 *  - supports hardware volume control
  76 *  - single chip low cost solution (128 pin QFP)
  77 *  - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
  78 *    required for Microsoft's logo compliance (FIXME: where?)
  79 *    At least the Trident 4D Wave DX has one bit somewhere
  80 *    to enable writes to PCI subsystem VID registers, that should be it.
  81 *    This might easily be in extended PCI reg space, since PCI168 also has
  82 *    some custom data starting at 0x80. What kind of config settings
  83 *    are located in our extended PCI space anyway??
  84 *  - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  85 *    [TDA1517P chip]
  86 *
  87 *  Note that this driver now is actually *better* than the Windows driver,
  88 *  since it additionally supports the card's 1MHz DirectX timer - just try
  89 *  the following snd-seq module parameters etc.:
  90 *  - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  91 *    seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  92 *    seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  93 *  - "timidity -iAv -B2,8 -Os -EFreverb=0"
  94 *  - "pmidi -p 128:0 jazz.mid"
  95 *
  96 *  OPL3 hardware playback testing, try something like:
  97 *  cat /proc/asound/hwdep
  98 *  and
  99 *  aconnect -o
 100 *  Then use
 101 *  sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
 102 *  where x,y is the xx-yy number as given in hwdep.
 103 *  Then try
 104 *  pmidi -p a:b jazz.mid
 105 *  where a:b is the client number plus 0 usually, as given by aconnect above.
 106 *  Oh, and make sure to unmute the FM mixer control (doh!)
 107 *  NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
 108 *  despite no CPU activity, possibly due to hindering ACPI idling somehow.
 109 *  Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
 110 *  Higher PCM / FM mixer levels seem to conflict (causes crackling),
 111 *  at least sometimes.   Maybe even use with hardware sequencer timer above :)
 112 *  adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
 113 *
 114 *  Certain PCI versions of this card are susceptible to DMA traffic underruns
 115 *  in some systems (resulting in sound crackling/clicking/popping),
 116 *  probably because they don't have a DMA FIFO buffer or so.
 117 *  Overview (PCI ID/PCI subID/PCI rev.):
 118 *  - no DMA crackling on SiS735: 0x50DC/0x1801/16
 119 *  - unknown performance: 0x50DC/0x1801/10
 120 *    (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
 121 *
 122 *  Crackling happens with VIA chipsets or, in my case, an SiS735, which is
 123 *  supposed to be very fast and supposed to get rid of crackling much
 124 *  better than a VIA, yet ironically I still get crackling, like many other
 125 *  people with the same chipset.
 126 *  Possible remedies:
 127 *  - use speaker (amplifier) output instead of headphone output
 128 *    (in case crackling is due to overloaded output clipping)
 129 *  - plug card into a different PCI slot, preferably one that isn't shared
 130 *    too much (this helps a lot, but not completely!)
 131 *  - get rid of PCI VGA card, use AGP instead
 132 *  - upgrade or downgrade BIOS
 133 *  - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
 134 *    Not too helpful.
 135 *  - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
 136 *
 137 * BUGS
 138 *  - full-duplex might *still* be problematic, however a recent test was fine
 139 *  - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
 140 *    if you set PCM output switch to "pre 3D" instead of "post 3D".
 141 *    If this can't be set, then get a mixer application that Isn't Stupid (tm)
 142 *    (e.g. kmix, gamix) - unfortunately several are!!
 143 *  - locking is not entirely clean, especially the audio stream activity
 144 *    ints --> may be racy
 145 *  - an _unconnected_ secondary joystick at the gameport will be reported
 146 *    to be "active" (floating values, not precisely -1) due to the way we need
 147 *    to read the Digital Enhanced Game Port. Not sure whether it is fixable.
 148 *
 149 * TODO
 150 *  - use PCI_VDEVICE
 151 *  - verify driver status on x86_64
 152 *  - test multi-card driver operation
 153 *  - (ab)use 1MHz DirectX timer as kernel clocksource
 154 *  - test MPU401 MIDI playback etc.
 155 *  - add more power micro-management (disable various units of the card
 156 *    as long as they're unused, to improve audio quality and save power).
 157 *    However this requires more I/O ports which I haven't figured out yet
 158 *    and which thus might not even exist...
 159 *    The standard suspend/resume functionality could probably make use of
 160 *    some improvement, too...
 161 *  - figure out what all unknown port bits are responsible for
 162 *  - figure out some cleverly evil scheme to possibly make ALSA AC97 code
 163 *    fully accept our quite incompatible ""AC97"" mixer and thus save some
 164 *    code (but I'm not too optimistic that doing this is possible at all)
 165 *  - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
 166 */
 167
 168#include <linux/io.h>
 169#include <linux/init.h>
 170#include <linux/bug.h> /* WARN_ONCE */
 171#include <linux/pci.h>
 172#include <linux/delay.h>
 173#include <linux/slab.h>
 174#include <linux/gameport.h>
 175#include <linux/module.h>
 176#include <linux/dma-mapping.h>
 177#include <sound/core.h>
 178#include <sound/control.h>
 179#include <sound/pcm.h>
 180#include <sound/rawmidi.h>
 181#include <sound/mpu401.h>
 182#include <sound/opl3.h>
 183#include <sound/initval.h>
 184/*
 185 * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap.
 186 * If the AC97 compatibility parts we needed to implement locally turn out
 187 * to work nicely, then remove the old implementation eventually.
 188 */
 189#define AZF_USE_AC97_LAYER 1
 190
 191#ifdef AZF_USE_AC97_LAYER
 192#include <sound/ac97_codec.h>
 193#endif
 194#include "azt3328.h"
 195
 196MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
 197MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
 198MODULE_LICENSE("GPL");
 199MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
 200
 201#if IS_REACHABLE(CONFIG_GAMEPORT)
 202#define SUPPORT_GAMEPORT 1
 203#endif
 204
 205/* === Debug settings ===
 206  Further diagnostic functionality than the settings below
 207  does not need to be provided, since one can easily write a POSIX shell script
 208  to dump the card's I/O ports (those listed in lspci -v -v):
 209  dump()
 210  {
 211    local descr=$1; local addr=$2; local count=$3
 212
 213    echo "${descr}: ${count} @ ${addr}:"
 214    dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
 215      2>/dev/null| hexdump -C
 216  }
 217  and then use something like
 218  "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
 219  "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
 220  possibly within a "while true; do ... sleep 1; done" loop.
 221  Tweaking ports could be done using
 222  VALSTRING="`printf "%02x" $value`"
 223  printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
 224    2>/dev/null
 225*/
 226
 227static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
 228module_param_array(index, int, NULL, 0444);
 229MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
 230
 231static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
 232module_param_array(id, charp, NULL, 0444);
 233MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
 234
 235static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
 236module_param_array(enable, bool, NULL, 0444);
 237MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
 238
 239static int seqtimer_scaling = 128;
 240module_param(seqtimer_scaling, int, 0444);
 241MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
 242
 243enum snd_azf3328_codec_type {
 244  /* warning: fixed indices (also used for bitmask checks!) */
 245  AZF_CODEC_PLAYBACK = 0,
 246  AZF_CODEC_CAPTURE = 1,
 247  AZF_CODEC_I2S_OUT = 2,
 248};
 249
 250struct snd_azf3328_codec_data {
 251        unsigned long io_base; /* keep first! (avoid offset calc) */
 252        unsigned int dma_base; /* helper to avoid an indirection in hotpath */
 253        spinlock_t *lock; /* TODO: convert to our own per-codec lock member */
 254        struct snd_pcm_substream *substream;
 255        bool running;
 256        enum snd_azf3328_codec_type type;
 257        const char *name;
 258};
 259
 260struct snd_azf3328 {
 261        /* often-used fields towards beginning, then grouped */
 262
 263        unsigned long ctrl_io; /* usually 0xb000, size 128 */
 264        unsigned long game_io;  /* usually 0xb400, size 8 */
 265        unsigned long mpu_io;   /* usually 0xb800, size 4 */
 266        unsigned long opl3_io; /* usually 0xbc00, size 8 */
 267        unsigned long mixer_io; /* usually 0xc000, size 64 */
 268
 269        spinlock_t reg_lock;
 270
 271        struct snd_timer *timer;
 272
 273        struct snd_pcm *pcm[3];
 274
 275        /* playback, recording and I2S out codecs */
 276        struct snd_azf3328_codec_data codecs[3];
 277
 278#ifdef AZF_USE_AC97_LAYER
 279        struct snd_ac97 *ac97;
 280#endif
 281
 282        struct snd_card *card;
 283        struct snd_rawmidi *rmidi;
 284
 285#ifdef SUPPORT_GAMEPORT
 286        struct gameport *gameport;
 287        u16 axes[4];
 288#endif
 289
 290        struct pci_dev *pci;
 291        int irq;
 292
 293        /* register 0x6a is write-only, thus need to remember setting.
 294         * If we need to add more registers here, then we might try to fold this
 295         * into some transparent combined shadow register handling with
 296         * CONFIG_PM register storage below, but that's slightly difficult. */
 297        u16 shadow_reg_ctrl_6AH;
 298
 299#ifdef CONFIG_PM_SLEEP
 300        /* register value containers for power management
 301         * Note: not always full I/O range preserved (similar to Win driver!) */
 302        u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
 303        u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
 304        u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
 305        u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
 306        u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
 307#endif
 308};
 309
 310static const struct pci_device_id snd_azf3328_ids[] = {
 311        { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },   /* PCI168/3328 */
 312        { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },   /* 3328 */
 313        { 0, }
 314};
 315
 316MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
 317
 318
 319static int
 320snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
 321{
 322        /* Well, strictly spoken, the inb/outb sequence isn't atomic
 323           and would need locking. However we currently don't care
 324           since it potentially complicates matters. */
 325        u8 prev = inb(reg), new;
 326
 327        new = (do_set) ? (prev|mask) : (prev & ~mask);
 328        /* we need to always write the new value no matter whether it differs
 329         * or not, since some register bits don't indicate their setting */
 330        outb(new, reg);
 331        if (new != prev)
 332                return 1;
 333
 334        return 0;
 335}
 336
 337static inline void
 338snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
 339                       unsigned reg,
 340                       u8 value
 341)
 342{
 343        outb(value, codec->io_base + reg);
 344}
 345
 346static inline u8
 347snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
 348{
 349        return inb(codec->io_base + reg);
 350}
 351
 352static inline void
 353snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
 354                       unsigned reg,
 355                       u16 value
 356)
 357{
 358        outw(value, codec->io_base + reg);
 359}
 360
 361static inline u16
 362snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
 363{
 364        return inw(codec->io_base + reg);
 365}
 366
 367static inline void
 368snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
 369                       unsigned reg,
 370                       u32 value
 371)
 372{
 373        outl(value, codec->io_base + reg);
 374}
 375
 376static inline void
 377snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
 378                             unsigned reg, const void *buffer, int count
 379)
 380{
 381        unsigned long addr = codec->io_base + reg;
 382        if (count) {
 383                const u32 *buf = buffer;
 384                do {
 385                        outl(*buf++, addr);
 386                        addr += 4;
 387                } while (--count);
 388        }
 389}
 390
 391static inline u32
 392snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
 393{
 394        return inl(codec->io_base + reg);
 395}
 396
 397static inline void
 398snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
 399{
 400        outb(value, chip->ctrl_io + reg);
 401}
 402
 403static inline u8
 404snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
 405{
 406        return inb(chip->ctrl_io + reg);
 407}
 408
 409static inline u16
 410snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg)
 411{
 412        return inw(chip->ctrl_io + reg);
 413}
 414
 415static inline void
 416snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
 417{
 418        outw(value, chip->ctrl_io + reg);
 419}
 420
 421static inline void
 422snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
 423{
 424        outl(value, chip->ctrl_io + reg);
 425}
 426
 427static inline void
 428snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
 429{
 430        outb(value, chip->game_io + reg);
 431}
 432
 433static inline void
 434snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
 435{
 436        outw(value, chip->game_io + reg);
 437}
 438
 439static inline u8
 440snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
 441{
 442        return inb(chip->game_io + reg);
 443}
 444
 445static inline u16
 446snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
 447{
 448        return inw(chip->game_io + reg);
 449}
 450
 451static inline void
 452snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
 453{
 454        outw(value, chip->mixer_io + reg);
 455}
 456
 457static inline u16
 458snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
 459{
 460        return inw(chip->mixer_io + reg);
 461}
 462
 463#define AZF_MUTE_BIT 0x80
 464
 465static bool
 466snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip,
 467                           unsigned reg, bool do_mute
 468)
 469{
 470        unsigned long portbase = chip->mixer_io + reg + 1;
 471        bool updated;
 472
 473        /* the mute bit is on the *second* (i.e. right) register of a
 474         * left/right channel setting */
 475        updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
 476
 477        /* indicate whether it was muted before */
 478        return (do_mute) ? !updated : updated;
 479}
 480
 481static inline bool
 482snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip,
 483                           bool do_mute
 484)
 485{
 486        return snd_azf3328_mixer_mute_control(
 487                chip,
 488                IDX_MIXER_PLAY_MASTER,
 489                do_mute
 490        );
 491}
 492
 493static inline bool
 494snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip,
 495                           bool do_mute
 496)
 497{
 498        return snd_azf3328_mixer_mute_control(
 499                chip,
 500                IDX_MIXER_WAVEOUT,
 501                do_mute
 502        );
 503}
 504
 505static inline void
 506snd_azf3328_mixer_reset(const struct snd_azf3328 *chip)
 507{
 508        /* reset (close) mixer:
 509         * first mute master volume, then reset
 510         */
 511        snd_azf3328_mixer_mute_control_master(chip, 1);
 512        snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
 513}
 514
 515#ifdef AZF_USE_AC97_LAYER
 516
 517static inline void
 518snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip,
 519                                       unsigned short reg, const char *mode)
 520{
 521        /* need to add some more or less clever emulation? */
 522        dev_warn(chip->card->dev,
 523                "missing %s emulation for AC97 register 0x%02x!\n",
 524                mode, reg);
 525}
 526
 527/*
 528 * Need to have _special_ AC97 mixer hardware register index mapper,
 529 * to compensate for the issue of a rather AC97-incompatible hardware layout.
 530 */
 531#define AZF_REG_MASK 0x3f
 532#define AZF_AC97_REG_UNSUPPORTED 0x8000
 533#define AZF_AC97_REG_REAL_IO_READ 0x4000
 534#define AZF_AC97_REG_REAL_IO_WRITE 0x2000
 535#define AZF_AC97_REG_REAL_IO_RW \
 536        (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE)
 537#define AZF_AC97_REG_EMU_IO_READ 0x0400
 538#define AZF_AC97_REG_EMU_IO_WRITE 0x0200
 539#define AZF_AC97_REG_EMU_IO_RW \
 540        (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE)
 541static unsigned short
 542snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg)
 543{
 544        static const struct {
 545                unsigned short azf_reg;
 546        } azf_reg_mapper[] = {
 547                /* Especially when taking into consideration
 548                 * mono/stereo-based sequence of azf vs. AC97 control series,
 549                 * it's quite obvious that azf simply got rid
 550                 * of the AC97_HEADPHONE control at its intended offset,
 551                 * thus shifted _all_ controls by one,
 552                 * and _then_ simply added it as an FMSYNTH control at the end,
 553                 * to make up for the offset.
 554                 * This means we'll have to translate indices here as
 555                 * needed and then do some tiny AC97 patch action
 556                 * (snd_ac97_rename_vol_ctl() etc.) - that's it.
 557                 */
 558                { /* AC97_RESET */ IDX_MIXER_RESET
 559                        | AZF_AC97_REG_REAL_IO_WRITE
 560                        | AZF_AC97_REG_EMU_IO_READ },
 561                { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER },
 562                 /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */
 563                { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH },
 564                { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT },
 565                { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE },
 566                { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP },
 567                { /* AC97_PHONE */ IDX_MIXER_MODEMIN },
 568                { /* AC97_MIC */ IDX_MIXER_MIC },
 569                { /* AC97_LINE */ IDX_MIXER_LINEIN },
 570                { /* AC97_CD */ IDX_MIXER_CDAUDIO },
 571                { /* AC97_VIDEO */ IDX_MIXER_VIDEO },
 572                { /* AC97_AUX */ IDX_MIXER_AUX },
 573                { /* AC97_PCM */ IDX_MIXER_WAVEOUT },
 574                { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT },
 575                { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME },
 576                { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW },
 577                { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 },
 578                { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 },
 579        };
 580
 581        unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED;
 582
 583        /* azf3328 supports the low-numbered and low-spec:ed range
 584           of AC97 regs only */
 585        if (reg <= AC97_3D_CONTROL) {
 586                unsigned short reg_idx = reg / 2;
 587                reg_azf = azf_reg_mapper[reg_idx].azf_reg;
 588                /* a translation-only entry means it's real read/write: */
 589                if (!(reg_azf & ~AZF_REG_MASK))
 590                        reg_azf |= AZF_AC97_REG_REAL_IO_RW;
 591        } else {
 592                switch (reg) {
 593                case AC97_POWERDOWN:
 594                        reg_azf = AZF_AC97_REG_EMU_IO_RW;
 595                        break;
 596                case AC97_EXTENDED_ID:
 597                        reg_azf = AZF_AC97_REG_EMU_IO_READ;
 598                        break;
 599                case AC97_EXTENDED_STATUS:
 600                        /* I don't know what the h*ll AC97 layer
 601                         * would consult this _extended_ register for
 602                         * given a base-AC97-advertised card,
 603                         * but let's just emulate it anyway :-P
 604                         */
 605                        reg_azf = AZF_AC97_REG_EMU_IO_RW;
 606                        break;
 607                case AC97_VENDOR_ID1:
 608                case AC97_VENDOR_ID2:
 609                        reg_azf = AZF_AC97_REG_EMU_IO_READ;
 610                        break;
 611                }
 612        }
 613        return reg_azf;
 614}
 615
 616static const unsigned short
 617azf_emulated_ac97_caps =
 618        AC97_BC_DEDICATED_MIC |
 619        AC97_BC_BASS_TREBLE |
 620        /* Headphone is an FM Synth control here */
 621        AC97_BC_HEADPHONE |
 622        /* no AC97_BC_LOUDNESS! */
 623        /* mask 0x7c00 is
 624           vendor-specific 3D enhancement
 625           vendor indicator.
 626           Since there actually _is_ an
 627           entry for Aztech Labs
 628           (13), make damn sure
 629           to indicate it. */
 630        (13 << 10);
 631
 632static const unsigned short
 633azf_emulated_ac97_powerdown =
 634        /* pretend everything to be active */
 635                AC97_PD_ADC_STATUS |
 636                AC97_PD_DAC_STATUS |
 637                AC97_PD_MIXER_STATUS |
 638                AC97_PD_VREF_STATUS;
 639
 640/*
 641 * Emulated, _inofficial_ vendor ID
 642 * (there might be some devices such as the MR 2800-W
 643 * which could reveal the real Aztech AC97 ID).
 644 * We choose to use "AZT" prefix, and then use 1 to indicate PCI168
 645 * (better don't use 0x68 since there's a PCI368 as well).
 646 */
 647static const unsigned int
 648azf_emulated_ac97_vendor_id = 0x415a5401;
 649
 650static unsigned short
 651snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97)
 652{
 653        const struct snd_azf3328 *chip = ac97->private_data;
 654        unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
 655        unsigned short reg_val = 0;
 656        bool unsupported = false;
 657
 658        dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n",
 659                reg_ac97);
 660        if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
 661                unsupported = true;
 662        else {
 663                if (reg_azf & AZF_AC97_REG_REAL_IO_READ)
 664                        reg_val = snd_azf3328_mixer_inw(chip,
 665                                                reg_azf & AZF_REG_MASK);
 666                else {
 667                        /*
 668                         * Proceed with dummy I/O read,
 669                         * to ensure compatible timing where this may matter.
 670                         * (ALSA AC97 layer usually doesn't call I/O functions
 671                         * due to intelligent I/O caching anyway)
 672                         * Choose a mixer register that's thoroughly unrelated
 673                         * to common audio (try to minimize distortion).
 674                         */
 675                        snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H);
 676                }
 677
 678                if (reg_azf & AZF_AC97_REG_EMU_IO_READ) {
 679                        switch (reg_ac97) {
 680                        case AC97_RESET:
 681                                reg_val |= azf_emulated_ac97_caps;
 682                                break;
 683                        case AC97_POWERDOWN:
 684                                reg_val |= azf_emulated_ac97_powerdown;
 685                                break;
 686                        case AC97_EXTENDED_ID:
 687                        case AC97_EXTENDED_STATUS:
 688                                /* AFAICS we simply can't support anything: */
 689                                reg_val |= 0;
 690                                break;
 691                        case AC97_VENDOR_ID1:
 692                                reg_val = azf_emulated_ac97_vendor_id >> 16;
 693                                break;
 694                        case AC97_VENDOR_ID2:
 695                                reg_val = azf_emulated_ac97_vendor_id & 0xffff;
 696                                break;
 697                        default:
 698                                unsupported = true;
 699                                break;
 700                        }
 701                }
 702        }
 703        if (unsupported)
 704                snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read");
 705
 706        return reg_val;
 707}
 708
 709static void
 710snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97,
 711                     unsigned short reg_ac97, unsigned short val)
 712{
 713        const struct snd_azf3328 *chip = ac97->private_data;
 714        unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
 715        bool unsupported = false;
 716
 717        dev_dbg(chip->card->dev,
 718                "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n",
 719                reg_ac97, val);
 720        if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
 721                unsupported = true;
 722        else {
 723                if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE)
 724                        snd_azf3328_mixer_outw(
 725                                chip,
 726                                reg_azf & AZF_REG_MASK,
 727                                val
 728                        );
 729                else
 730                if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) {
 731                        switch (reg_ac97) {
 732                        case AC97_REC_GAIN_MIC:
 733                        case AC97_POWERDOWN:
 734                        case AC97_EXTENDED_STATUS:
 735                                /*
 736                                 * Silently swallow these writes.
 737                                 * Since for most registers our card doesn't
 738                                 * actually support a comparable feature,
 739                                 * this is exactly what we should do here.
 740                                 * The AC97 layer's I/O caching probably
 741                                 * automatically takes care of all the rest...
 742                                 * (remembers written values etc.)
 743                                 */
 744                                break;
 745                        default:
 746                                unsupported = true;
 747                                break;
 748                        }
 749                }
 750        }
 751        if (unsupported)
 752                snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write");
 753}
 754
 755static int
 756snd_azf3328_mixer_new(struct snd_azf3328 *chip)
 757{
 758        struct snd_ac97_bus *bus;
 759        struct snd_ac97_template ac97;
 760        static struct snd_ac97_bus_ops ops = {
 761                .write = snd_azf3328_mixer_ac97_write,
 762                .read = snd_azf3328_mixer_ac97_read,
 763        };
 764        int rc;
 765
 766        memset(&ac97, 0, sizeof(ac97));
 767        ac97.scaps = AC97_SCAP_SKIP_MODEM
 768                        | AC97_SCAP_AUDIO /* we support audio! */
 769                        | AC97_SCAP_NO_SPDIF;
 770        ac97.private_data = chip;
 771        ac97.pci = chip->pci;
 772
 773        /*
 774         * ALSA's AC97 layer has terrible init crackling issues,
 775         * unfortunately, and since it makes use of AC97_RESET,
 776         * there's no use trying to mute Master Playback proactively.
 777         */
 778
 779        rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus);
 780        if (!rc)
 781                rc = snd_ac97_mixer(bus, &ac97, &chip->ac97);
 782                /*
 783                 * Make sure to complain loudly in case of AC97 init failure,
 784                 * since failure may happen quite often,
 785                 * due to this card being a very quirky AC97 "lookalike".
 786                 */
 787        if (rc)
 788                dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc);
 789
 790        /* If we return an error here, then snd_card_free() should
 791         * free up any ac97 codecs that got created, as well as the bus.
 792         */
 793        return rc;
 794}
 795#else /* AZF_USE_AC97_LAYER */
 796static void
 797snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
 798                                         unsigned reg,
 799                                         unsigned char dst_vol_left,
 800                                         unsigned char dst_vol_right,
 801                                         int chan_sel, int delay
 802)
 803{
 804        unsigned long portbase = chip->mixer_io + reg;
 805        unsigned char curr_vol_left = 0, curr_vol_right = 0;
 806        int left_change = 0, right_change = 0;
 807
 808        if (chan_sel & SET_CHAN_LEFT) {
 809                curr_vol_left  = inb(portbase + 1);
 810
 811                /* take care of muting flag contained in left channel */
 812                if (curr_vol_left & AZF_MUTE_BIT)
 813                        dst_vol_left |= AZF_MUTE_BIT;
 814                else
 815                        dst_vol_left &= ~AZF_MUTE_BIT;
 816
 817                left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
 818        }
 819
 820        if (chan_sel & SET_CHAN_RIGHT) {
 821                curr_vol_right = inb(portbase + 0);
 822
 823                right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
 824        }
 825
 826        do {
 827                if (left_change) {
 828                        if (curr_vol_left != dst_vol_left) {
 829                                curr_vol_left += left_change;
 830                                outb(curr_vol_left, portbase + 1);
 831                        } else
 832                            left_change = 0;
 833                }
 834                if (right_change) {
 835                        if (curr_vol_right != dst_vol_right) {
 836                                curr_vol_right += right_change;
 837
 838                        /* during volume change, the right channel is crackling
 839                         * somewhat more than the left channel, unfortunately.
 840                         * This seems to be a hardware issue. */
 841                                outb(curr_vol_right, portbase + 0);
 842                        } else
 843                            right_change = 0;
 844                }
 845                if (delay)
 846                        mdelay(delay);
 847        } while ((left_change) || (right_change));
 848}
 849
 850/*
 851 * general mixer element
 852 */
 853struct azf3328_mixer_reg {
 854        unsigned reg;
 855        unsigned int lchan_shift, rchan_shift;
 856        unsigned int mask;
 857        unsigned int invert: 1;
 858        unsigned int stereo: 1;
 859        unsigned int enum_c: 4;
 860};
 861
 862#define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
 863 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
 864  (mask << 16) | \
 865  (invert << 24) | \
 866  (stereo << 25) | \
 867  (enum_c << 26))
 868
 869static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
 870{
 871        r->reg = val & 0xff;
 872        r->lchan_shift = (val >> 8) & 0x0f;
 873        r->rchan_shift = (val >> 12) & 0x0f;
 874        r->mask = (val >> 16) & 0xff;
 875        r->invert = (val >> 24) & 1;
 876        r->stereo = (val >> 25) & 1;
 877        r->enum_c = (val >> 26) & 0x0f;
 878}
 879
 880/*
 881 * mixer switches/volumes
 882 */
 883
 884#define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
 885{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 886  .info = snd_azf3328_info_mixer, \
 887  .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
 888  .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
 889}
 890
 891#define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
 892{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 893  .info = snd_azf3328_info_mixer, \
 894  .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
 895  .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
 896}
 897
 898#define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
 899{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 900  .info = snd_azf3328_info_mixer, \
 901  .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
 902  .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
 903}
 904
 905#define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
 906{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 907  .info = snd_azf3328_info_mixer, \
 908  .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
 909  .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
 910}
 911
 912#define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
 913{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 914  .info = snd_azf3328_info_mixer_enum, \
 915  .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
 916  .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
 917}
 918
 919static int
 920snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
 921                       struct snd_ctl_elem_info *uinfo)
 922{
 923        struct azf3328_mixer_reg reg;
 924
 925        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
 926        uinfo->type = reg.mask == 1 ?
 927                SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
 928        uinfo->count = reg.stereo + 1;
 929        uinfo->value.integer.min = 0;
 930        uinfo->value.integer.max = reg.mask;
 931        return 0;
 932}
 933
 934static int
 935snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
 936                      struct snd_ctl_elem_value *ucontrol)
 937{
 938        struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
 939        struct azf3328_mixer_reg reg;
 940        u16 oreg, val;
 941
 942        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
 943
 944        oreg = snd_azf3328_mixer_inw(chip, reg.reg);
 945        val = (oreg >> reg.lchan_shift) & reg.mask;
 946        if (reg.invert)
 947                val = reg.mask - val;
 948        ucontrol->value.integer.value[0] = val;
 949        if (reg.stereo) {
 950                val = (oreg >> reg.rchan_shift) & reg.mask;
 951                if (reg.invert)
 952                        val = reg.mask - val;
 953                ucontrol->value.integer.value[1] = val;
 954        }
 955        dev_dbg(chip->card->dev,
 956                "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
 957                reg.reg, oreg,
 958                ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
 959                reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
 960        return 0;
 961}
 962
 963static int
 964snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
 965                      struct snd_ctl_elem_value *ucontrol)
 966{
 967        struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
 968        struct azf3328_mixer_reg reg;
 969        u16 oreg, nreg, val;
 970
 971        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
 972        oreg = snd_azf3328_mixer_inw(chip, reg.reg);
 973        val = ucontrol->value.integer.value[0] & reg.mask;
 974        if (reg.invert)
 975                val = reg.mask - val;
 976        nreg = oreg & ~(reg.mask << reg.lchan_shift);
 977        nreg |= (val << reg.lchan_shift);
 978        if (reg.stereo) {
 979                val = ucontrol->value.integer.value[1] & reg.mask;
 980                if (reg.invert)
 981                        val = reg.mask - val;
 982                nreg &= ~(reg.mask << reg.rchan_shift);
 983                nreg |= (val << reg.rchan_shift);
 984        }
 985        if (reg.mask >= 0x07) /* it's a volume control, so better take care */
 986                snd_azf3328_mixer_write_volume_gradually(
 987                        chip, reg.reg, nreg >> 8, nreg & 0xff,
 988                        /* just set both channels, doesn't matter */
 989                        SET_CHAN_LEFT|SET_CHAN_RIGHT,
 990                        0);
 991        else
 992                snd_azf3328_mixer_outw(chip, reg.reg, nreg);
 993
 994        dev_dbg(chip->card->dev,
 995                "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
 996                reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
 997                oreg, reg.lchan_shift, reg.rchan_shift,
 998                nreg, snd_azf3328_mixer_inw(chip, reg.reg));
 999        return (nreg != oreg);
1000}
1001
1002static int
1003snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
1004                            struct snd_ctl_elem_info *uinfo)
1005{
1006        static const char * const texts1[] = {
1007                "Mic1", "Mic2"
1008        };
1009        static const char * const texts2[] = {
1010                "Mix", "Mic"
1011        };
1012        static const char * const texts3[] = {
1013                "Mic", "CD", "Video", "Aux",
1014                "Line", "Mix", "Mix Mono", "Phone"
1015        };
1016        static const char * const texts4[] = {
1017                "pre 3D", "post 3D"
1018        };
1019        struct azf3328_mixer_reg reg;
1020        const char * const *p = NULL;
1021
1022        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1023        if (reg.reg == IDX_MIXER_ADVCTL2) {
1024                switch(reg.lchan_shift) {
1025                case 8: /* modem out sel */
1026                        p = texts1;
1027                        break;
1028                case 9: /* mono sel source */
1029                        p = texts2;
1030                        break;
1031                case 15: /* PCM Out Path */
1032                        p = texts4;
1033                        break;
1034                }
1035        } else if (reg.reg == IDX_MIXER_REC_SELECT)
1036                p = texts3;
1037
1038        return snd_ctl_enum_info(uinfo,
1039                                 (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1,
1040                                 reg.enum_c, p);
1041}
1042
1043static int
1044snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
1045                           struct snd_ctl_elem_value *ucontrol)
1046{
1047        struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1048        struct azf3328_mixer_reg reg;
1049        unsigned short val;
1050
1051        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1052        val = snd_azf3328_mixer_inw(chip, reg.reg);
1053        if (reg.reg == IDX_MIXER_REC_SELECT) {
1054                ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
1055                ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
1056        } else
1057                ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
1058
1059        dev_dbg(chip->card->dev,
1060                "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
1061                reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
1062                reg.lchan_shift, reg.enum_c);
1063        return 0;
1064}
1065
1066static int
1067snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
1068                           struct snd_ctl_elem_value *ucontrol)
1069{
1070        struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
1071        struct azf3328_mixer_reg reg;
1072        u16 oreg, nreg, val;
1073
1074        snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
1075        oreg = snd_azf3328_mixer_inw(chip, reg.reg);
1076        val = oreg;
1077        if (reg.reg == IDX_MIXER_REC_SELECT) {
1078                if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
1079                ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
1080                        return -EINVAL;
1081                val = (ucontrol->value.enumerated.item[0] << 8) |
1082                      (ucontrol->value.enumerated.item[1] << 0);
1083        } else {
1084                if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
1085                        return -EINVAL;
1086                val &= ~((reg.enum_c - 1) << reg.lchan_shift);
1087                val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
1088        }
1089        snd_azf3328_mixer_outw(chip, reg.reg, val);
1090        nreg = val;
1091
1092        dev_dbg(chip->card->dev,
1093                "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
1094        return (nreg != oreg);
1095}
1096
1097static struct snd_kcontrol_new snd_azf3328_mixer_controls[] = {
1098        AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
1099        AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
1100        AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
1101        AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
1102                                        IDX_MIXER_WAVEOUT, 0x1f, 1),
1103        AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
1104                                        IDX_MIXER_ADVCTL2, 7, 1),
1105        AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
1106        AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
1107        AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
1108        AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
1109        AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
1110        AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
1111        AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
1112        AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
1113        AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
1114        AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
1115        AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
1116        AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
1117        AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
1118        AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
1119        AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
1120        AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
1121        AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
1122        AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
1123        AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
1124        AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
1125        AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
1126        AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
1127        AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
1128        AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
1129        AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
1130        AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
1131        AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
1132        AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
1133        AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
1134        AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
1135#if MIXER_TESTING
1136        AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
1137        AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
1138        AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
1139        AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
1140        AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
1141        AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
1142        AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
1143        AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
1144        AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
1145        AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
1146        AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
1147        AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
1148        AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
1149        AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
1150        AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
1151        AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
1152#endif
1153};
1154
1155static u16 snd_azf3328_init_values[][2] = {
1156        { IDX_MIXER_PLAY_MASTER,        MIXER_MUTE_MASK|0x1f1f },
1157        { IDX_MIXER_MODEMOUT,           MIXER_MUTE_MASK|0x1f1f },
1158        { IDX_MIXER_BASSTREBLE,         0x0000 },
1159        { IDX_MIXER_PCBEEP,             MIXER_MUTE_MASK|0x1f1f },
1160        { IDX_MIXER_MODEMIN,            MIXER_MUTE_MASK|0x1f1f },
1161        { IDX_MIXER_MIC,                MIXER_MUTE_MASK|0x001f },
1162        { IDX_MIXER_LINEIN,             MIXER_MUTE_MASK|0x1f1f },
1163        { IDX_MIXER_CDAUDIO,            MIXER_MUTE_MASK|0x1f1f },
1164        { IDX_MIXER_VIDEO,              MIXER_MUTE_MASK|0x1f1f },
1165        { IDX_MIXER_AUX,                MIXER_MUTE_MASK|0x1f1f },
1166        { IDX_MIXER_WAVEOUT,            MIXER_MUTE_MASK|0x1f1f },
1167        { IDX_MIXER_FMSYNTH,            MIXER_MUTE_MASK|0x1f1f },
1168        { IDX_MIXER_REC_VOLUME,         MIXER_MUTE_MASK|0x0707 },
1169};
1170
1171static int
1172snd_azf3328_mixer_new(struct snd_azf3328 *chip)
1173{
1174        struct snd_card *card;
1175        const struct snd_kcontrol_new *sw;
1176        unsigned int idx;
1177        int err;
1178
1179        if (snd_BUG_ON(!chip || !chip->card))
1180                return -EINVAL;
1181
1182        card = chip->card;
1183
1184        /* mixer reset */
1185        snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
1186
1187        /* mute and zero volume channels */
1188        for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
1189                snd_azf3328_mixer_outw(chip,
1190                        snd_azf3328_init_values[idx][0],
1191                        snd_azf3328_init_values[idx][1]);
1192        }
1193
1194        /* add mixer controls */
1195        sw = snd_azf3328_mixer_controls;
1196        for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
1197                        ++idx, ++sw) {
1198                if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
1199                        return err;
1200        }
1201        snd_component_add(card, "AZF3328 mixer");
1202        strcpy(card->mixername, "AZF3328 mixer");
1203
1204        return 0;
1205}
1206#endif /* AZF_USE_AC97_LAYER */
1207
1208static int
1209snd_azf3328_hw_params(struct snd_pcm_substream *substream,
1210                                 struct snd_pcm_hw_params *hw_params)
1211{
1212        return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1213}
1214
1215static int
1216snd_azf3328_hw_free(struct snd_pcm_substream *substream)
1217{
1218        snd_pcm_lib_free_pages(substream);
1219        return 0;
1220}
1221
1222static void
1223snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec,
1224                               enum azf_freq_t bitrate,
1225                               unsigned int format_width,
1226                               unsigned int channels
1227)
1228{
1229        unsigned long flags;
1230        u16 val = 0xff00;
1231        u8 freq = 0;
1232
1233        switch (bitrate) {
1234        case AZF_FREQ_4000:  freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
1235        case AZF_FREQ_4800:  freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
1236        case AZF_FREQ_5512:
1237                /* the AZF3328 names it "5510" for some strange reason */
1238                             freq = SOUNDFORMAT_FREQ_5510; break;
1239        case AZF_FREQ_6620:  freq = SOUNDFORMAT_FREQ_6620; break;
1240        case AZF_FREQ_8000:  freq = SOUNDFORMAT_FREQ_8000; break;
1241        case AZF_FREQ_9600:  freq = SOUNDFORMAT_FREQ_9600; break;
1242        case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break;
1243        case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
1244        case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break;
1245        case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break;
1246        case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break;
1247        default:
1248                snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
1249                /* fall-through */
1250        case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break;
1251        case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break;
1252        case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
1253        }
1254        /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
1255        /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
1256        /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
1257        /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
1258        /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
1259        /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
1260        /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
1261        /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
1262        /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
1263
1264        val |= freq;
1265
1266        if (channels == 2)
1267                val |= SOUNDFORMAT_FLAG_2CHANNELS;
1268
1269        if (format_width == 16)
1270                val |= SOUNDFORMAT_FLAG_16BIT;
1271
1272        spin_lock_irqsave(codec->lock, flags);
1273
1274        /* set bitrate/format */
1275        snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
1276
1277        /* changing the bitrate/format settings switches off the
1278         * audio output with an annoying click in case of 8/16bit format change
1279         * (maybe shutting down DAC/ADC?), thus immediately
1280         * do some tweaking to reenable it and get rid of the clicking
1281         * (FIXME: yes, it works, but what exactly am I doing here?? :)
1282         * FIXME: does this have some side effects for full-duplex
1283         * or other dramatic side effects? */
1284        /* do it for non-capture codecs only */
1285        if (codec->type != AZF_CODEC_CAPTURE)
1286                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1287                        snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
1288                        DMA_RUN_SOMETHING1 |
1289                        DMA_RUN_SOMETHING2 |
1290                        SOMETHING_ALMOST_ALWAYS_SET |
1291                        DMA_EPILOGUE_SOMETHING |
1292                        DMA_SOMETHING_ELSE
1293                );
1294
1295        spin_unlock_irqrestore(codec->lock, flags);
1296}
1297
1298static inline void
1299snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec
1300)
1301{
1302        /* choose lowest frequency for low power consumption.
1303         * While this will cause louder noise due to rather coarse frequency,
1304         * it should never matter since output should always
1305         * get disabled properly when idle anyway. */
1306        snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1);
1307}
1308
1309static void
1310snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
1311                                        unsigned bitmask,
1312                                        bool enable
1313)
1314{
1315        bool do_mask = !enable;
1316        if (do_mask)
1317                chip->shadow_reg_ctrl_6AH |= bitmask;
1318        else
1319                chip->shadow_reg_ctrl_6AH &= ~bitmask;
1320        dev_dbg(chip->card->dev,
1321                "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
1322                bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
1323        snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
1324}
1325
1326static inline void
1327snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
1328{
1329        dev_dbg(chip->card->dev, "codec_enable %d\n", enable);
1330        /* no idea what exactly is being done here, but I strongly assume it's
1331         * PM related */
1332        snd_azf3328_ctrl_reg_6AH_update(
1333                chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
1334        );
1335}
1336
1337static void
1338snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1339                                enum snd_azf3328_codec_type codec_type,
1340                                bool enable
1341)
1342{
1343        struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1344        bool need_change = (codec->running != enable);
1345
1346        dev_dbg(chip->card->dev,
1347                "codec_activity: %s codec, enable %d, need_change %d\n",
1348                                codec->name, enable, need_change
1349        );
1350        if (need_change) {
1351                static const struct {
1352                        enum snd_azf3328_codec_type other1;
1353                        enum snd_azf3328_codec_type other2;
1354                } peer_codecs[3] =
1355                        { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
1356                          { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
1357                          { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
1358                bool call_function;
1359
1360                if (enable)
1361                        /* if enable codec, call enable_codecs func
1362                           to enable codec supply... */
1363                        call_function = 1;
1364                else {
1365                        /* ...otherwise call enable_codecs func
1366                           (which globally shuts down operation of codecs)
1367                           only in case the other codecs are currently
1368                           not active either! */
1369                        call_function =
1370                                ((!chip->codecs[peer_codecs[codec_type].other1]
1371                                        .running)
1372                             &&  (!chip->codecs[peer_codecs[codec_type].other2]
1373                                        .running));
1374                }
1375                if (call_function)
1376                        snd_azf3328_ctrl_enable_codecs(chip, enable);
1377
1378                /* ...and adjust clock, too
1379                 * (reduce noise and power consumption) */
1380                if (!enable)
1381                        snd_azf3328_codec_setfmt_lowpower(codec);
1382                codec->running = enable;
1383        }
1384}
1385
1386static void
1387snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
1388                          struct snd_azf3328_codec_data *codec,
1389                          unsigned long addr,
1390                          unsigned int period_bytes,
1391                          unsigned int buffer_bytes
1392)
1393{
1394        WARN_ONCE(period_bytes & 1, "odd period length!?\n");
1395        WARN_ONCE(buffer_bytes != 2 * period_bytes,
1396                 "missed our input expectations! %u vs. %u\n",
1397                 buffer_bytes, period_bytes);
1398        if (!codec->running) {
1399                /* AZF3328 uses a two buffer pointer DMA transfer approach */
1400
1401                unsigned long flags;
1402
1403                /* width 32bit (prevent overflow): */
1404                u32 area_length;
1405                struct codec_setup_io {
1406                        u32 dma_start_1;
1407                        u32 dma_start_2;
1408                        u32 dma_lengths;
1409                } __attribute__((packed)) setup_io;
1410
1411                area_length = buffer_bytes/2;
1412
1413                setup_io.dma_start_1 = addr;
1414                setup_io.dma_start_2 = addr+area_length;
1415
1416                dev_dbg(chip->card->dev,
1417                        "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n",
1418                                setup_io.dma_start_1, area_length,
1419                                setup_io.dma_start_2, area_length,
1420                                period_bytes, buffer_bytes);
1421
1422                /* Hmm, are we really supposed to decrement this by 1??
1423                   Most definitely certainly not: configuring full length does
1424                   work properly (i.e. likely better), and BTW we
1425                   violated possibly differing frame sizes with this...
1426
1427                area_length--; |* max. index *|
1428                */
1429
1430                /* build combined I/O buffer length word */
1431                setup_io.dma_lengths = (area_length << 16) | (area_length);
1432
1433                spin_lock_irqsave(codec->lock, flags);
1434                snd_azf3328_codec_outl_multi(
1435                        codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3
1436                );
1437                spin_unlock_irqrestore(codec->lock, flags);
1438        }
1439}
1440
1441static int
1442snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream)
1443{
1444        struct snd_pcm_runtime *runtime = substream->runtime;
1445        struct snd_azf3328_codec_data *codec = runtime->private_data;
1446#if 0
1447        unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1448        unsigned int count = snd_pcm_lib_period_bytes(substream);
1449#endif
1450
1451        codec->dma_base = runtime->dma_addr;
1452
1453#if 0
1454        snd_azf3328_codec_setfmt(codec,
1455                runtime->rate,
1456                snd_pcm_format_width(runtime->format),
1457                runtime->channels);
1458        snd_azf3328_codec_setdmaa(chip, codec,
1459                                        runtime->dma_addr, count, size);
1460#endif
1461        return 0;
1462}
1463
1464static int
1465snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1466{
1467        struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1468        struct snd_pcm_runtime *runtime = substream->runtime;
1469        struct snd_azf3328_codec_data *codec = runtime->private_data;
1470        int result = 0;
1471        u16 flags1;
1472        bool previously_muted = false;
1473        bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type);
1474
1475        switch (cmd) {
1476        case SNDRV_PCM_TRIGGER_START:
1477                dev_dbg(chip->card->dev, "START PCM %s\n", codec->name);
1478
1479                if (is_main_mixer_playback_codec) {
1480                        /* mute WaveOut (avoid clicking during setup) */
1481                        previously_muted =
1482                                snd_azf3328_mixer_mute_control_pcm(
1483                                                chip, 1
1484                                );
1485                }
1486
1487                snd_azf3328_codec_setfmt(codec,
1488                        runtime->rate,
1489                        snd_pcm_format_width(runtime->format),
1490                        runtime->channels);
1491
1492                spin_lock(codec->lock);
1493                /* first, remember current value: */
1494                flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1495
1496                /* stop transfer */
1497                flags1 &= ~DMA_RESUME;
1498                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1499
1500                /* FIXME: clear interrupts or what??? */
1501                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
1502                spin_unlock(codec->lock);
1503
1504                snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr,
1505                        snd_pcm_lib_period_bytes(substream),
1506                        snd_pcm_lib_buffer_bytes(substream)
1507                );
1508
1509                spin_lock(codec->lock);
1510#ifdef WIN9X
1511                /* FIXME: enable playback/recording??? */
1512                flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
1513                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1514
1515                /* start transfer again */
1516                /* FIXME: what is this value (0x0010)??? */
1517                flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1518                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1519#else /* NT4 */
1520                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1521                        0x0000);
1522                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1523                        DMA_RUN_SOMETHING1);
1524                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1525                        DMA_RUN_SOMETHING1 |
1526                        DMA_RUN_SOMETHING2);
1527                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1528                        DMA_RESUME |
1529                        SOMETHING_ALMOST_ALWAYS_SET |
1530                        DMA_EPILOGUE_SOMETHING |
1531                        DMA_SOMETHING_ELSE);
1532#endif
1533                spin_unlock(codec->lock);
1534                snd_azf3328_ctrl_codec_activity(chip, codec->type, 1);
1535
1536                if (is_main_mixer_playback_codec) {
1537                        /* now unmute WaveOut */
1538                        if (!previously_muted)
1539                                snd_azf3328_mixer_mute_control_pcm(
1540                                                chip, 0
1541                                );
1542                }
1543
1544                dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name);
1545                break;
1546        case SNDRV_PCM_TRIGGER_RESUME:
1547                dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name);
1548                /* resume codec if we were active */
1549                spin_lock(codec->lock);
1550                if (codec->running)
1551                        snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1552                                snd_azf3328_codec_inw(
1553                                        codec, IDX_IO_CODEC_DMA_FLAGS
1554                                ) | DMA_RESUME
1555                        );
1556                spin_unlock(codec->lock);
1557                break;
1558        case SNDRV_PCM_TRIGGER_STOP:
1559                dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name);
1560
1561                if (is_main_mixer_playback_codec) {
1562                        /* mute WaveOut (avoid clicking during setup) */
1563                        previously_muted =
1564                                snd_azf3328_mixer_mute_control_pcm(
1565                                                chip, 1
1566                                );
1567                }
1568
1569                spin_lock(codec->lock);
1570                /* first, remember current value: */
1571                flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1572
1573                /* stop transfer */
1574                flags1 &= ~DMA_RESUME;
1575                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1576
1577                /* hmm, is this really required? we're resetting the same bit
1578                 * immediately thereafter... */
1579                flags1 |= DMA_RUN_SOMETHING1;
1580                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1581
1582                flags1 &= ~DMA_RUN_SOMETHING1;
1583                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1584                spin_unlock(codec->lock);
1585                snd_azf3328_ctrl_codec_activity(chip, codec->type, 0);
1586
1587                if (is_main_mixer_playback_codec) {
1588                        /* now unmute WaveOut */
1589                        if (!previously_muted)
1590                                snd_azf3328_mixer_mute_control_pcm(
1591                                                chip, 0
1592                                );
1593                }
1594
1595                dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name);
1596                break;
1597        case SNDRV_PCM_TRIGGER_SUSPEND:
1598                dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name);
1599                /* make sure codec is stopped */
1600                snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1601                        snd_azf3328_codec_inw(
1602                                codec, IDX_IO_CODEC_DMA_FLAGS
1603                        ) & ~DMA_RESUME
1604                );
1605                break;
1606        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1607                WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1608                break;
1609        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1610                WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1611                break;
1612        default:
1613                WARN(1, "FIXME: unknown trigger mode!\n");
1614                return -EINVAL;
1615        }
1616
1617        return result;
1618}
1619
1620static snd_pcm_uframes_t
1621snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream
1622)
1623{
1624        const struct snd_azf3328_codec_data *codec =
1625                substream->runtime->private_data;
1626        unsigned long result;
1627        snd_pcm_uframes_t frmres;
1628
1629        result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
1630
1631        /* calculate offset */
1632#ifdef QUERY_HARDWARE
1633        result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
1634#else
1635        result -= codec->dma_base;
1636#endif
1637        frmres = bytes_to_frames( substream->runtime, result);
1638        dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n",
1639                jiffies, codec->name, result, frmres);
1640        return frmres;
1641}
1642
1643/******************************************************************/
1644
1645#ifdef SUPPORT_GAMEPORT
1646static inline void
1647snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1648                                bool enable
1649)
1650{
1651        snd_azf3328_io_reg_setb(
1652                chip->game_io+IDX_GAME_HWCONFIG,
1653                GAME_HWCFG_IRQ_ENABLE,
1654                enable
1655        );
1656}
1657
1658static inline void
1659snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1660                                           bool enable
1661)
1662{
1663        snd_azf3328_io_reg_setb(
1664                chip->game_io+IDX_GAME_HWCONFIG,
1665                GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1666                enable
1667        );
1668}
1669
1670static void
1671snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1672                                           unsigned int freq_cfg
1673)
1674{
1675        snd_azf3328_io_reg_setb(
1676                chip->game_io+IDX_GAME_HWCONFIG,
1677                0x02,
1678                (freq_cfg & 1) != 0
1679        );
1680        snd_azf3328_io_reg_setb(
1681                chip->game_io+IDX_GAME_HWCONFIG,
1682                0x04,
1683                (freq_cfg & 2) != 0
1684        );
1685}
1686
1687static inline void
1688snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
1689{
1690        snd_azf3328_ctrl_reg_6AH_update(
1691                chip, IO_6A_SOMETHING2_GAMEPORT, enable
1692        );
1693}
1694
1695static inline void
1696snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1697{
1698        /*
1699         * skeleton handler only
1700         * (we do not want axis reading in interrupt handler - too much load!)
1701         */
1702        dev_dbg(chip->card->dev, "gameport irq\n");
1703
1704         /* this should ACK the gameport IRQ properly, hopefully. */
1705        snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1706}
1707
1708static int
1709snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1710{
1711        struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1712        int res;
1713
1714        dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode);
1715        switch (mode) {
1716        case GAMEPORT_MODE_COOKED:
1717        case GAMEPORT_MODE_RAW:
1718                res = 0;
1719                break;
1720        default:
1721                res = -1;
1722                break;
1723        }
1724
1725        snd_azf3328_gameport_set_counter_frequency(chip,
1726                                GAME_HWCFG_ADC_COUNTER_FREQ_STD);
1727        snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1728
1729        return res;
1730}
1731
1732static void
1733snd_azf3328_gameport_close(struct gameport *gameport)
1734{
1735        struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1736
1737        dev_dbg(chip->card->dev, "gameport_close\n");
1738        snd_azf3328_gameport_set_counter_frequency(chip,
1739                                GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1740        snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1741}
1742
1743static int
1744snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1745                                 int *axes,
1746                                 int *buttons
1747)
1748{
1749        struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1750        int i;
1751        u8 val;
1752        unsigned long flags;
1753
1754        if (snd_BUG_ON(!chip))
1755                return 0;
1756
1757        spin_lock_irqsave(&chip->reg_lock, flags);
1758        val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1759        *buttons = (~(val) >> 4) & 0xf;
1760
1761        /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
1762         * thus we're atomic and cannot actively wait in here
1763         * (which would be useful for us since it probably would be better
1764         * to trigger a measurement in here, then wait a short amount of
1765         * time until it's finished, then read values of _this_ measurement).
1766         *
1767         * Thus we simply resort to reading values if they're available already
1768         * and trigger the next measurement.
1769         */
1770
1771        val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1772        if (val & GAME_AXES_SAMPLING_READY) {
1773                for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
1774                        /* configure the axis to read */
1775                        val = (i << 4) | 0x0f;
1776                        snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1777
1778                        chip->axes[i] = snd_azf3328_game_inw(
1779                                                chip, IDX_GAME_AXIS_VALUE
1780                                        );
1781                }
1782        }
1783
1784        /* trigger next sampling of axes, to be evaluated the next time we
1785         * enter this function */
1786
1787        /* for some very, very strange reason we cannot enable
1788         * Measurement Ready monitoring for all axes here,
1789         * at least not when only one joystick connected */
1790        val = 0x03; /* we're able to monitor axes 1 and 2 only */
1791        snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1792
1793        snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1794        spin_unlock_irqrestore(&chip->reg_lock, flags);
1795
1796        for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
1797                axes[i] = chip->axes[i];
1798                if (axes[i] == 0xffff)
1799                        axes[i] = -1;
1800        }
1801
1802        dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n",
1803                axes[0], axes[1], axes[2], axes[3], *buttons);
1804
1805        return 0;
1806}
1807
1808static int
1809snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1810{
1811        struct gameport *gp;
1812
1813        chip->gameport = gp = gameport_allocate_port();
1814        if (!gp) {
1815                dev_err(chip->card->dev, "cannot alloc memory for gameport\n");
1816                return -ENOMEM;
1817        }
1818
1819        gameport_set_name(gp, "AZF3328 Gameport");
1820        gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1821        gameport_set_dev_parent(gp, &chip->pci->dev);
1822        gp->io = chip->game_io;
1823        gameport_set_port_data(gp, chip);
1824
1825        gp->open = snd_azf3328_gameport_open;
1826        gp->close = snd_azf3328_gameport_close;
1827        gp->fuzz = 16; /* seems ok */
1828        gp->cooked_read = snd_azf3328_gameport_cooked_read;
1829
1830        /* DISABLE legacy address: we don't need it! */
1831        snd_azf3328_gameport_legacy_address_enable(chip, 0);
1832
1833        snd_azf3328_gameport_set_counter_frequency(chip,
1834                                GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1835        snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1836
1837        gameport_register_port(chip->gameport);
1838
1839        return 0;
1840}
1841
1842static void
1843snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1844{
1845        if (chip->gameport) {
1846                gameport_unregister_port(chip->gameport);
1847                chip->gameport = NULL;
1848        }
1849        snd_azf3328_gameport_irq_enable(chip, 0);
1850}
1851#else
1852static inline int
1853snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1854static inline void
1855snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1856static inline void
1857snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1858{
1859        dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n");
1860}
1861#endif /* SUPPORT_GAMEPORT */
1862
1863/******************************************************************/
1864
1865static inline void
1866snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which)
1867{
1868        dev_dbg(chip->card->dev,
1869                "unknown IRQ type (%x) occurred, please report!\n",
1870                which);
1871}
1872
1873static inline void
1874snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip,
1875                          const struct snd_azf3328_codec_data *first_codec,
1876                          u8 status
1877)
1878{
1879        u8 which;
1880        enum snd_azf3328_codec_type codec_type;
1881        const struct snd_azf3328_codec_data *codec = first_codec;
1882
1883        for (codec_type = AZF_CODEC_PLAYBACK;
1884                 codec_type <= AZF_CODEC_I2S_OUT;
1885                         ++codec_type, ++codec) {
1886
1887                /* skip codec if there's no interrupt for it */
1888                if (!(status & (1 << codec_type)))
1889                        continue;
1890
1891                spin_lock(codec->lock);
1892                which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
1893                /* ack all IRQ types immediately */
1894                snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
1895                spin_unlock(codec->lock);
1896
1897                if (codec->substream) {
1898                        snd_pcm_period_elapsed(codec->substream);
1899                        dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n",
1900                                codec->name,
1901                                which,
1902                                snd_azf3328_codec_inl(
1903                                        codec, IDX_IO_CODEC_DMA_CURRPOS));
1904                } else
1905                        dev_warn(chip->card->dev, "irq handler problem!\n");
1906                if (which & IRQ_SOMETHING)
1907                        snd_azf3328_irq_log_unknown_type(chip, which);
1908        }
1909}
1910
1911static irqreturn_t
1912snd_azf3328_interrupt(int irq, void *dev_id)
1913{
1914        struct snd_azf3328 *chip = dev_id;
1915        u8 status;
1916        static unsigned long irq_count;
1917
1918        status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1919
1920        /* fast path out, to ease interrupt sharing */
1921        if (!(status &
1922                (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
1923                |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
1924        ))
1925                return IRQ_NONE; /* must be interrupt for another device */
1926
1927        dev_dbg(chip->card->dev,
1928                "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
1929                        irq_count++ /* debug-only */,
1930                        status);
1931
1932        if (status & IRQ_TIMER) {
1933                /* dev_dbg(chip->card->dev, "timer %ld\n",
1934                        snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1935                                & TIMER_VALUE_MASK
1936                ); */
1937                if (chip->timer)
1938                        snd_timer_interrupt(chip->timer, chip->timer->sticks);
1939                /* ACK timer */
1940                spin_lock(&chip->reg_lock);
1941                snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
1942                spin_unlock(&chip->reg_lock);
1943                dev_dbg(chip->card->dev, "timer IRQ\n");
1944        }
1945
1946        if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
1947                snd_azf3328_pcm_interrupt(chip, chip->codecs, status);
1948
1949        if (status & IRQ_GAMEPORT)
1950                snd_azf3328_gameport_interrupt(chip);
1951
1952        /* MPU401 has less critical IRQ requirements
1953         * than timer and playback/recording, right? */
1954        if (status & IRQ_MPU401) {
1955                snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1956
1957                /* hmm, do we have to ack the IRQ here somehow?
1958                 * If so, then I don't know how yet... */
1959                dev_dbg(chip->card->dev, "MPU401 IRQ\n");
1960        }
1961        return IRQ_HANDLED;
1962}
1963
1964/*****************************************************************/
1965
1966/* as long as we think we have identical snd_pcm_hardware parameters
1967   for playback, capture and i2s out, we can use the same physical struct
1968   since the struct is simply being copied into a member.
1969*/
1970static const struct snd_pcm_hardware snd_azf3328_hardware =
1971{
1972        /* FIXME!! Correct? */
1973        .info =                 SNDRV_PCM_INFO_MMAP |
1974                                SNDRV_PCM_INFO_INTERLEAVED |
1975                                SNDRV_PCM_INFO_MMAP_VALID,
1976        .formats =              SNDRV_PCM_FMTBIT_S8 |
1977                                SNDRV_PCM_FMTBIT_U8 |
1978                                SNDRV_PCM_FMTBIT_S16_LE |
1979                                SNDRV_PCM_FMTBIT_U16_LE,
1980        .rates =                SNDRV_PCM_RATE_5512 |
1981                                SNDRV_PCM_RATE_8000_48000 |
1982                                SNDRV_PCM_RATE_KNOT,
1983        .rate_min =             AZF_FREQ_4000,
1984        .rate_max =             AZF_FREQ_66200,
1985        .channels_min =         1,
1986        .channels_max =         2,
1987        .buffer_bytes_max =     (64*1024),
1988        .period_bytes_min =     1024,
1989        .period_bytes_max =     (32*1024),
1990        /* We simply have two DMA areas (instead of a list of descriptors
1991           such as other cards); I believe that this is a fixed hardware
1992           attribute and there isn't much driver magic to be done to expand it.
1993           Thus indicate that we have at least and at most 2 periods. */
1994        .periods_min =          2,
1995        .periods_max =          2,
1996        /* FIXME: maybe that card actually has a FIFO?
1997         * Hmm, it seems newer revisions do have one, but we still don't know
1998         * its size... */
1999        .fifo_size =            0,
2000};
2001
2002
2003static const unsigned int snd_azf3328_fixed_rates[] = {
2004        AZF_FREQ_4000,
2005        AZF_FREQ_4800,
2006        AZF_FREQ_5512,
2007        AZF_FREQ_6620,
2008        AZF_FREQ_8000,
2009        AZF_FREQ_9600,
2010        AZF_FREQ_11025,
2011        AZF_FREQ_13240,
2012        AZF_FREQ_16000,
2013        AZF_FREQ_22050,
2014        AZF_FREQ_32000,
2015        AZF_FREQ_44100,
2016        AZF_FREQ_48000,
2017        AZF_FREQ_66200
2018};
2019
2020static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
2021        .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
2022        .list = snd_azf3328_fixed_rates,
2023        .mask = 0,
2024};
2025
2026/*****************************************************************/
2027
2028static int
2029snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
2030                     enum snd_azf3328_codec_type codec_type
2031)
2032{
2033        struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
2034        struct snd_pcm_runtime *runtime = substream->runtime;
2035        struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
2036
2037        codec->substream = substream;
2038
2039        /* same parameters for all our codecs - at least we think so... */
2040        runtime->hw = snd_azf3328_hardware;
2041
2042        snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
2043                                   &snd_azf3328_hw_constraints_rates);
2044        runtime->private_data = codec;
2045        return 0;
2046}
2047
2048static int
2049snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream)
2050{
2051        return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
2052}
2053
2054static int
2055snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream)
2056{
2057        return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
2058}
2059
2060static int
2061snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream)
2062{
2063        return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
2064}
2065
2066static int
2067snd_azf3328_pcm_close(struct snd_pcm_substream *substream
2068)
2069{
2070        struct snd_azf3328_codec_data *codec =
2071                substream->runtime->private_data;
2072
2073        codec->substream = NULL;
2074        return 0;
2075}
2076
2077/******************************************************************/
2078
2079static const struct snd_pcm_ops snd_azf3328_playback_ops = {
2080        .open =         snd_azf3328_pcm_playback_open,
2081        .close =        snd_azf3328_pcm_close,
2082        .ioctl =        snd_pcm_lib_ioctl,
2083        .hw_params =    snd_azf3328_hw_params,
2084        .hw_free =      snd_azf3328_hw_free,
2085        .prepare =      snd_azf3328_pcm_prepare,
2086        .trigger =      snd_azf3328_pcm_trigger,
2087        .pointer =      snd_azf3328_pcm_pointer
2088};
2089
2090static const struct snd_pcm_ops snd_azf3328_capture_ops = {
2091        .open =         snd_azf3328_pcm_capture_open,
2092        .close =        snd_azf3328_pcm_close,
2093        .ioctl =        snd_pcm_lib_ioctl,
2094        .hw_params =    snd_azf3328_hw_params,
2095        .hw_free =      snd_azf3328_hw_free,
2096        .prepare =      snd_azf3328_pcm_prepare,
2097        .trigger =      snd_azf3328_pcm_trigger,
2098        .pointer =      snd_azf3328_pcm_pointer
2099};
2100
2101static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
2102        .open =         snd_azf3328_pcm_i2s_out_open,
2103        .close =        snd_azf3328_pcm_close,
2104        .ioctl =        snd_pcm_lib_ioctl,
2105        .hw_params =    snd_azf3328_hw_params,
2106        .hw_free =      snd_azf3328_hw_free,
2107        .prepare =      snd_azf3328_pcm_prepare,
2108        .trigger =      snd_azf3328_pcm_trigger,
2109        .pointer =      snd_azf3328_pcm_pointer
2110};
2111
2112static int
2113snd_azf3328_pcm(struct snd_azf3328 *chip)
2114{
2115        /* pcm devices */
2116        enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS };
2117
2118        struct snd_pcm *pcm;
2119        int err;
2120
2121        err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
2122                                                                1, 1, &pcm);
2123        if (err < 0)
2124                return err;
2125        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
2126                                                &snd_azf3328_playback_ops);
2127        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
2128                                                &snd_azf3328_capture_ops);
2129
2130        pcm->private_data = chip;
2131        pcm->info_flags = 0;
2132        strcpy(pcm->name, chip->card->shortname);
2133        /* same pcm object for playback/capture (see snd_pcm_new() above) */
2134        chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
2135        chip->pcm[AZF_CODEC_CAPTURE] = pcm;
2136
2137        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2138                                              &chip->pci->dev,
2139                                              64*1024, 64*1024);
2140
2141        err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
2142                                                                1, 0, &pcm);
2143        if (err < 0)
2144                return err;
2145        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
2146                                                &snd_azf3328_i2s_out_ops);
2147
2148        pcm->private_data = chip;
2149        pcm->info_flags = 0;
2150        strcpy(pcm->name, chip->card->shortname);
2151        chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
2152
2153        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
2154                                              &chip->pci->dev,
2155                                              64*1024, 64*1024);
2156
2157        return 0;
2158}
2159
2160/******************************************************************/
2161
2162/*** NOTE: the physical timer resolution actually is 1024000 ticks per second
2163 *** (probably derived from main crystal via a divider of 24),
2164 *** but announcing those attributes to user-space would make programs
2165 *** configure the timer to a 1 tick value, resulting in an absolutely fatal
2166 *** timer IRQ storm.
2167 *** Thus I chose to announce a down-scaled virtual timer to the outside and
2168 *** calculate real timer countdown values internally.
2169 *** (the scale factor can be set via module parameter "seqtimer_scaling").
2170 ***/
2171
2172static int
2173snd_azf3328_timer_start(struct snd_timer *timer)
2174{
2175        struct snd_azf3328 *chip;
2176        unsigned long flags;
2177        unsigned int delay;
2178
2179        chip = snd_timer_chip(timer);
2180        delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
2181        if (delay < 49) {
2182                /* uhoh, that's not good, since user-space won't know about
2183                 * this timing tweak
2184                 * (we need to do it to avoid a lockup, though) */
2185
2186                dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay);
2187                delay = 49; /* minimum time is 49 ticks */
2188        }
2189        dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay);
2190        delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
2191        spin_lock_irqsave(&chip->reg_lock, flags);
2192        snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
2193        spin_unlock_irqrestore(&chip->reg_lock, flags);
2194        return 0;
2195}
2196
2197static int
2198snd_azf3328_timer_stop(struct snd_timer *timer)
2199{
2200        struct snd_azf3328 *chip;
2201        unsigned long flags;
2202
2203        chip = snd_timer_chip(timer);
2204        spin_lock_irqsave(&chip->reg_lock, flags);
2205        /* disable timer countdown and interrupt */
2206        /* Hmm, should we write TIMER_IRQ_ACK here?
2207           YES indeed, otherwise a rogue timer operation - which prompts
2208           ALSA(?) to call repeated stop() in vain, but NOT start() -
2209           will never end (value 0x03 is kept shown in control byte).
2210           Simply manually poking 0x04 _once_ immediately successfully stops
2211           the hardware/ALSA interrupt activity. */
2212        snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
2213        spin_unlock_irqrestore(&chip->reg_lock, flags);
2214        return 0;
2215}
2216
2217
2218static int
2219snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
2220                                               unsigned long *num, unsigned long *den)
2221{
2222        *num = 1;
2223        *den = 1024000 / seqtimer_scaling;
2224        return 0;
2225}
2226
2227static struct snd_timer_hardware snd_azf3328_timer_hw = {
2228        .flags = SNDRV_TIMER_HW_AUTO,
2229        .resolution = 977, /* 1000000/1024000 = 0.9765625us */
2230        .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
2231        .start = snd_azf3328_timer_start,
2232        .stop = snd_azf3328_timer_stop,
2233        .precise_resolution = snd_azf3328_timer_precise_resolution,
2234};
2235
2236static int
2237snd_azf3328_timer(struct snd_azf3328 *chip, int device)
2238{
2239        struct snd_timer *timer = NULL;
2240        struct snd_timer_id tid;
2241        int err;
2242
2243        tid.dev_class = SNDRV_TIMER_CLASS_CARD;
2244        tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
2245        tid.card = chip->card->number;
2246        tid.device = device;
2247        tid.subdevice = 0;
2248
2249        snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
2250        snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
2251
2252        err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
2253        if (err < 0)
2254                goto out;
2255
2256        strcpy(timer->name, "AZF3328 timer");
2257        timer->private_data = chip;
2258        timer->hw = snd_azf3328_timer_hw;
2259
2260        chip->timer = timer;
2261
2262        snd_azf3328_timer_stop(timer);
2263
2264        err = 0;
2265
2266out:
2267        return err;
2268}
2269
2270/******************************************************************/
2271
2272static int
2273snd_azf3328_free(struct snd_azf3328 *chip)
2274{
2275        if (chip->irq < 0)
2276                goto __end_hw;
2277
2278        snd_azf3328_mixer_reset(chip);
2279
2280        snd_azf3328_timer_stop(chip->timer);
2281        snd_azf3328_gameport_free(chip);
2282
2283__end_hw:
2284        if (chip->irq >= 0)
2285                free_irq(chip->irq, chip);
2286        pci_release_regions(chip->pci);
2287        pci_disable_device(chip->pci);
2288
2289        kfree(chip);
2290        return 0;
2291}
2292
2293static int
2294snd_azf3328_dev_free(struct snd_device *device)
2295{
2296        struct snd_azf3328 *chip = device->device_data;
2297        return snd_azf3328_free(chip);
2298}
2299
2300#if 0
2301/* check whether a bit can be modified */
2302static void
2303snd_azf3328_test_bit(unsigned unsigned reg, int bit)
2304{
2305        unsigned char val, valoff, valon;
2306
2307        val = inb(reg);
2308
2309        outb(val & ~(1 << bit), reg);
2310        valoff = inb(reg);
2311
2312        outb(val|(1 << bit), reg);
2313        valon = inb(reg);
2314
2315        outb(val, reg);
2316
2317        printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
2318                                reg, bit, val, valoff, valon
2319        );
2320}
2321#endif
2322
2323static inline void
2324snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2325{
2326        u16 tmp;
2327
2328        dev_dbg(chip->card->dev,
2329                "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
2330                "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
2331                chip->ctrl_io, chip->game_io, chip->mpu_io,
2332                chip->opl3_io, chip->mixer_io, chip->irq);
2333
2334        dev_dbg(chip->card->dev,
2335                "game %02x %02x %02x %02x %02x %02x\n",
2336                snd_azf3328_game_inb(chip, 0),
2337                snd_azf3328_game_inb(chip, 1),
2338                snd_azf3328_game_inb(chip, 2),
2339                snd_azf3328_game_inb(chip, 3),
2340                snd_azf3328_game_inb(chip, 4),
2341                snd_azf3328_game_inb(chip, 5));
2342
2343        for (tmp = 0; tmp < 0x07; tmp += 1)
2344                dev_dbg(chip->card->dev,
2345                        "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2346
2347        for (tmp = 0; tmp <= 0x07; tmp += 1)
2348                dev_dbg(chip->card->dev,
2349                        "0x%02x: game200 0x%04x, game208 0x%04x\n",
2350                        tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2351
2352        for (tmp = 0; tmp <= 0x01; tmp += 1)
2353                dev_dbg(chip->card->dev,
2354                        "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2355                        "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2356                                tmp,
2357                                inb(0x300 + tmp),
2358                                inb(0x310 + tmp),
2359                                inb(0x320 + tmp),
2360                                inb(0x330 + tmp),
2361                                inb(0x388 + tmp),
2362                                inb(0x38c + tmp));
2363
2364        for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
2365                dev_dbg(chip->card->dev,
2366                        "ctrl 0x%02x: 0x%04x\n",
2367                        tmp, snd_azf3328_ctrl_inw(chip, tmp));
2368
2369        for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
2370                dev_dbg(chip->card->dev,
2371                        "mixer 0x%02x: 0x%04x\n",
2372                        tmp, snd_azf3328_mixer_inw(chip, tmp));
2373}
2374
2375static int
2376snd_azf3328_create(struct snd_card *card,
2377                   struct pci_dev *pci,
2378                   unsigned long device_type,
2379                   struct snd_azf3328 **rchip)
2380{
2381        struct snd_azf3328 *chip;
2382        int err;
2383        static struct snd_device_ops ops = {
2384                .dev_free =     snd_azf3328_dev_free,
2385        };
2386        u8 dma_init;
2387        enum snd_azf3328_codec_type codec_type;
2388        struct snd_azf3328_codec_data *codec_setup;
2389
2390        *rchip = NULL;
2391
2392        err = pci_enable_device(pci);
2393        if (err < 0)
2394                return err;
2395
2396        chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2397        if (chip == NULL) {
2398                err = -ENOMEM;
2399                goto out_err;
2400        }
2401        spin_lock_init(&chip->reg_lock);
2402        chip->card = card;
2403        chip->pci = pci;
2404        chip->irq = -1;
2405
2406        /* check if we can restrict PCI DMA transfers to 24 bits */
2407        if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
2408            dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
2409                dev_err(card->dev,
2410                        "architecture does not support 24bit PCI busmaster DMA\n"
2411                );
2412                err = -ENXIO;
2413                goto out_err;
2414        }
2415
2416        err = pci_request_regions(pci, "Aztech AZF3328");
2417        if (err < 0)
2418                goto out_err;
2419
2420        chip->ctrl_io  = pci_resource_start(pci, 0);
2421        chip->game_io  = pci_resource_start(pci, 1);
2422        chip->mpu_io   = pci_resource_start(pci, 2);
2423        chip->opl3_io  = pci_resource_start(pci, 3);
2424        chip->mixer_io = pci_resource_start(pci, 4);
2425
2426        codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
2427        codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2428        codec_setup->lock = &chip->reg_lock;
2429        codec_setup->type = AZF_CODEC_PLAYBACK;
2430        codec_setup->name = "PLAYBACK";
2431
2432        codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
2433        codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2434        codec_setup->lock = &chip->reg_lock;
2435        codec_setup->type = AZF_CODEC_CAPTURE;
2436        codec_setup->name = "CAPTURE";
2437
2438        codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
2439        codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2440        codec_setup->lock = &chip->reg_lock;
2441        codec_setup->type = AZF_CODEC_I2S_OUT;
2442        codec_setup->name = "I2S_OUT";
2443
2444        if (request_irq(pci->irq, snd_azf3328_interrupt,
2445                        IRQF_SHARED, KBUILD_MODNAME, chip)) {
2446                dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2447                err = -EBUSY;
2448                goto out_err;
2449        }
2450        chip->irq = pci->irq;
2451        pci_set_master(pci);
2452        synchronize_irq(chip->irq);
2453
2454        snd_azf3328_debug_show_ports(chip);
2455
2456        err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2457        if (err < 0)
2458                goto out_err;
2459
2460        /* create mixer interface & switches */
2461        err = snd_azf3328_mixer_new(chip);
2462        if (err < 0)
2463                goto out_err;
2464
2465        /* standard codec init stuff */
2466                /* default DMA init value */
2467        dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2468
2469        for (codec_type = AZF_CODEC_PLAYBACK;
2470                codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
2471                struct snd_azf3328_codec_data *codec =
2472                         &chip->codecs[codec_type];
2473
2474                /* shutdown codecs to reduce power / noise */
2475                        /* have ...ctrl_codec_activity() act properly */
2476                codec->running = 1;
2477                snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
2478
2479                spin_lock_irq(codec->lock);
2480                snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
2481                                                 dma_init);
2482                spin_unlock_irq(codec->lock);
2483        }
2484
2485        *rchip = chip;
2486
2487        err = 0;
2488        goto out;
2489
2490out_err:
2491        if (chip)
2492                snd_azf3328_free(chip);
2493        pci_disable_device(pci);
2494
2495out:
2496        return err;
2497}
2498
2499static int
2500snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2501{
2502        static int dev;
2503        struct snd_card *card;
2504        struct snd_azf3328 *chip;
2505        struct snd_opl3 *opl3;
2506        int err;
2507
2508        if (dev >= SNDRV_CARDS) {
2509                err = -ENODEV;
2510                goto out;
2511        }
2512        if (!enable[dev]) {
2513                dev++;
2514                err = -ENOENT;
2515                goto out;
2516        }
2517
2518        err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2519                           0, &card);
2520        if (err < 0)
2521                goto out;
2522
2523        strcpy(card->driver, "AZF3328");
2524        strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
2525
2526        err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2527        if (err < 0)
2528                goto out_err;
2529
2530        card->private_data = chip;
2531
2532        /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
2533           since our hardware ought to be similar, thus use same ID. */
2534        err = snd_mpu401_uart_new(
2535                card, 0,
2536                MPU401_HW_AZT2320, chip->mpu_io,
2537                MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
2538                -1, &chip->rmidi
2539        );
2540        if (err < 0) {
2541                dev_err(card->dev, "no MPU-401 device at 0x%lx?\n",
2542                                chip->mpu_io
2543                );
2544                goto out_err;
2545        }
2546
2547        err = snd_azf3328_timer(chip, 0);
2548        if (err < 0)
2549                goto out_err;
2550
2551        err = snd_azf3328_pcm(chip);
2552        if (err < 0)
2553                goto out_err;
2554
2555        if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
2556                            OPL3_HW_AUTO, 1, &opl3) < 0) {
2557                dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n",
2558                           chip->opl3_io, chip->opl3_io+2
2559                );
2560        } else {
2561                /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
2562                err = snd_opl3_timer_new(opl3, 1, 2);
2563                if (err < 0)
2564                        goto out_err;
2565                err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2566                if (err < 0)
2567                        goto out_err;
2568                opl3->private_data = chip;
2569        }
2570
2571        sprintf(card->longname, "%s at 0x%lx, irq %i",
2572                card->shortname, chip->ctrl_io, chip->irq);
2573
2574        err = snd_card_register(card);
2575        if (err < 0)
2576                goto out_err;
2577
2578#ifdef MODULE
2579        dev_info(card->dev,
2580                 "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n");
2581        dev_info(card->dev,
2582                 "Hardware was completely undocumented, unfortunately.\n");
2583        dev_info(card->dev,
2584                 "Feel free to contact andi AT lisas.de for bug reports etc.!\n");
2585        dev_info(card->dev,
2586                 "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2587                 1024000 / seqtimer_scaling, seqtimer_scaling);
2588#endif
2589
2590        snd_azf3328_gameport(chip, dev);
2591
2592        pci_set_drvdata(pci, card);
2593        dev++;
2594
2595        err = 0;
2596        goto out;
2597
2598out_err:
2599        dev_err(card->dev, "something failed, exiting\n");
2600        snd_card_free(card);
2601
2602out:
2603        return err;
2604}
2605
2606static void
2607snd_azf3328_remove(struct pci_dev *pci)
2608{
2609        snd_card_free(pci_get_drvdata(pci));
2610}
2611
2612#ifdef CONFIG_PM_SLEEP
2613static inline void
2614snd_azf3328_suspend_regs(const struct snd_azf3328 *chip,
2615                         unsigned long io_addr, unsigned count, u32 *saved_regs)
2616{
2617        unsigned reg;
2618
2619        for (reg = 0; reg < count; ++reg) {
2620                *saved_regs = inl(io_addr);
2621                dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n",
2622                        io_addr, *saved_regs);
2623                ++saved_regs;
2624                io_addr += sizeof(*saved_regs);
2625        }
2626}
2627
2628static inline void
2629snd_azf3328_resume_regs(const struct snd_azf3328 *chip,
2630                        const u32 *saved_regs,
2631                        unsigned long io_addr,
2632                        unsigned count
2633)
2634{
2635        unsigned reg;
2636
2637        for (reg = 0; reg < count; ++reg) {
2638                outl(*saved_regs, io_addr);
2639                dev_dbg(chip->card->dev,
2640                        "resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
2641                        io_addr, *saved_regs, inl(io_addr));
2642                ++saved_regs;
2643                io_addr += sizeof(*saved_regs);
2644        }
2645}
2646
2647static inline void
2648snd_azf3328_suspend_ac97(struct snd_azf3328 *chip)
2649{
2650#ifdef AZF_USE_AC97_LAYER
2651        snd_ac97_suspend(chip->ac97);
2652#else
2653        snd_azf3328_suspend_regs(chip, chip->mixer_io,
2654                ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
2655
2656        /* make sure to disable master volume etc. to prevent looping sound */
2657        snd_azf3328_mixer_mute_control_master(chip, 1);
2658        snd_azf3328_mixer_mute_control_pcm(chip, 1);
2659#endif /* AZF_USE_AC97_LAYER */
2660}
2661
2662static inline void
2663snd_azf3328_resume_ac97(const struct snd_azf3328 *chip)
2664{
2665#ifdef AZF_USE_AC97_LAYER
2666        snd_ac97_resume(chip->ac97);
2667#else
2668        snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io,
2669                                        ARRAY_SIZE(chip->saved_regs_mixer));
2670
2671        /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
2672           and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
2673           resulting in a mixer reset condition persisting until _after_
2674           master vol was restored. Thus master vol needs an extra restore. */
2675        outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2676#endif /* AZF_USE_AC97_LAYER */
2677}
2678
2679static int
2680snd_azf3328_suspend(struct device *dev)
2681{
2682        struct snd_card *card = dev_get_drvdata(dev);
2683        struct snd_azf3328 *chip = card->private_data;
2684        u16 *saved_regs_ctrl_u16;
2685
2686        snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2687
2688        snd_azf3328_suspend_ac97(chip);
2689
2690        snd_azf3328_suspend_regs(chip, chip->ctrl_io,
2691                ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
2692
2693        /* manually store the one currently relevant write-only reg, too */
2694        saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2695        saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
2696
2697        snd_azf3328_suspend_regs(chip, chip->game_io,
2698                ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
2699        snd_azf3328_suspend_regs(chip, chip->mpu_io,
2700                ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
2701        snd_azf3328_suspend_regs(chip, chip->opl3_io,
2702                ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
2703        return 0;
2704}
2705
2706static int
2707snd_azf3328_resume(struct device *dev)
2708{
2709        struct snd_card *card = dev_get_drvdata(dev);
2710        const struct snd_azf3328 *chip = card->private_data;
2711
2712        snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io,
2713                                        ARRAY_SIZE(chip->saved_regs_game));
2714        snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io,
2715                                        ARRAY_SIZE(chip->saved_regs_mpu));
2716        snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io,
2717                                        ARRAY_SIZE(chip->saved_regs_opl3));
2718
2719        snd_azf3328_resume_ac97(chip);
2720
2721        snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io,
2722                                        ARRAY_SIZE(chip->saved_regs_ctrl));
2723
2724        snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2725        return 0;
2726}
2727
2728static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume);
2729#define SND_AZF3328_PM_OPS      &snd_azf3328_pm
2730#else
2731#define SND_AZF3328_PM_OPS      NULL
2732#endif /* CONFIG_PM_SLEEP */
2733
2734static struct pci_driver azf3328_driver = {
2735        .name = KBUILD_MODNAME,
2736        .id_table = snd_azf3328_ids,
2737        .probe = snd_azf3328_probe,
2738        .remove = snd_azf3328_remove,
2739        .driver = {
2740                .pm = SND_AZF3328_PM_OPS,
2741        },
2742};
2743
2744module_pci_driver(azf3328_driver);
2745