LXR linux/sound/soc/sof/intel/hda.h

   1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
   2/*
   3 * This file is provided under a dual BSD/GPLv2 license.  When using or
   4 * redistributing this file, you may do so under either license.
   5 *
   6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
   7 *
   8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
   9 */
  10
  11#ifndef __SOF_INTEL_HDA_H
  12#define __SOF_INTEL_HDA_H
  13
  14#include <sound/hda_codec.h>
  15#include <sound/hdaudio_ext.h>
  16#include "shim.h"
  17
  18/* PCI registers */
  19#define PCI_TCSEL                       0x44
  20#define PCI_PGCTL                       PCI_TCSEL
  21#define PCI_CGCTL                       0x48
  22
  23/* PCI_PGCTL bits */
  24#define PCI_PGCTL_ADSPPGD               BIT(2)
  25#define PCI_PGCTL_LSRMD_MASK            BIT(4)
  26
  27/* PCI_CGCTL bits */
  28#define PCI_CGCTL_MISCBDCGE_MASK        BIT(6)
  29#define PCI_CGCTL_ADSPDCGE              BIT(1)
  30
  31/* Legacy HDA registers and bits used - widths are variable */
  32#define SOF_HDA_GCAP                    0x0
  33#define SOF_HDA_GCTL                    0x8
  34/* accept unsol. response enable */
  35#define SOF_HDA_GCTL_UNSOL              BIT(8)
  36#define SOF_HDA_LLCH                    0x14
  37#define SOF_HDA_INTCTL                  0x20
  38#define SOF_HDA_INTSTS                  0x24
  39#define SOF_HDA_WAKESTS                 0x0E
  40#define SOF_HDA_WAKESTS_INT_MASK        ((1 << 8) - 1)
  41#define SOF_HDA_RIRBSTS                 0x5d
  42
  43/* SOF_HDA_GCTL register bist */
  44#define SOF_HDA_GCTL_RESET              BIT(0)
  45
  46/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
  47#define SOF_HDA_INT_GLOBAL_EN           BIT(31)
  48#define SOF_HDA_INT_CTRL_EN             BIT(30)
  49#define SOF_HDA_INT_ALL_STREAM          0xff
  50
  51#define SOF_HDA_MAX_CAPS                10
  52#define SOF_HDA_CAP_ID_OFF              16
  53#define SOF_HDA_CAP_ID_MASK             GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
  54                                                SOF_HDA_CAP_ID_OFF)
  55#define SOF_HDA_CAP_NEXT_MASK           0xFFFF
  56
  57#define SOF_HDA_GTS_CAP_ID                      0x1
  58#define SOF_HDA_ML_CAP_ID                       0x2
  59
  60#define SOF_HDA_PP_CAP_ID               0x3
  61#define SOF_HDA_REG_PP_PPCH             0x10
  62#define SOF_HDA_REG_PP_PPCTL            0x04
  63#define SOF_HDA_REG_PP_PPSTS            0x08
  64#define SOF_HDA_PPCTL_PIE               BIT(31)
  65#define SOF_HDA_PPCTL_GPROCEN           BIT(30)
  66
  67/*Vendor Specific Registers*/
  68#define SOF_HDA_VS_D0I3C                0x104A
  69
  70/* D0I3C Register fields */
  71#define SOF_HDA_VS_D0I3C_CIP            BIT(0) /* Command-In-Progress */
  72#define SOF_HDA_VS_D0I3C_I3             BIT(2) /* D0i3 enable bit */
  73
  74/* DPIB entry size: 8 Bytes = 2 DWords */
  75#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
  76
  77#define SOF_HDA_SPIB_CAP_ID             0x4
  78#define SOF_HDA_DRSM_CAP_ID             0x5
  79
  80#define SOF_HDA_SPIB_BASE               0x08
  81#define SOF_HDA_SPIB_INTERVAL           0x08
  82#define SOF_HDA_SPIB_SPIB               0x00
  83#define SOF_HDA_SPIB_MAXFIFO            0x04
  84
  85#define SOF_HDA_PPHC_BASE               0x10
  86#define SOF_HDA_PPHC_INTERVAL           0x10
  87
  88#define SOF_HDA_PPLC_BASE               0x10
  89#define SOF_HDA_PPLC_MULTI              0x10
  90#define SOF_HDA_PPLC_INTERVAL           0x10
  91
  92#define SOF_HDA_DRSM_BASE               0x08
  93#define SOF_HDA_DRSM_INTERVAL           0x08
  94
  95/* Descriptor error interrupt */
  96#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR          0x10
  97
  98/* FIFO error interrupt */
  99#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR          0x08
 100
 101/* Buffer completion interrupt */
 102#define SOF_HDA_CL_DMA_SD_INT_COMPLETE          0x04
 103
 104#define SOF_HDA_CL_DMA_SD_INT_MASK \
 105        (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
 106        SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
 107        SOF_HDA_CL_DMA_SD_INT_COMPLETE)
 108#define SOF_HDA_SD_CTL_DMA_START                0x02 /* Stream DMA start bit */
 109
 110/* Intel HD Audio Code Loader DMA Registers */
 111#define SOF_HDA_ADSP_LOADER_BASE                0x80
 112#define SOF_HDA_ADSP_DPLBASE                    0x70
 113#define SOF_HDA_ADSP_DPUBASE                    0x74
 114#define SOF_HDA_ADSP_DPLBASE_ENABLE             0x01
 115
 116/* Stream Registers */
 117#define SOF_HDA_ADSP_REG_CL_SD_CTL              0x00
 118#define SOF_HDA_ADSP_REG_CL_SD_STS              0x03
 119#define SOF_HDA_ADSP_REG_CL_SD_LPIB             0x04
 120#define SOF_HDA_ADSP_REG_CL_SD_CBL              0x08
 121#define SOF_HDA_ADSP_REG_CL_SD_LVI              0x0C
 122#define SOF_HDA_ADSP_REG_CL_SD_FIFOW            0x0E
 123#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE         0x10
 124#define SOF_HDA_ADSP_REG_CL_SD_FORMAT           0x12
 125#define SOF_HDA_ADSP_REG_CL_SD_FIFOL            0x14
 126#define SOF_HDA_ADSP_REG_CL_SD_BDLPL            0x18
 127#define SOF_HDA_ADSP_REG_CL_SD_BDLPU            0x1C
 128#define SOF_HDA_ADSP_SD_ENTRY_SIZE              0x20
 129
 130/* CL: Software Position Based FIFO Capability Registers */
 131#define SOF_DSP_REG_CL_SPBFIFO \
 132        (SOF_HDA_ADSP_LOADER_BASE + 0x20)
 133#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH      0x0
 134#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL    0x4
 135#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB        0x8
 136#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS    0xc
 137
 138/* Stream Number */
 139#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT      20
 140#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
 141        GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
 142                SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
 143
 144#define HDA_DSP_HDA_BAR                         0
 145#define HDA_DSP_PP_BAR                          1
 146#define HDA_DSP_SPIB_BAR                        2
 147#define HDA_DSP_DRSM_BAR                        3
 148#define HDA_DSP_BAR                             4
 149
 150#define SRAM_WINDOW_OFFSET(x)                   (0x80000 + (x) * 0x20000)
 151
 152#define HDA_DSP_MBOX_OFFSET                     SRAM_WINDOW_OFFSET(0)
 153
 154#define HDA_DSP_PANIC_OFFSET(x) \
 155        (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
 156
 157/* SRAM window 0 FW "registers" */
 158#define HDA_DSP_SRAM_REG_ROM_STATUS             (HDA_DSP_MBOX_OFFSET + 0x0)
 159#define HDA_DSP_SRAM_REG_ROM_ERROR              (HDA_DSP_MBOX_OFFSET + 0x4)
 160/* FW and ROM share offset 4 */
 161#define HDA_DSP_SRAM_REG_FW_STATUS              (HDA_DSP_MBOX_OFFSET + 0x4)
 162#define HDA_DSP_SRAM_REG_FW_TRACEP              (HDA_DSP_MBOX_OFFSET + 0x8)
 163#define HDA_DSP_SRAM_REG_FW_END                 (HDA_DSP_MBOX_OFFSET + 0xc)
 164
 165#define HDA_DSP_MBOX_UPLINK_OFFSET              0x81000
 166
 167#define HDA_DSP_STREAM_RESET_TIMEOUT            300
 168/*
 169 * Timeout in us, for setting the stream RUN bit, during
 170 * start/stop the stream. The timeout expires if new RUN bit
 171 * value cannot be read back within the specified time.
 172 */
 173#define HDA_DSP_STREAM_RUN_TIMEOUT              300
 174#define HDA_DSP_CL_TRIGGER_TIMEOUT              300
 175
 176#define HDA_DSP_SPIB_ENABLE                     1
 177#define HDA_DSP_SPIB_DISABLE                    0
 178
 179#define SOF_HDA_MAX_BUFFER_SIZE                 (32 * PAGE_SIZE)
 180
 181#define HDA_DSP_STACK_DUMP_SIZE                 32
 182
 183/* ROM  status/error values */
 184#define HDA_DSP_ROM_STS_MASK                    GENMASK(23, 0)
 185#define HDA_DSP_ROM_INIT                        0x1
 186#define HDA_DSP_ROM_FW_MANIFEST_LOADED          0x3
 187#define HDA_DSP_ROM_FW_FW_LOADED                0x4
 188#define HDA_DSP_ROM_FW_ENTERED                  0x5
 189#define HDA_DSP_ROM_RFW_START                   0xf
 190#define HDA_DSP_ROM_CSE_ERROR                   40
 191#define HDA_DSP_ROM_CSE_WRONG_RESPONSE          41
 192#define HDA_DSP_ROM_IMR_TO_SMALL                42
 193#define HDA_DSP_ROM_BASE_FW_NOT_FOUND           43
 194#define HDA_DSP_ROM_CSE_VALIDATION_FAILED       44
 195#define HDA_DSP_ROM_IPC_FATAL_ERROR             45
 196#define HDA_DSP_ROM_L2_CACHE_ERROR              46
 197#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL        47
 198#define HDA_DSP_ROM_API_PTR_INVALID             50
 199#define HDA_DSP_ROM_BASEFW_INCOMPAT             51
 200#define HDA_DSP_ROM_UNHANDLED_INTERRUPT         0xBEE00000
 201#define HDA_DSP_ROM_MEMORY_HOLE_ECC             0xECC00000
 202#define HDA_DSP_ROM_KERNEL_EXCEPTION            0xCAFE0000
 203#define HDA_DSP_ROM_USER_EXCEPTION              0xBEEF0000
 204#define HDA_DSP_ROM_UNEXPECTED_RESET            0xDECAF000
 205#define HDA_DSP_ROM_NULL_FW_ENTRY               0x4c4c4e55
 206#define HDA_DSP_IPC_PURGE_FW                    0x01004000
 207
 208/* various timeout values */
 209#define HDA_DSP_PU_TIMEOUT              50
 210#define HDA_DSP_PD_TIMEOUT              50
 211#define HDA_DSP_RESET_TIMEOUT_US        50000
 212#define HDA_DSP_BASEFW_TIMEOUT_US       3000000
 213#define HDA_DSP_INIT_TIMEOUT_US 500000
 214#define HDA_DSP_CTRL_RESET_TIMEOUT              100
 215#define HDA_DSP_WAIT_TIMEOUT            500     /* 500 msec */
 216#define HDA_DSP_REG_POLL_INTERVAL_US            500     /* 0.5 msec */
 217#define HDA_DSP_REG_POLL_RETRY_COUNT            50
 218
 219#define HDA_DSP_ADSPIC_IPC                      1
 220#define HDA_DSP_ADSPIS_IPC                      1
 221
 222/* Intel HD Audio General DSP Registers */
 223#define HDA_DSP_GEN_BASE                0x0
 224#define HDA_DSP_REG_ADSPCS              (HDA_DSP_GEN_BASE + 0x04)
 225#define HDA_DSP_REG_ADSPIC              (HDA_DSP_GEN_BASE + 0x08)
 226#define HDA_DSP_REG_ADSPIS              (HDA_DSP_GEN_BASE + 0x0C)
 227#define HDA_DSP_REG_ADSPIC2             (HDA_DSP_GEN_BASE + 0x10)
 228#define HDA_DSP_REG_ADSPIS2             (HDA_DSP_GEN_BASE + 0x14)
 229
 230/* Intel HD Audio Inter-Processor Communication Registers */
 231#define HDA_DSP_IPC_BASE                0x40
 232#define HDA_DSP_REG_HIPCT               (HDA_DSP_IPC_BASE + 0x00)
 233#define HDA_DSP_REG_HIPCTE              (HDA_DSP_IPC_BASE + 0x04)
 234#define HDA_DSP_REG_HIPCI               (HDA_DSP_IPC_BASE + 0x08)
 235#define HDA_DSP_REG_HIPCIE              (HDA_DSP_IPC_BASE + 0x0C)
 236#define HDA_DSP_REG_HIPCCTL             (HDA_DSP_IPC_BASE + 0x10)
 237
 238/* Intel Vendor Specific Registers */
 239#define HDA_VS_INTEL_EM2                0x1030
 240#define HDA_VS_INTEL_EM2_L1SEN          BIT(13)
 241
 242/*  HIPCI */
 243#define HDA_DSP_REG_HIPCI_BUSY          BIT(31)
 244#define HDA_DSP_REG_HIPCI_MSG_MASK      0x7FFFFFFF
 245
 246/* HIPCIE */
 247#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
 248#define HDA_DSP_REG_HIPCIE_MSG_MASK     0x3FFFFFFF
 249
 250/* HIPCCTL */
 251#define HDA_DSP_REG_HIPCCTL_DONE        BIT(1)
 252#define HDA_DSP_REG_HIPCCTL_BUSY        BIT(0)
 253
 254/* HIPCT */
 255#define HDA_DSP_REG_HIPCT_BUSY          BIT(31)
 256#define HDA_DSP_REG_HIPCT_MSG_MASK      0x7FFFFFFF
 257
 258/* HIPCTE */
 259#define HDA_DSP_REG_HIPCTE_MSG_MASK     0x3FFFFFFF
 260
 261#define HDA_DSP_ADSPIC_CL_DMA           0x2
 262#define HDA_DSP_ADSPIS_CL_DMA           0x2
 263
 264/* Delay before scheduling D0i3 entry */
 265#define BXT_D0I3_DELAY 5000
 266
 267#define FW_CL_STREAM_NUMBER             0x1
 268
 269/* ADSPCS - Audio DSP Control & Status */
 270
 271/*
 272 * Core Reset - asserted high
 273 * CRST Mask for a given core mask pattern, cm
 274 */
 275#define HDA_DSP_ADSPCS_CRST_SHIFT       0
 276#define HDA_DSP_ADSPCS_CRST_MASK(cm)    ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
 277
 278/*
 279 * Core run/stall - when set to '1' core is stalled
 280 * CSTALL Mask for a given core mask pattern, cm
 281 */
 282#define HDA_DSP_ADSPCS_CSTALL_SHIFT     8
 283#define HDA_DSP_ADSPCS_CSTALL_MASK(cm)  ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
 284
 285/*
 286 * Set Power Active - when set to '1' turn cores on
 287 * SPA Mask for a given core mask pattern, cm
 288 */
 289#define HDA_DSP_ADSPCS_SPA_SHIFT        16
 290#define HDA_DSP_ADSPCS_SPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
 291
 292/*
 293 * Current Power Active - power status of cores, set by hardware
 294 * CPA Mask for a given core mask pattern, cm
 295 */
 296#define HDA_DSP_ADSPCS_CPA_SHIFT        24
 297#define HDA_DSP_ADSPCS_CPA_MASK(cm)     ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
 298
 299/* Mask for a given core index, c = 0.. number of supported cores - 1 */
 300#define HDA_DSP_CORE_MASK(c)            BIT(c)
 301
 302/*
 303 * Mask for a given number of cores
 304 * nc = number of supported cores
 305 */
 306#define SOF_DSP_CORES_MASK(nc)  GENMASK(((nc) - 1), 0)
 307
 308/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
 309#define CNL_DSP_IPC_BASE                0xc0
 310#define CNL_DSP_REG_HIPCTDR             (CNL_DSP_IPC_BASE + 0x00)
 311#define CNL_DSP_REG_HIPCTDA             (CNL_DSP_IPC_BASE + 0x04)
 312#define CNL_DSP_REG_HIPCTDD             (CNL_DSP_IPC_BASE + 0x08)
 313#define CNL_DSP_REG_HIPCIDR             (CNL_DSP_IPC_BASE + 0x10)
 314#define CNL_DSP_REG_HIPCIDA             (CNL_DSP_IPC_BASE + 0x14)
 315#define CNL_DSP_REG_HIPCIDD             (CNL_DSP_IPC_BASE + 0x18)
 316#define CNL_DSP_REG_HIPCCTL             (CNL_DSP_IPC_BASE + 0x28)
 317
 318/*  HIPCI */
 319#define CNL_DSP_REG_HIPCIDR_BUSY                BIT(31)
 320#define CNL_DSP_REG_HIPCIDR_MSG_MASK    0x7FFFFFFF
 321
 322/* HIPCIE */
 323#define CNL_DSP_REG_HIPCIDA_DONE        BIT(31)
 324#define CNL_DSP_REG_HIPCIDA_MSG_MASK    0x7FFFFFFF
 325
 326/* HIPCCTL */
 327#define CNL_DSP_REG_HIPCCTL_DONE        BIT(1)
 328#define CNL_DSP_REG_HIPCCTL_BUSY        BIT(0)
 329
 330/* HIPCT */
 331#define CNL_DSP_REG_HIPCTDR_BUSY                BIT(31)
 332#define CNL_DSP_REG_HIPCTDR_MSG_MASK    0x7FFFFFFF
 333
 334/* HIPCTDA */
 335#define CNL_DSP_REG_HIPCTDA_DONE        BIT(31)
 336#define CNL_DSP_REG_HIPCTDA_MSG_MASK    0x7FFFFFFF
 337
 338/* HIPCTDD */
 339#define CNL_DSP_REG_HIPCTDD_MSG_MASK    0x7FFFFFFF
 340
 341/* BDL */
 342#define HDA_DSP_BDL_SIZE                        4096
 343#define HDA_DSP_MAX_BDL_ENTRIES                 \
 344        (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
 345
 346/* Number of DAIs */
 347#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 348#define SOF_SKL_NUM_DAIS                14
 349#else
 350#define SOF_SKL_NUM_DAIS                8
 351#endif
 352
 353/* Intel HD Audio SRAM Window 0*/
 354#define HDA_ADSP_SRAM0_BASE_SKL         0x8000
 355
 356/* Firmware status window */
 357#define HDA_ADSP_FW_STATUS_SKL          HDA_ADSP_SRAM0_BASE_SKL
 358#define HDA_ADSP_ERROR_CODE_SKL         (HDA_ADSP_FW_STATUS_SKL + 0x4)
 359
 360/* Host Device Memory Space */
 361#define APL_SSP_BASE_OFFSET     0x2000
 362#define CNL_SSP_BASE_OFFSET     0x10000
 363
 364/* Host Device Memory Size of a Single SSP */
 365#define SSP_DEV_MEM_SIZE        0x1000
 366
 367/* SSP Count of the Platform */
 368#define APL_SSP_COUNT           6
 369#define CNL_SSP_COUNT           3
 370#define ICL_SSP_COUNT           6
 371
 372/* SSP Registers */
 373#define SSP_SSC1_OFFSET         0x4
 374#define SSP_SET_SCLK_SLAVE      BIT(25)
 375#define SSP_SET_SFRM_SLAVE      BIT(24)
 376#define SSP_SET_SLAVE           (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
 377
 378#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
 379
 380struct sof_intel_dsp_bdl {
 381        __le32 addr_l;
 382        __le32 addr_h;
 383        __le32 size;
 384        __le32 ioc;
 385} __attribute((packed));
 386
 387#define SOF_HDA_PLAYBACK_STREAMS        16
 388#define SOF_HDA_CAPTURE_STREAMS         16
 389#define SOF_HDA_PLAYBACK                0
 390#define SOF_HDA_CAPTURE                 1
 391
 392/* represents DSP HDA controller frontend - i.e. host facing control */
 393struct sof_intel_hda_dev {
 394
 395        struct hda_bus hbus;
 396
 397        /* hw config */
 398        const struct sof_intel_dsp_desc *desc;
 399
 400        /* trace */
 401        struct hdac_ext_stream *dtrace_stream;
 402
 403        /* if position update IPC needed */
 404        u32 no_ipc_position;
 405
 406        /* the maximum number of streams (playback + capture) supported */
 407        u32 stream_max;
 408
 409        int irq;
 410
 411        /* PM related */
 412        bool l1_support_changed;/* during suspend, is L1SEN changed or not */
 413
 414        /* DMIC device */
 415        struct platform_device *dmic_dev;
 416};
 417
 418static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
 419{
 420        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 421
 422        return &hda->hbus.core;
 423}
 424
 425static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
 426{
 427        struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
 428
 429        return &hda->hbus;
 430}
 431
 432struct sof_intel_hda_stream {
 433        struct snd_sof_dev *sdev;
 434        struct hdac_ext_stream hda_stream;
 435        struct sof_intel_stream stream;
 436        int host_reserved; /* reserve host DMA channel */
 437};
 438
 439#define hstream_to_sof_hda_stream(hstream) \
 440        container_of(hstream, struct sof_intel_hda_stream, hda_stream)
 441
 442#define bus_to_sof_hda(bus) \
 443        container_of(bus, struct sof_intel_hda_dev, hbus.core)
 444
 445#define SOF_STREAM_SD_OFFSET(s) \
 446        (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
 447         + SOF_HDA_ADSP_LOADER_BASE)
 448
 449/*
 450 * DSP Core services.
 451 */
 452int hda_dsp_probe(struct snd_sof_dev *sdev);
 453int hda_dsp_remove(struct snd_sof_dev *sdev);
 454int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
 455                             unsigned int core_mask);
 456int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
 457                             unsigned int core_mask);
 458int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
 459int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
 460int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
 461int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
 462int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
 463bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
 464                             unsigned int core_mask);
 465int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
 466                                  unsigned int core_mask);
 467void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
 468void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
 469
 470int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
 471                            enum sof_d0_substate d0_substate);
 472
 473int hda_dsp_suspend(struct snd_sof_dev *sdev);
 474int hda_dsp_resume(struct snd_sof_dev *sdev);
 475int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
 476int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
 477int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
 478int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
 479void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
 480void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
 481void hda_ipc_dump(struct snd_sof_dev *sdev);
 482void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
 483
 484/*
 485 * DSP PCM Operations.
 486 */
 487int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
 488                     struct snd_pcm_substream *substream);
 489int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
 490                      struct snd_pcm_substream *substream);
 491int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
 492                          struct snd_pcm_substream *substream,
 493                          struct snd_pcm_hw_params *params,
 494                          struct sof_ipc_stream_params *ipc_params);
 495int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
 496                           struct snd_pcm_substream *substream);
 497int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
 498                        struct snd_pcm_substream *substream, int cmd);
 499snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
 500                                      struct snd_pcm_substream *substream);
 501
 502/*
 503 * DSP Stream Operations.
 504 */
 505
 506int hda_dsp_stream_init(struct snd_sof_dev *sdev);
 507void hda_dsp_stream_free(struct snd_sof_dev *sdev);
 508int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
 509                             struct hdac_ext_stream *stream,
 510                             struct snd_dma_buffer *dmab,
 511                             struct snd_pcm_hw_params *params);
 512int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
 513                           struct hdac_ext_stream *stream, int cmd);
 514irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
 515irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
 516int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
 517                             struct snd_dma_buffer *dmab,
 518                             struct hdac_stream *stream);
 519
 520struct hdac_ext_stream *
 521        hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
 522int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
 523int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
 524                               struct hdac_ext_stream *stream,
 525                               int enable, u32 size);
 526
 527void hda_ipc_msg_data(struct snd_sof_dev *sdev,
 528                      struct snd_pcm_substream *substream,
 529                      void *p, size_t sz);
 530int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
 531                       struct snd_pcm_substream *substream,
 532                       const struct sof_ipc_pcm_params_reply *reply);
 533
 534/*
 535 * DSP IPC Operations.
 536 */
 537int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
 538                         struct snd_sof_ipc_msg *msg);
 539void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
 540int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
 541int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
 542
 543irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
 544irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
 545int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
 546
 547/*
 548 * DSP Code loader.
 549 */
 550int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
 551int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
 552
 553/* pre and post fw run ops */
 554int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
 555int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
 556
 557/*
 558 * HDA Controller Operations.
 559 */
 560int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
 561void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
 562void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
 563int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
 564void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
 565int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
 566int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
 567void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
 568/*
 569 * HDA bus operations.
 570 */
 571void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
 572
 573#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
 574/*
 575 * HDA Codec operations.
 576 */
 577int hda_codec_probe_bus(struct snd_sof_dev *sdev);
 578void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
 579void hda_codec_jack_check(struct snd_sof_dev *sdev);
 580
 581#endif /* CONFIG_SND_SOC_SOF_HDA */
 582
 583#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && \
 584        (IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) || \
 585         IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
 586
 587void hda_codec_i915_get(struct snd_sof_dev *sdev);
 588void hda_codec_i915_put(struct snd_sof_dev *sdev);
 589int hda_codec_i915_init(struct snd_sof_dev *sdev);
 590int hda_codec_i915_exit(struct snd_sof_dev *sdev);
 591
 592#else
 593
 594static inline void hda_codec_i915_get(struct snd_sof_dev *sdev)  { }
 595static inline void hda_codec_i915_put(struct snd_sof_dev *sdev)  { }
 596static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
 597static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
 598
 599#endif
 600
 601/*
 602 * Trace Control.
 603 */
 604int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
 605int hda_dsp_trace_release(struct snd_sof_dev *sdev);
 606int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
 607
 608/* common dai driver */
 609extern struct snd_soc_dai_driver skl_dai[];
 610
 611/*
 612 * Platform Specific HW abstraction Ops.
 613 */
 614extern const struct snd_sof_dsp_ops sof_apl_ops;
 615extern const struct snd_sof_dsp_ops sof_cnl_ops;
 616
 617extern const struct sof_intel_dsp_desc apl_chip_info;
 618extern const struct sof_intel_dsp_desc cnl_chip_info;
 619extern const struct sof_intel_dsp_desc skl_chip_info;
 620extern const struct sof_intel_dsp_desc icl_chip_info;
 621extern const struct sof_intel_dsp_desc tgl_chip_info;
 622extern const struct sof_intel_dsp_desc ehl_chip_info;
 623extern const struct sof_intel_dsp_desc jsl_chip_info;
 624
 625#endif
 626