linux/arch/arm/include/asm/kvm_hyp.h
<<
>>
Prefs
   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2015 - ARM Ltd
   4 * Author: Marc Zyngier <marc.zyngier@arm.com>
   5 */
   6
   7#ifndef __ARM_KVM_HYP_H__
   8#define __ARM_KVM_HYP_H__
   9
  10#include <linux/compiler.h>
  11#include <linux/kvm_host.h>
  12#include <asm/cp15.h>
  13#include <asm/kvm_arm.h>
  14#include <asm/vfp.h>
  15
  16#define __hyp_text __section(.hyp.text) notrace
  17
  18#define __ACCESS_VFP(CRn)                       \
  19        "mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
  20
  21#define write_special(v, r)                                     \
  22        asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
  23#define read_special(r) ({                                      \
  24        u32 __val;                                              \
  25        asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
  26        __val;                                                  \
  27})
  28
  29#define TTBR0           __ACCESS_CP15_64(0, c2)
  30#define TTBR1           __ACCESS_CP15_64(1, c2)
  31#define VTTBR           __ACCESS_CP15_64(6, c2)
  32#define PAR             __ACCESS_CP15_64(0, c7)
  33#define CNTP_CVAL       __ACCESS_CP15_64(2, c14)
  34#define CNTV_CVAL       __ACCESS_CP15_64(3, c14)
  35#define CNTVOFF         __ACCESS_CP15_64(4, c14)
  36
  37#define MIDR            __ACCESS_CP15(c0, 0, c0, 0)
  38#define CSSELR          __ACCESS_CP15(c0, 2, c0, 0)
  39#define VPIDR           __ACCESS_CP15(c0, 4, c0, 0)
  40#define VMPIDR          __ACCESS_CP15(c0, 4, c0, 5)
  41#define SCTLR           __ACCESS_CP15(c1, 0, c0, 0)
  42#define CPACR           __ACCESS_CP15(c1, 0, c0, 2)
  43#define HCR             __ACCESS_CP15(c1, 4, c1, 0)
  44#define HDCR            __ACCESS_CP15(c1, 4, c1, 1)
  45#define HCPTR           __ACCESS_CP15(c1, 4, c1, 2)
  46#define HSTR            __ACCESS_CP15(c1, 4, c1, 3)
  47#define TTBCR           __ACCESS_CP15(c2, 0, c0, 2)
  48#define HTCR            __ACCESS_CP15(c2, 4, c0, 2)
  49#define VTCR            __ACCESS_CP15(c2, 4, c1, 2)
  50#define DACR            __ACCESS_CP15(c3, 0, c0, 0)
  51#define DFSR            __ACCESS_CP15(c5, 0, c0, 0)
  52#define IFSR            __ACCESS_CP15(c5, 0, c0, 1)
  53#define ADFSR           __ACCESS_CP15(c5, 0, c1, 0)
  54#define AIFSR           __ACCESS_CP15(c5, 0, c1, 1)
  55#define HSR             __ACCESS_CP15(c5, 4, c2, 0)
  56#define DFAR            __ACCESS_CP15(c6, 0, c0, 0)
  57#define IFAR            __ACCESS_CP15(c6, 0, c0, 2)
  58#define HDFAR           __ACCESS_CP15(c6, 4, c0, 0)
  59#define HIFAR           __ACCESS_CP15(c6, 4, c0, 2)
  60#define HPFAR           __ACCESS_CP15(c6, 4, c0, 4)
  61#define ICIALLUIS       __ACCESS_CP15(c7, 0, c1, 0)
  62#define BPIALLIS        __ACCESS_CP15(c7, 0, c1, 6)
  63#define ICIMVAU         __ACCESS_CP15(c7, 0, c5, 1)
  64#define ATS1CPR         __ACCESS_CP15(c7, 0, c8, 0)
  65#define TLBIALLIS       __ACCESS_CP15(c8, 0, c3, 0)
  66#define TLBIALL         __ACCESS_CP15(c8, 0, c7, 0)
  67#define TLBIALLNSNHIS   __ACCESS_CP15(c8, 4, c3, 4)
  68#define PRRR            __ACCESS_CP15(c10, 0, c2, 0)
  69#define NMRR            __ACCESS_CP15(c10, 0, c2, 1)
  70#define AMAIR0          __ACCESS_CP15(c10, 0, c3, 0)
  71#define AMAIR1          __ACCESS_CP15(c10, 0, c3, 1)
  72#define VBAR            __ACCESS_CP15(c12, 0, c0, 0)
  73#define CID             __ACCESS_CP15(c13, 0, c0, 1)
  74#define TID_URW         __ACCESS_CP15(c13, 0, c0, 2)
  75#define TID_URO         __ACCESS_CP15(c13, 0, c0, 3)
  76#define TID_PRIV        __ACCESS_CP15(c13, 0, c0, 4)
  77#define HTPIDR          __ACCESS_CP15(c13, 4, c0, 2)
  78#define CNTKCTL         __ACCESS_CP15(c14, 0, c1, 0)
  79#define CNTP_CTL        __ACCESS_CP15(c14, 0, c2, 1)
  80#define CNTV_CTL        __ACCESS_CP15(c14, 0, c3, 1)
  81#define CNTHCTL         __ACCESS_CP15(c14, 4, c1, 0)
  82
  83#define VFP_FPEXC       __ACCESS_VFP(FPEXC)
  84
  85/* AArch64 compatibility macros, only for the timer so far */
  86#define read_sysreg_el0(r)              read_sysreg(r##_EL0)
  87#define write_sysreg_el0(v, r)          write_sysreg(v, r##_EL0)
  88
  89#define SYS_CNTP_CTL_EL0                CNTP_CTL
  90#define SYS_CNTP_CVAL_EL0               CNTP_CVAL
  91#define SYS_CNTV_CTL_EL0                CNTV_CTL
  92#define SYS_CNTV_CVAL_EL0               CNTV_CVAL
  93
  94#define cntvoff_el2                     CNTVOFF
  95#define cnthctl_el2                     CNTHCTL
  96
  97void __timer_enable_traps(struct kvm_vcpu *vcpu);
  98void __timer_disable_traps(struct kvm_vcpu *vcpu);
  99
 100void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
 101void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
 102
 103void __sysreg_save_state(struct kvm_cpu_context *ctxt);
 104void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
 105
 106void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
 107void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
 108void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
 109void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
 110void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
 111void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
 112
 113asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
 114asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
 115static inline bool __vfp_enabled(void)
 116{
 117        return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10)));
 118}
 119
 120void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt);
 121void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt);
 122
 123asmlinkage int __guest_enter(struct kvm_vcpu *vcpu,
 124                             struct kvm_cpu_context *host);
 125asmlinkage int __hyp_do_panic(const char *, int, u32);
 126
 127#endif /* __ARM_KVM_HYP_H__ */
 128