LXR linux/arch/mips/pistachio/init.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Pistachio platform setup
   4 *
   5 * Copyright (C) 2014 Google, Inc.
   6 * Copyright (C) 2016 Imagination Technologies
   7 */
   8
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/of_address.h>
  13#include <linux/of_fdt.h>
  14
  15#include <asm/cacheflush.h>
  16#include <asm/dma-coherence.h>
  17#include <asm/fw/fw.h>
  18#include <asm/mips-boards/generic.h>
  19#include <asm/mips-cps.h>
  20#include <asm/prom.h>
  21#include <asm/smp-ops.h>
  22#include <asm/traps.h>
  23
  24/*
  25 * Core revision register decoding
  26 * Bits 23 to 20: Major rev
  27 * Bits 15 to 8: Minor rev
  28 * Bits 7 to 0: Maintenance rev
  29 */
  30#define PISTACHIO_CORE_REV_REG  0xB81483D0
  31#define PISTACHIO_CORE_REV_A1   0x00100006
  32#define PISTACHIO_CORE_REV_B0   0x00100106
  33
  34const char *get_system_type(void)
  35{
  36        u32 core_rev;
  37        const char *sys_type;
  38
  39        core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
  40
  41        switch (core_rev) {
  42        case PISTACHIO_CORE_REV_B0:
  43                sys_type = "IMG Pistachio SoC (B0)";
  44                break;
  45
  46        case PISTACHIO_CORE_REV_A1:
  47                sys_type = "IMG Pistachio SoC (A1)";
  48                break;
  49
  50        default:
  51                sys_type = "IMG Pistachio SoC";
  52                break;
  53        }
  54
  55        return sys_type;
  56}
  57
  58void __init *plat_get_fdt(void)
  59{
  60        if (fw_arg0 != -2)
  61                panic("Device-tree not present");
  62        return (void *)fw_arg1;
  63}
  64
  65void __init plat_mem_setup(void)
  66{
  67        __dt_setup_arch(plat_get_fdt());
  68}
  69
  70#define DEFAULT_CPC_BASE_ADDR   0x1bde0000
  71#define DEFAULT_CDMM_BASE_ADDR  0x1bdd0000
  72
  73phys_addr_t mips_cpc_default_phys_base(void)
  74{
  75        return DEFAULT_CPC_BASE_ADDR;
  76}
  77
  78phys_addr_t mips_cdmm_phys_base(void)
  79{
  80        return DEFAULT_CDMM_BASE_ADDR;
  81}
  82
  83static void __init mips_nmi_setup(void)
  84{
  85        void *base;
  86        extern char except_vec_nmi;
  87
  88        base = cpu_has_veic ?
  89                (void *)(CAC_BASE + 0xa80) :
  90                (void *)(CAC_BASE + 0x380);
  91        memcpy(base, &except_vec_nmi, 0x80);
  92        flush_icache_range((unsigned long)base,
  93                           (unsigned long)base + 0x80);
  94}
  95
  96static void __init mips_ejtag_setup(void)
  97{
  98        void *base;
  99        extern char except_vec_ejtag_debug;
 100
 101        base = cpu_has_veic ?
 102                (void *)(CAC_BASE + 0xa00) :
 103                (void *)(CAC_BASE + 0x300);
 104        memcpy(base, &except_vec_ejtag_debug, 0x80);
 105        flush_icache_range((unsigned long)base,
 106                           (unsigned long)base + 0x80);
 107}
 108
 109void __init prom_init(void)
 110{
 111        board_nmi_handler_setup = mips_nmi_setup;
 112        board_ejtag_handler_setup = mips_ejtag_setup;
 113
 114        mips_cm_probe();
 115        mips_cpc_probe();
 116        register_cps_smp_ops();
 117
 118        pr_info("SoC Type: %s\n", get_system_type());
 119}
 120
 121void __init prom_free_prom_memory(void)
 122{
 123}
 124
 125void __init device_tree_init(void)
 126{
 127        if (!initial_boot_params)
 128                return;
 129
 130        unflatten_and_copy_device_tree();
 131}
 132