LXR linux/arch/sh/kernel/cpu/sh4a/clock-shx3.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * arch/sh/kernel/cpu/sh4/clock-shx3.c
   4 *
   5 * SH-X3 support for the clock framework
   6 *
   7 *  Copyright (C) 2006-2007  Renesas Technology Corp.
   8 *  Copyright (C) 2006-2007  Renesas Solutions Corp.
   9 *  Copyright (C) 2006-2010  Paul Mundt
  10 */
  11#include <linux/init.h>
  12#include <linux/kernel.h>
  13#include <linux/io.h>
  14#include <linux/clkdev.h>
  15#include <asm/clock.h>
  16#include <asm/freq.h>
  17
  18/*
  19 * Default rate for the root input clock, reset this with clk_set_rate()
  20 * from the platform code.
  21 */
  22static struct clk extal_clk = {
  23        .rate           = 16666666,
  24};
  25
  26static unsigned long pll_recalc(struct clk *clk)
  27{
  28        /* PLL1 has a fixed x72 multiplier.  */
  29        return clk->parent->rate * 72;
  30}
  31
  32static struct sh_clk_ops pll_clk_ops = {
  33        .recalc         = pll_recalc,
  34};
  35
  36static struct clk pll_clk = {
  37        .ops            = &pll_clk_ops,
  38        .parent         = &extal_clk,
  39        .flags          = CLK_ENABLE_ON_INIT,
  40};
  41
  42static struct clk *clks[] = {
  43        &extal_clk,
  44        &pll_clk,
  45};
  46
  47static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
  48                               24, 32, 36, 48 };
  49
  50static struct clk_div_mult_table div4_div_mult_table = {
  51        .divisors = div2,
  52        .nr_divisors = ARRAY_SIZE(div2),
  53};
  54
  55static struct clk_div4_table div4_table = {
  56        .div_mult_table = &div4_div_mult_table,
  57};
  58
  59enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_SHA, DIV4_P, DIV4_NR };
  60
  61#define DIV4(_bit, _mask, _flags) \
  62  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
  63
  64struct clk div4_clks[DIV4_NR] = {
  65        [DIV4_P] = DIV4(0, 0x0f80, 0),
  66        [DIV4_SHA] = DIV4(4, 0x0ff0, 0),
  67        [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
  68        [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
  69        [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
  70        [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
  71};
  72
  73#define MSTPCR0         0xffc00030
  74#define MSTPCR1         0xffc00034
  75
  76enum { MSTP027, MSTP026, MSTP025, MSTP024,
  77       MSTP009, MSTP008, MSTP003, MSTP002,
  78       MSTP001, MSTP000, MSTP119, MSTP105,
  79       MSTP104, MSTP_NR };
  80
  81static struct clk mstp_clks[MSTP_NR] = {
  82        /* MSTPCR0 */
  83        [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
  84        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
  85        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
  86        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
  87        [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
  88        [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
  89        [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
  90        [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
  91        [MSTP001] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
  92        [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
  93
  94        /* MSTPCR1 */
  95        [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
  96        [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
  97        [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
  98};
  99
 100static struct clk_lookup lookups[] = {
 101        /* main clocks */
 102        CLKDEV_CON_ID("extal", &extal_clk),
 103        CLKDEV_CON_ID("pll_clk", &pll_clk),
 104
 105        /* DIV4 clocks */
 106        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 107        CLKDEV_CON_ID("shywaya_clk", &div4_clks[DIV4_SHA]),
 108        CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
 109        CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 110        CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 111        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 112
 113        /* MSTP32 clocks */
 114        CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
 115        CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
 116        CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
 117        CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
 118
 119        CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
 120        CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
 121        CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
 122        CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
 123
 124        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
 125        CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
 126
 127        CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
 128        CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
 129        CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
 130};
 131
 132int __init arch_clk_init(void)
 133{
 134        int i, ret = 0;
 135
 136        for (i = 0; i < ARRAY_SIZE(clks); i++)
 137                ret |= clk_register(clks[i]);
 138
 139        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 140
 141        if (!ret)
 142                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 143                                           &div4_table);
 144        if (!ret)
 145                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 146
 147        return ret;
 148}
 149