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38#include <linux/clk.h>
39#include <linux/clk-provider.h>
40#include <linux/module.h>
41#include <linux/io.h>
42#include <linux/device.h>
43#include <linux/err.h>
44#include <linux/pm_runtime.h>
45#include <linux/of.h>
46#include <linux/of_device.h>
47#include <linux/platform_device.h>
48#include <linux/platform_data/dmtimer-omap.h>
49
50#include <clocksource/timer-ti-dm.h>
51
52static u32 omap_reserved_systimers;
53static LIST_HEAD(omap_timer_list);
54static DEFINE_SPINLOCK(dm_timer_lock);
55
56enum {
57 REQUEST_ANY = 0,
58 REQUEST_BY_ID,
59 REQUEST_BY_CAP,
60 REQUEST_BY_NODE,
61};
62
63
64
65
66
67
68
69
70
71
72static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
73{
74 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
75 return __omap_dm_timer_read(timer, reg, timer->posted);
76}
77
78
79
80
81
82
83
84
85
86
87
88static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
89 u32 value)
90{
91 WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
92 __omap_dm_timer_write(timer, reg, value, timer->posted);
93}
94
95static void omap_timer_restore_context(struct omap_dm_timer *timer)
96{
97 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
98 timer->context.twer);
99 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
100 timer->context.tcrr);
101 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
102 timer->context.tldr);
103 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
104 timer->context.tmar);
105 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
106 timer->context.tsicr);
107 writel_relaxed(timer->context.tier, timer->irq_ena);
108 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
109 timer->context.tclr);
110}
111
112static int omap_dm_timer_reset(struct omap_dm_timer *timer)
113{
114 u32 l, timeout = 100000;
115
116 if (timer->revision != 1)
117 return -EINVAL;
118
119 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
120
121 do {
122 l = __omap_dm_timer_read(timer,
123 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
124 } while (!l && timeout--);
125
126 if (!timeout) {
127 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
128 return -ETIMEDOUT;
129 }
130
131
132 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
133 l |= 0x2 << 0x3;
134 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
135
136 timer->posted = 0;
137
138 return 0;
139}
140
141static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
142{
143 int ret;
144 struct clk *parent;
145
146
147
148
149
150 if (!timer->fclk)
151 return -ENODEV;
152
153 parent = clk_get(&timer->pdev->dev, NULL);
154 if (IS_ERR(parent))
155 return -ENODEV;
156
157
158 if (clk_is_match(parent, timer->fclk))
159 return 0;
160
161 ret = clk_set_parent(timer->fclk, parent);
162 if (ret < 0)
163 pr_err("%s: failed to set parent\n", __func__);
164
165 clk_put(parent);
166
167 return ret;
168}
169
170static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
171{
172 int ret;
173 const char *parent_name;
174 struct clk *parent;
175 struct dmtimer_platform_data *pdata;
176
177 if (unlikely(!timer) || IS_ERR(timer->fclk))
178 return -EINVAL;
179
180 switch (source) {
181 case OMAP_TIMER_SRC_SYS_CLK:
182 parent_name = "timer_sys_ck";
183 break;
184 case OMAP_TIMER_SRC_32_KHZ:
185 parent_name = "timer_32k_ck";
186 break;
187 case OMAP_TIMER_SRC_EXT_CLK:
188 parent_name = "timer_ext_ck";
189 break;
190 default:
191 return -EINVAL;
192 }
193
194 pdata = timer->pdev->dev.platform_data;
195
196
197
198
199
200
201 if (pdata && pdata->set_timer_src)
202 return pdata->set_timer_src(timer->pdev, source);
203
204#if defined(CONFIG_COMMON_CLK)
205
206 if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2)
207 return 0;
208#endif
209
210 parent = clk_get(&timer->pdev->dev, parent_name);
211 if (IS_ERR(parent)) {
212 pr_err("%s: %s not found\n", __func__, parent_name);
213 return -EINVAL;
214 }
215
216 ret = clk_set_parent(timer->fclk, parent);
217 if (ret < 0)
218 pr_err("%s: failed to set %s as parent\n", __func__,
219 parent_name);
220
221 clk_put(parent);
222
223 return ret;
224}
225
226static void omap_dm_timer_enable(struct omap_dm_timer *timer)
227{
228 int c;
229
230 pm_runtime_get_sync(&timer->pdev->dev);
231
232 if (!(timer->capability & OMAP_TIMER_ALWON)) {
233 if (timer->get_context_loss_count) {
234 c = timer->get_context_loss_count(&timer->pdev->dev);
235 if (c != timer->ctx_loss_count) {
236 omap_timer_restore_context(timer);
237 timer->ctx_loss_count = c;
238 }
239 } else {
240 omap_timer_restore_context(timer);
241 }
242 }
243}
244
245static void omap_dm_timer_disable(struct omap_dm_timer *timer)
246{
247 pm_runtime_put_sync(&timer->pdev->dev);
248}
249
250static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
251{
252 int rc;
253
254
255
256
257
258 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
259 timer->fclk = clk_get(&timer->pdev->dev, "fck");
260 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) {
261 dev_err(&timer->pdev->dev, ": No fclk handle.\n");
262 return -EINVAL;
263 }
264 }
265
266 omap_dm_timer_enable(timer);
267
268 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
269 rc = omap_dm_timer_reset(timer);
270 if (rc) {
271 omap_dm_timer_disable(timer);
272 return rc;
273 }
274 }
275
276 __omap_dm_timer_enable_posted(timer);
277 omap_dm_timer_disable(timer);
278
279 rc = omap_dm_timer_of_set_source(timer);
280 if (rc == -ENODEV)
281 return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
282
283 return rc;
284}
285
286static inline u32 omap_dm_timer_reserved_systimer(int id)
287{
288 return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
289}
290
291int omap_dm_timer_reserve_systimer(int id)
292{
293 if (omap_dm_timer_reserved_systimer(id))
294 return -ENODEV;
295
296 omap_reserved_systimers |= (1 << (id - 1));
297
298 return 0;
299}
300
301static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
302{
303 struct omap_dm_timer *timer = NULL, *t;
304 struct device_node *np = NULL;
305 unsigned long flags;
306 u32 cap = 0;
307 int id = 0;
308
309 switch (req_type) {
310 case REQUEST_BY_ID:
311 id = *(int *)data;
312 break;
313 case REQUEST_BY_CAP:
314 cap = *(u32 *)data;
315 break;
316 case REQUEST_BY_NODE:
317 np = (struct device_node *)data;
318 break;
319 default:
320
321 break;
322 }
323
324 spin_lock_irqsave(&dm_timer_lock, flags);
325 list_for_each_entry(t, &omap_timer_list, node) {
326 if (t->reserved)
327 continue;
328
329 switch (req_type) {
330 case REQUEST_BY_ID:
331 if (id == t->pdev->id) {
332 timer = t;
333 timer->reserved = 1;
334 goto found;
335 }
336 break;
337 case REQUEST_BY_CAP:
338 if (cap == (t->capability & cap)) {
339
340
341
342
343
344
345
346
347 if (timer)
348 timer->reserved = 0;
349 timer = t;
350 timer->reserved = 1;
351
352
353 if (t->capability == cap)
354 goto found;
355 }
356 break;
357 case REQUEST_BY_NODE:
358 if (np == t->pdev->dev.of_node) {
359 timer = t;
360 timer->reserved = 1;
361 goto found;
362 }
363 break;
364 default:
365
366 timer = t;
367 timer->reserved = 1;
368 goto found;
369 }
370 }
371found:
372 spin_unlock_irqrestore(&dm_timer_lock, flags);
373
374 if (timer && omap_dm_timer_prepare(timer)) {
375 timer->reserved = 0;
376 timer = NULL;
377 }
378
379 if (!timer)
380 pr_debug("%s: timer request failed!\n", __func__);
381
382 return timer;
383}
384
385static struct omap_dm_timer *omap_dm_timer_request(void)
386{
387 return _omap_dm_timer_request(REQUEST_ANY, NULL);
388}
389
390static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
391{
392
393 if (of_have_populated_dt()) {
394 pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
395 __func__);
396 return NULL;
397 }
398
399 return _omap_dm_timer_request(REQUEST_BY_ID, &id);
400}
401
402
403
404
405
406
407
408
409
410
411struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
412{
413 return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
414}
415
416
417
418
419
420
421
422
423static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
424{
425 if (!np)
426 return NULL;
427
428 return _omap_dm_timer_request(REQUEST_BY_NODE, np);
429}
430
431static int omap_dm_timer_free(struct omap_dm_timer *timer)
432{
433 if (unlikely(!timer))
434 return -EINVAL;
435
436 clk_put(timer->fclk);
437
438 WARN_ON(!timer->reserved);
439 timer->reserved = 0;
440 return 0;
441}
442
443int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
444{
445 if (timer)
446 return timer->irq;
447 return -EINVAL;
448}
449
450#if defined(CONFIG_ARCH_OMAP1)
451#include <mach/hardware.h>
452
453static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
454{
455 return NULL;
456}
457
458
459
460
461
462__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
463{
464 int i = 0;
465 struct omap_dm_timer *timer = NULL;
466 unsigned long flags;
467
468
469 if (!(inputmask & (1 << 1)))
470 return inputmask;
471
472
473 spin_lock_irqsave(&dm_timer_lock, flags);
474 list_for_each_entry(timer, &omap_timer_list, node) {
475 u32 l;
476
477 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
478 if (l & OMAP_TIMER_CTRL_ST) {
479 if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
480 inputmask &= ~(1 << 1);
481 else
482 inputmask &= ~(1 << 2);
483 }
484 i++;
485 }
486 spin_unlock_irqrestore(&dm_timer_lock, flags);
487
488 return inputmask;
489}
490
491#else
492
493static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
494{
495 if (timer && !IS_ERR(timer->fclk))
496 return timer->fclk;
497 return NULL;
498}
499
500__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
501{
502 BUG();
503
504 return 0;
505}
506
507#endif
508
509int omap_dm_timer_trigger(struct omap_dm_timer *timer)
510{
511 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
512 pr_err("%s: timer not available or enabled.\n", __func__);
513 return -EINVAL;
514 }
515
516 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
517 return 0;
518}
519
520static int omap_dm_timer_start(struct omap_dm_timer *timer)
521{
522 u32 l;
523
524 if (unlikely(!timer))
525 return -EINVAL;
526
527 omap_dm_timer_enable(timer);
528
529 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
530 if (!(l & OMAP_TIMER_CTRL_ST)) {
531 l |= OMAP_TIMER_CTRL_ST;
532 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
533 }
534
535
536 timer->context.tclr = l;
537 return 0;
538}
539
540static int omap_dm_timer_stop(struct omap_dm_timer *timer)
541{
542 unsigned long rate = 0;
543
544 if (unlikely(!timer))
545 return -EINVAL;
546
547 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
548 rate = clk_get_rate(timer->fclk);
549
550 __omap_dm_timer_stop(timer, timer->posted, rate);
551
552
553
554
555
556
557 timer->context.tclr =
558 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
559 omap_dm_timer_disable(timer);
560 return 0;
561}
562
563static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
564 unsigned int load)
565{
566 u32 l;
567
568 if (unlikely(!timer))
569 return -EINVAL;
570
571 omap_dm_timer_enable(timer);
572 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
573 if (autoreload)
574 l |= OMAP_TIMER_CTRL_AR;
575 else
576 l &= ~OMAP_TIMER_CTRL_AR;
577 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
578 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
579
580 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
581
582 timer->context.tclr = l;
583 timer->context.tldr = load;
584 omap_dm_timer_disable(timer);
585 return 0;
586}
587
588static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
589 unsigned int match)
590{
591 u32 l;
592
593 if (unlikely(!timer))
594 return -EINVAL;
595
596 omap_dm_timer_enable(timer);
597 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
598 if (enable)
599 l |= OMAP_TIMER_CTRL_CE;
600 else
601 l &= ~OMAP_TIMER_CTRL_CE;
602 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
603 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
604
605
606 timer->context.tclr = l;
607 timer->context.tmar = match;
608 omap_dm_timer_disable(timer);
609 return 0;
610}
611
612static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
613 int toggle, int trigger)
614{
615 u32 l;
616
617 if (unlikely(!timer))
618 return -EINVAL;
619
620 omap_dm_timer_enable(timer);
621 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
622 l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
623 OMAP_TIMER_CTRL_PT | (0x03 << 10));
624 if (def_on)
625 l |= OMAP_TIMER_CTRL_SCPWM;
626 if (toggle)
627 l |= OMAP_TIMER_CTRL_PT;
628 l |= trigger << 10;
629 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
630
631
632 timer->context.tclr = l;
633 omap_dm_timer_disable(timer);
634 return 0;
635}
636
637static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
638 int prescaler)
639{
640 u32 l;
641
642 if (unlikely(!timer) || prescaler < -1 || prescaler > 7)
643 return -EINVAL;
644
645 omap_dm_timer_enable(timer);
646 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
647 l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
648 if (prescaler >= 0) {
649 l |= OMAP_TIMER_CTRL_PRE;
650 l |= prescaler << 2;
651 }
652 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
653
654
655 timer->context.tclr = l;
656 omap_dm_timer_disable(timer);
657 return 0;
658}
659
660static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
661 unsigned int value)
662{
663 if (unlikely(!timer))
664 return -EINVAL;
665
666 omap_dm_timer_enable(timer);
667 __omap_dm_timer_int_enable(timer, value);
668
669
670 timer->context.tier = value;
671 timer->context.twer = value;
672 omap_dm_timer_disable(timer);
673 return 0;
674}
675
676
677
678
679
680
681
682
683static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
684{
685 u32 l = mask;
686
687 if (unlikely(!timer))
688 return -EINVAL;
689
690 omap_dm_timer_enable(timer);
691
692 if (timer->revision == 1)
693 l = readl_relaxed(timer->irq_ena) & ~mask;
694
695 writel_relaxed(l, timer->irq_dis);
696 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
697 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
698
699
700 timer->context.tier &= ~mask;
701 timer->context.twer &= ~mask;
702 omap_dm_timer_disable(timer);
703 return 0;
704}
705
706static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
707{
708 unsigned int l;
709
710 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
711 pr_err("%s: timer not available or enabled.\n", __func__);
712 return 0;
713 }
714
715 l = readl_relaxed(timer->irq_stat);
716
717 return l;
718}
719
720static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
721{
722 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
723 return -EINVAL;
724
725 __omap_dm_timer_write_status(timer, value);
726
727 return 0;
728}
729
730static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
731{
732 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
733 pr_err("%s: timer not iavailable or enabled.\n", __func__);
734 return 0;
735 }
736
737 return __omap_dm_timer_read_counter(timer, timer->posted);
738}
739
740static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
741{
742 if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
743 pr_err("%s: timer not available or enabled.\n", __func__);
744 return -EINVAL;
745 }
746
747 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
748
749
750 timer->context.tcrr = value;
751 return 0;
752}
753
754int omap_dm_timers_active(void)
755{
756 struct omap_dm_timer *timer;
757
758 list_for_each_entry(timer, &omap_timer_list, node) {
759 if (!timer->reserved)
760 continue;
761
762 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
763 OMAP_TIMER_CTRL_ST) {
764 return 1;
765 }
766 }
767 return 0;
768}
769
770static const struct of_device_id omap_timer_match[];
771
772
773
774
775
776
777
778
779static int omap_dm_timer_probe(struct platform_device *pdev)
780{
781 unsigned long flags;
782 struct omap_dm_timer *timer;
783 struct device *dev = &pdev->dev;
784 const struct dmtimer_platform_data *pdata;
785 int ret;
786
787 pdata = of_device_get_match_data(dev);
788 if (!pdata)
789 pdata = dev_get_platdata(dev);
790 else
791 dev->platform_data = (void *)pdata;
792
793 if (!pdata) {
794 dev_err(dev, "%s: no platform data.\n", __func__);
795 return -ENODEV;
796 }
797
798 timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL);
799 if (!timer)
800 return -ENOMEM;
801
802 timer->irq = platform_get_irq(pdev, 0);
803 if (timer->irq < 0)
804 return timer->irq;
805
806 timer->fclk = ERR_PTR(-ENODEV);
807 timer->io_base = devm_platform_ioremap_resource(pdev, 0);
808 if (IS_ERR(timer->io_base))
809 return PTR_ERR(timer->io_base);
810
811 if (dev->of_node) {
812 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
813 timer->capability |= OMAP_TIMER_ALWON;
814 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
815 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
816 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
817 timer->capability |= OMAP_TIMER_HAS_PWM;
818 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
819 timer->capability |= OMAP_TIMER_SECURE;
820 } else {
821 timer->id = pdev->id;
822 timer->capability = pdata->timer_capability;
823 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
824 timer->get_context_loss_count = pdata->get_context_loss_count;
825 }
826
827 if (pdata)
828 timer->errata = pdata->timer_errata;
829
830 timer->pdev = pdev;
831
832 pm_runtime_enable(dev);
833
834 if (!timer->reserved) {
835 ret = pm_runtime_get_sync(dev);
836 if (ret < 0) {
837 dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
838 __func__);
839 goto err_get_sync;
840 }
841 __omap_dm_timer_init_regs(timer);
842 pm_runtime_put(dev);
843 }
844
845
846 spin_lock_irqsave(&dm_timer_lock, flags);
847 list_add_tail(&timer->node, &omap_timer_list);
848 spin_unlock_irqrestore(&dm_timer_lock, flags);
849
850 dev_dbg(dev, "Device Probed.\n");
851
852 return 0;
853
854err_get_sync:
855 pm_runtime_put_noidle(dev);
856 pm_runtime_disable(dev);
857 return ret;
858}
859
860
861
862
863
864
865
866
867
868static int omap_dm_timer_remove(struct platform_device *pdev)
869{
870 struct omap_dm_timer *timer;
871 unsigned long flags;
872 int ret = -EINVAL;
873
874 spin_lock_irqsave(&dm_timer_lock, flags);
875 list_for_each_entry(timer, &omap_timer_list, node)
876 if (!strcmp(dev_name(&timer->pdev->dev),
877 dev_name(&pdev->dev))) {
878 list_del(&timer->node);
879 ret = 0;
880 break;
881 }
882 spin_unlock_irqrestore(&dm_timer_lock, flags);
883
884 pm_runtime_disable(&pdev->dev);
885
886 return ret;
887}
888
889static const struct omap_dm_timer_ops dmtimer_ops = {
890 .request_by_node = omap_dm_timer_request_by_node,
891 .request_specific = omap_dm_timer_request_specific,
892 .request = omap_dm_timer_request,
893 .set_source = omap_dm_timer_set_source,
894 .get_irq = omap_dm_timer_get_irq,
895 .set_int_enable = omap_dm_timer_set_int_enable,
896 .set_int_disable = omap_dm_timer_set_int_disable,
897 .free = omap_dm_timer_free,
898 .enable = omap_dm_timer_enable,
899 .disable = omap_dm_timer_disable,
900 .get_fclk = omap_dm_timer_get_fclk,
901 .start = omap_dm_timer_start,
902 .stop = omap_dm_timer_stop,
903 .set_load = omap_dm_timer_set_load,
904 .set_match = omap_dm_timer_set_match,
905 .set_pwm = omap_dm_timer_set_pwm,
906 .set_prescaler = omap_dm_timer_set_prescaler,
907 .read_counter = omap_dm_timer_read_counter,
908 .write_counter = omap_dm_timer_write_counter,
909 .read_status = omap_dm_timer_read_status,
910 .write_status = omap_dm_timer_write_status,
911};
912
913static const struct dmtimer_platform_data omap3plus_pdata = {
914 .timer_errata = OMAP_TIMER_ERRATA_I103_I767,
915 .timer_ops = &dmtimer_ops,
916};
917
918static const struct of_device_id omap_timer_match[] = {
919 {
920 .compatible = "ti,omap2420-timer",
921 },
922 {
923 .compatible = "ti,omap3430-timer",
924 .data = &omap3plus_pdata,
925 },
926 {
927 .compatible = "ti,omap4430-timer",
928 .data = &omap3plus_pdata,
929 },
930 {
931 .compatible = "ti,omap5430-timer",
932 .data = &omap3plus_pdata,
933 },
934 {
935 .compatible = "ti,am335x-timer",
936 .data = &omap3plus_pdata,
937 },
938 {
939 .compatible = "ti,am335x-timer-1ms",
940 .data = &omap3plus_pdata,
941 },
942 {
943 .compatible = "ti,dm816-timer",
944 .data = &omap3plus_pdata,
945 },
946 {},
947};
948MODULE_DEVICE_TABLE(of, omap_timer_match);
949
950static struct platform_driver omap_dm_timer_driver = {
951 .probe = omap_dm_timer_probe,
952 .remove = omap_dm_timer_remove,
953 .driver = {
954 .name = "omap_timer",
955 .of_match_table = of_match_ptr(omap_timer_match),
956 },
957};
958
959module_platform_driver(omap_dm_timer_driver);
960
961MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
962MODULE_LICENSE("GPL");
963MODULE_AUTHOR("Texas Instruments Inc");
964