1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25#include <drm/amdgpu_drm.h>
26#include <drm/drm_drv.h>
27#include <drm/drm_gem.h>
28#include <drm/drm_vblank.h>
29#include "amdgpu_drv.h"
30
31#include <drm/drm_pciids.h>
32#include <linux/console.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
37#include <drm/drm_probe_helper.h>
38#include <linux/mmu_notifier.h>
39
40#include "amdgpu.h"
41#include "amdgpu_irq.h"
42#include "amdgpu_dma_buf.h"
43
44#include "amdgpu_amdkfd.h"
45
46#include "amdgpu_ras.h"
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89#define KMS_DRIVER_MAJOR 3
90#define KMS_DRIVER_MINOR 36
91#define KMS_DRIVER_PATCHLEVEL 0
92
93int amdgpu_vram_limit = 0;
94int amdgpu_vis_vram_limit = 0;
95int amdgpu_gart_size = -1;
96int amdgpu_gtt_size = -1;
97int amdgpu_moverate = -1;
98int amdgpu_benchmarking = 0;
99int amdgpu_testing = 0;
100int amdgpu_audio = -1;
101int amdgpu_disp_priority = 0;
102int amdgpu_hw_i2c = 0;
103int amdgpu_pcie_gen2 = -1;
104int amdgpu_msi = -1;
105char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
106int amdgpu_dpm = -1;
107int amdgpu_fw_load_type = -1;
108int amdgpu_aspm = -1;
109int amdgpu_runtime_pm = -1;
110uint amdgpu_ip_block_mask = 0xffffffff;
111int amdgpu_bapm = -1;
112int amdgpu_deep_color = 0;
113int amdgpu_vm_size = -1;
114int amdgpu_vm_fragment_size = -1;
115int amdgpu_vm_block_size = -1;
116int amdgpu_vm_fault_stop = 0;
117int amdgpu_vm_debug = 0;
118int amdgpu_vm_update_mode = -1;
119int amdgpu_exp_hw_support = 0;
120int amdgpu_dc = -1;
121int amdgpu_sched_jobs = 32;
122int amdgpu_sched_hw_submission = 2;
123uint amdgpu_pcie_gen_cap = 0;
124uint amdgpu_pcie_lane_cap = 0;
125uint amdgpu_cg_mask = 0xffffffff;
126uint amdgpu_pg_mask = 0xffffffff;
127uint amdgpu_sdma_phase_quantum = 32;
128char *amdgpu_disable_cu = NULL;
129char *amdgpu_virtual_display = NULL;
130
131uint amdgpu_pp_feature_mask = 0xffffbfff;
132uint amdgpu_force_long_training = 0;
133int amdgpu_job_hang_limit = 0;
134int amdgpu_lbpw = -1;
135int amdgpu_compute_multipipe = -1;
136int amdgpu_gpu_recovery = -1;
137int amdgpu_emu_mode = 0;
138uint amdgpu_smu_memory_pool_size = 0;
139
140uint amdgpu_dc_feature_mask = 0;
141int amdgpu_async_gfx_ring = 1;
142int amdgpu_mcbp = 0;
143int amdgpu_discovery = -1;
144int amdgpu_mes = 0;
145int amdgpu_noretry;
146int amdgpu_force_asic_type = -1;
147
148struct amdgpu_mgpu_info mgpu_info = {
149 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
150};
151int amdgpu_ras_enable = -1;
152uint amdgpu_ras_mask = 0xffffffff;
153
154
155
156
157
158MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
159module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
160
161
162
163
164
165MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
166module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
167
168
169
170
171
172MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
173module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
174
175
176
177
178
179
180MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
181module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
182
183
184
185
186
187MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
188module_param_named(moverate, amdgpu_moverate, int, 0600);
189
190
191
192
193
194MODULE_PARM_DESC(benchmark, "Run benchmark");
195module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
196
197
198
199
200
201MODULE_PARM_DESC(test, "Run tests");
202module_param_named(test, amdgpu_testing, int, 0444);
203
204
205
206
207
208MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
209module_param_named(audio, amdgpu_audio, int, 0444);
210
211
212
213
214
215MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
216module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
217
218
219
220
221
222MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
223module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
224
225
226
227
228
229MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
230module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
231
232
233
234
235
236MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
237module_param_named(msi, amdgpu_msi, int, 0444);
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; "
256 "for passthrough or sriov, 10000 for all jobs."
257 " 0: keep default value. negative: infinity timeout), "
258 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
259 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
260module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
261
262
263
264
265
266
267
268MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
269module_param_named(dpm, amdgpu_dpm, int, 0444);
270
271
272
273
274
275MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
276module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
277
278
279
280
281
282MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
283module_param_named(aspm, amdgpu_aspm, int, 0444);
284
285
286
287
288
289
290MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
291module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
292
293
294
295
296
297
298
299
300MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
301module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
302
303
304
305
306
307
308MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
309module_param_named(bapm, amdgpu_bapm, int, 0444);
310
311
312
313
314
315MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
316module_param_named(deep_color, amdgpu_deep_color, int, 0444);
317
318
319
320
321
322MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
323module_param_named(vm_size, amdgpu_vm_size, int, 0444);
324
325
326
327
328
329MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
330module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
331
332
333
334
335
336MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
337module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
338
339
340
341
342
343MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
344module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
345
346
347
348
349
350MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
351module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
352
353
354
355
356
357
358MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
359module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
360
361
362
363
364
365MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
366module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
367
368
369
370
371
372MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
373module_param_named(dc, amdgpu_dc, int, 0444);
374
375
376
377
378
379MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
380module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
381
382
383
384
385
386MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
387module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
388
389
390
391
392
393
394MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
395module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
396
397
398
399
400
401
402MODULE_PARM_DESC(forcelongtraining, "force memory long training");
403module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
404
405
406
407
408
409
410MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
411module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
412
413
414
415
416
417
418MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
419module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
420
421
422
423
424
425
426MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
427module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
428
429
430
431
432
433
434MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
435module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
436
437
438
439
440
441MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
442module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
443
444
445
446
447
448MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
449module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
450
451
452
453
454
455
456
457
458MODULE_PARM_DESC(virtual_display,
459 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
460module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
461
462
463
464
465
466MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
467module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
468
469
470
471
472
473MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
474module_param_named(lbpw, amdgpu_lbpw, int, 0444);
475
476MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
477module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
478
479
480
481
482
483MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
484module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
485
486
487
488
489
490MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
491module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
492
493
494
495
496
497MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
498module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
499
500
501
502
503
504
505MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
506module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
507
508
509
510
511
512
513
514#ifdef CONFIG_DRM_AMDGPU_SI
515
516#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
517int amdgpu_si_support = 0;
518MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
519#else
520int amdgpu_si_support = 1;
521MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
522#endif
523
524module_param_named(si_support, amdgpu_si_support, int, 0444);
525#endif
526
527
528
529
530
531
532
533#ifdef CONFIG_DRM_AMDGPU_CIK
534
535#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
536int amdgpu_cik_support = 0;
537MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
538#else
539int amdgpu_cik_support = 1;
540MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
541#endif
542
543module_param_named(cik_support, amdgpu_cik_support, int, 0444);
544#endif
545
546
547
548
549
550
551MODULE_PARM_DESC(smu_memory_pool_size,
552 "reserve gtt for smu debug usage, 0 = disable,"
553 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
554module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
555
556
557
558
559
560MODULE_PARM_DESC(async_gfx_ring,
561 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
562module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
563
564
565
566
567
568MODULE_PARM_DESC(mcbp,
569 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
570module_param_named(mcbp, amdgpu_mcbp, int, 0444);
571
572
573
574
575
576
577MODULE_PARM_DESC(discovery,
578 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
579module_param_named(discovery, amdgpu_discovery, int, 0444);
580
581
582
583
584
585
586MODULE_PARM_DESC(mes,
587 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
588module_param_named(mes, amdgpu_mes, int, 0444);
589
590MODULE_PARM_DESC(noretry,
591 "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)");
592module_param_named(noretry, amdgpu_noretry, int, 0644);
593
594
595
596
597
598MODULE_PARM_DESC(force_asic_type,
599 "A non negative value used to specify the asic type for all supported GPUs");
600module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
601
602
603
604#ifdef CONFIG_HSA_AMD
605
606
607
608
609
610
611int sched_policy = KFD_SCHED_POLICY_HWS;
612module_param(sched_policy, int, 0444);
613MODULE_PARM_DESC(sched_policy,
614 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
615
616
617
618
619
620
621int hws_max_conc_proc = 8;
622module_param(hws_max_conc_proc, int, 0444);
623MODULE_PARM_DESC(hws_max_conc_proc,
624 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
625
626
627
628
629
630
631
632int cwsr_enable = 1;
633module_param(cwsr_enable, int, 0444);
634MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
635
636
637
638
639
640
641int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
642module_param(max_num_of_queues_per_device, int, 0444);
643MODULE_PARM_DESC(max_num_of_queues_per_device,
644 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
645
646
647
648
649
650
651int send_sigterm;
652module_param(send_sigterm, int, 0444);
653MODULE_PARM_DESC(send_sigterm,
654 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
655
656
657
658
659
660
661
662
663int debug_largebar;
664module_param(debug_largebar, int, 0444);
665MODULE_PARM_DESC(debug_largebar,
666 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
667
668
669
670
671
672
673
674int ignore_crat;
675module_param(ignore_crat, int, 0444);
676MODULE_PARM_DESC(ignore_crat,
677 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)");
678
679
680
681
682
683
684int halt_if_hws_hang;
685module_param(halt_if_hws_hang, int, 0644);
686MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
687
688
689
690
691
692
693
694bool hws_gws_support;
695module_param(hws_gws_support, bool, 0444);
696MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)");
697
698
699
700
701
702int queue_preemption_timeout_ms = 9000;
703module_param(queue_preemption_timeout_ms, int, 0644);
704MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
705#endif
706
707
708
709
710
711
712MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
713module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
714
715
716
717
718
719
720
721
722
723
724
725
726
727uint amdgpu_dm_abm_level = 0;
728MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
729module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
730
731static const struct pci_device_id pciidlist[] = {
732#ifdef CONFIG_DRM_AMDGPU_SI
733 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
734 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
735 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
736 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
737 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
738 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
739 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
740 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
741 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
742 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
743 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
744 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
745 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
746 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
747 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
748 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
749 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
750 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
751 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
752 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
753 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
754 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
755 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
756 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
757 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
758 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
759 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
760 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
761 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
762 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
763 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
764 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
765 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
766 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
767 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
768 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
769 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
770 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
771 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
772 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
773 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
774 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
775 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
776 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
777 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
778 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
779 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
780 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
781 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
782 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
783 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
784 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
785 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
786 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
787 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
788 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
789 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
790 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
791 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
792 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
793 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
794 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
795 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
796 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
797 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
798 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
799 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
800 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
801 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
802 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
803 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
804 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
805#endif
806#ifdef CONFIG_DRM_AMDGPU_CIK
807
808 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
809 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
810 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
811 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
812 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
813 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
814 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
815 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
816 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
817 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
818 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
819 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
820 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
821 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
822 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
823 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
824 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
825 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
826 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
827 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
828 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
829 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
830
831 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
832 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
833 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
834 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
835 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
836 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
837 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
838 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
839 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
840 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
841 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
842
843 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
844 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
845 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
846 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
847 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
848 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
849 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
850 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
851 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
852 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
853 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
854 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
855
856 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
857 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
858 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
859 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
860 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
861 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
862 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
863 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
864 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
865 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
866 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
867 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
868 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
869 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
870 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
871 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
872
873 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
874 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
875 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
876 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
877 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
878 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
879 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
880 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
881 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
882 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
883 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
884 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
885 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
886 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
887 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
888 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
889#endif
890
891 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
892 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
893 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
894 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
895 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
896
897 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
898 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
899 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
900 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
901 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
902 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
903 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
904 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
905 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
906
907 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
908 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
909
910 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
911 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
912 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
913 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
914 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
915
916 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
917
918 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
919 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
920 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
921 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
922 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
923 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
924 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
925 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
926 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
927
928 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
929 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
930 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
931 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
932 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
933 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
934 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
935 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
936 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
937 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
938 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
939 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
940 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
941
942 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
943 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
944 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
945 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
946 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
947 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
948 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
949 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
950
951 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
952 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
953 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
954
955 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
956 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
957 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
958 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
959 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
960 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
961 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
962 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
963 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
964 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
965 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
966 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
967 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
968 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
969 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
970
971 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
972 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
973 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
974 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
975 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
976
977 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
978 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
979 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
980 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
981 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
982 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
983 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
984
985 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
986 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
987
988 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
989 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
990 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
991 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT},
992
993 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
994 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
995 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
996 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
997 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
998 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
999 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1000
1001 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1002 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1003 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1004 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1005
1006
1007 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1008
1009
1010 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1011 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT},
1012
1013 {0, 0, 0}
1014};
1015
1016MODULE_DEVICE_TABLE(pci, pciidlist);
1017
1018static struct drm_driver kms_driver;
1019
1020static int amdgpu_pci_probe(struct pci_dev *pdev,
1021 const struct pci_device_id *ent)
1022{
1023 struct drm_device *dev;
1024 unsigned long flags = ent->driver_data;
1025 int ret, retry = 0;
1026 bool supports_atomic = false;
1027
1028 if (!amdgpu_virtual_display &&
1029 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1030 supports_atomic = true;
1031
1032 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1033 DRM_INFO("This hardware requires experimental hardware support.\n"
1034 "See modparam exp_hw_support\n");
1035 return -ENODEV;
1036 }
1037
1038#ifdef CONFIG_DRM_AMDGPU_SI
1039 if (!amdgpu_si_support) {
1040 switch (flags & AMD_ASIC_MASK) {
1041 case CHIP_TAHITI:
1042 case CHIP_PITCAIRN:
1043 case CHIP_VERDE:
1044 case CHIP_OLAND:
1045 case CHIP_HAINAN:
1046 dev_info(&pdev->dev,
1047 "SI support provided by radeon.\n");
1048 dev_info(&pdev->dev,
1049 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1050 );
1051 return -ENODEV;
1052 }
1053 }
1054#endif
1055#ifdef CONFIG_DRM_AMDGPU_CIK
1056 if (!amdgpu_cik_support) {
1057 switch (flags & AMD_ASIC_MASK) {
1058 case CHIP_KAVERI:
1059 case CHIP_BONAIRE:
1060 case CHIP_HAWAII:
1061 case CHIP_KABINI:
1062 case CHIP_MULLINS:
1063 dev_info(&pdev->dev,
1064 "CIK support provided by radeon.\n");
1065 dev_info(&pdev->dev,
1066 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1067 );
1068 return -ENODEV;
1069 }
1070 }
1071#endif
1072
1073
1074 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb");
1075 if (ret)
1076 return ret;
1077
1078 dev = drm_dev_alloc(&kms_driver, &pdev->dev);
1079 if (IS_ERR(dev))
1080 return PTR_ERR(dev);
1081
1082 if (!supports_atomic)
1083 dev->driver_features &= ~DRIVER_ATOMIC;
1084
1085 ret = pci_enable_device(pdev);
1086 if (ret)
1087 goto err_free;
1088
1089 dev->pdev = pdev;
1090
1091 pci_set_drvdata(pdev, dev);
1092
1093retry_init:
1094 ret = drm_dev_register(dev, ent->driver_data);
1095 if (ret == -EAGAIN && ++retry <= 3) {
1096 DRM_INFO("retry init %d\n", retry);
1097
1098 msleep(5000);
1099 goto retry_init;
1100 } else if (ret)
1101 goto err_pci;
1102
1103 return 0;
1104
1105err_pci:
1106 pci_disable_device(pdev);
1107err_free:
1108 drm_dev_put(dev);
1109 return ret;
1110}
1111
1112static void
1113amdgpu_pci_remove(struct pci_dev *pdev)
1114{
1115 struct drm_device *dev = pci_get_drvdata(pdev);
1116
1117#ifdef MODULE
1118 if (THIS_MODULE->state != MODULE_STATE_GOING)
1119#endif
1120 DRM_ERROR("Hotplug removal is not supported\n");
1121 drm_dev_unplug(dev);
1122 drm_dev_put(dev);
1123 pci_disable_device(pdev);
1124 pci_set_drvdata(pdev, NULL);
1125}
1126
1127static void
1128amdgpu_pci_shutdown(struct pci_dev *pdev)
1129{
1130 struct drm_device *dev = pci_get_drvdata(pdev);
1131 struct amdgpu_device *adev = dev->dev_private;
1132
1133 if (amdgpu_ras_intr_triggered())
1134 return;
1135
1136
1137
1138
1139
1140
1141 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1142 amdgpu_device_ip_suspend(adev);
1143 adev->mp1_state = PP_MP1_STATE_NONE;
1144}
1145
1146static int amdgpu_pmops_suspend(struct device *dev)
1147{
1148 struct drm_device *drm_dev = dev_get_drvdata(dev);
1149
1150 return amdgpu_device_suspend(drm_dev, true);
1151}
1152
1153static int amdgpu_pmops_resume(struct device *dev)
1154{
1155 struct drm_device *drm_dev = dev_get_drvdata(dev);
1156
1157
1158 if (amdgpu_device_supports_boco(drm_dev) ||
1159 amdgpu_device_supports_baco(drm_dev)) {
1160 pm_runtime_disable(dev);
1161 pm_runtime_set_active(dev);
1162 pm_runtime_enable(dev);
1163 }
1164
1165 return amdgpu_device_resume(drm_dev, true);
1166}
1167
1168static int amdgpu_pmops_freeze(struct device *dev)
1169{
1170 struct drm_device *drm_dev = dev_get_drvdata(dev);
1171 struct amdgpu_device *adev = drm_dev->dev_private;
1172 int r;
1173
1174 r = amdgpu_device_suspend(drm_dev, true);
1175 if (r)
1176 return r;
1177 return amdgpu_asic_reset(adev);
1178}
1179
1180static int amdgpu_pmops_thaw(struct device *dev)
1181{
1182 struct drm_device *drm_dev = dev_get_drvdata(dev);
1183
1184 return amdgpu_device_resume(drm_dev, true);
1185}
1186
1187static int amdgpu_pmops_poweroff(struct device *dev)
1188{
1189 struct drm_device *drm_dev = dev_get_drvdata(dev);
1190
1191 return amdgpu_device_suspend(drm_dev, true);
1192}
1193
1194static int amdgpu_pmops_restore(struct device *dev)
1195{
1196 struct drm_device *drm_dev = dev_get_drvdata(dev);
1197
1198 return amdgpu_device_resume(drm_dev, true);
1199}
1200
1201static int amdgpu_pmops_runtime_suspend(struct device *dev)
1202{
1203 struct pci_dev *pdev = to_pci_dev(dev);
1204 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1205 struct amdgpu_device *adev = drm_dev->dev_private;
1206 int ret, i;
1207
1208 if (!adev->runpm) {
1209 pm_runtime_forbid(dev);
1210 return -EBUSY;
1211 }
1212
1213
1214 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1215 struct amdgpu_ring *ring = adev->rings[i];
1216 if (ring && ring->sched.ready) {
1217 ret = amdgpu_fence_wait_empty(ring);
1218 if (ret)
1219 return -EBUSY;
1220 }
1221 }
1222
1223 if (amdgpu_device_supports_boco(drm_dev))
1224 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1225 drm_kms_helper_poll_disable(drm_dev);
1226
1227 ret = amdgpu_device_suspend(drm_dev, false);
1228 if (amdgpu_device_supports_boco(drm_dev)) {
1229
1230
1231
1232 if (amdgpu_is_atpx_hybrid()) {
1233 pci_ignore_hotplug(pdev);
1234 } else {
1235 pci_save_state(pdev);
1236 pci_disable_device(pdev);
1237 pci_ignore_hotplug(pdev);
1238 pci_set_power_state(pdev, PCI_D3cold);
1239 }
1240 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1241 } else if (amdgpu_device_supports_baco(drm_dev)) {
1242 amdgpu_device_baco_enter(drm_dev);
1243 }
1244
1245 return 0;
1246}
1247
1248static int amdgpu_pmops_runtime_resume(struct device *dev)
1249{
1250 struct pci_dev *pdev = to_pci_dev(dev);
1251 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1252 struct amdgpu_device *adev = drm_dev->dev_private;
1253 int ret;
1254
1255 if (!adev->runpm)
1256 return -EINVAL;
1257
1258 if (amdgpu_device_supports_boco(drm_dev)) {
1259 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1260
1261
1262
1263
1264 if (amdgpu_is_atpx_hybrid()) {
1265 pci_set_master(pdev);
1266 } else {
1267 pci_set_power_state(pdev, PCI_D0);
1268 pci_restore_state(pdev);
1269 ret = pci_enable_device(pdev);
1270 if (ret)
1271 return ret;
1272 pci_set_master(pdev);
1273 }
1274 } else if (amdgpu_device_supports_baco(drm_dev)) {
1275 amdgpu_device_baco_exit(drm_dev);
1276 }
1277 ret = amdgpu_device_resume(drm_dev, false);
1278 drm_kms_helper_poll_enable(drm_dev);
1279 if (amdgpu_device_supports_boco(drm_dev))
1280 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1281 return 0;
1282}
1283
1284static int amdgpu_pmops_runtime_idle(struct device *dev)
1285{
1286 struct drm_device *drm_dev = dev_get_drvdata(dev);
1287 struct amdgpu_device *adev = drm_dev->dev_private;
1288 struct drm_crtc *crtc;
1289
1290 if (!adev->runpm) {
1291 pm_runtime_forbid(dev);
1292 return -EBUSY;
1293 }
1294
1295 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
1296 if (crtc->enabled) {
1297 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1298 return -EBUSY;
1299 }
1300 }
1301
1302 pm_runtime_mark_last_busy(dev);
1303 pm_runtime_autosuspend(dev);
1304
1305 return 1;
1306}
1307
1308long amdgpu_drm_ioctl(struct file *filp,
1309 unsigned int cmd, unsigned long arg)
1310{
1311 struct drm_file *file_priv = filp->private_data;
1312 struct drm_device *dev;
1313 long ret;
1314 dev = file_priv->minor->dev;
1315 ret = pm_runtime_get_sync(dev->dev);
1316 if (ret < 0)
1317 return ret;
1318
1319 ret = drm_ioctl(filp, cmd, arg);
1320
1321 pm_runtime_mark_last_busy(dev->dev);
1322 pm_runtime_put_autosuspend(dev->dev);
1323 return ret;
1324}
1325
1326static const struct dev_pm_ops amdgpu_pm_ops = {
1327 .suspend = amdgpu_pmops_suspend,
1328 .resume = amdgpu_pmops_resume,
1329 .freeze = amdgpu_pmops_freeze,
1330 .thaw = amdgpu_pmops_thaw,
1331 .poweroff = amdgpu_pmops_poweroff,
1332 .restore = amdgpu_pmops_restore,
1333 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1334 .runtime_resume = amdgpu_pmops_runtime_resume,
1335 .runtime_idle = amdgpu_pmops_runtime_idle,
1336};
1337
1338static int amdgpu_flush(struct file *f, fl_owner_t id)
1339{
1340 struct drm_file *file_priv = f->private_data;
1341 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1342 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1343
1344 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1345 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1346
1347 return timeout >= 0 ? 0 : timeout;
1348}
1349
1350static const struct file_operations amdgpu_driver_kms_fops = {
1351 .owner = THIS_MODULE,
1352 .open = drm_open,
1353 .flush = amdgpu_flush,
1354 .release = drm_release,
1355 .unlocked_ioctl = amdgpu_drm_ioctl,
1356 .mmap = amdgpu_mmap,
1357 .poll = drm_poll,
1358 .read = drm_read,
1359#ifdef CONFIG_COMPAT
1360 .compat_ioctl = amdgpu_kms_compat_ioctl,
1361#endif
1362};
1363
1364int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1365{
1366 struct drm_file *file;
1367
1368 if (!filp)
1369 return -EINVAL;
1370
1371 if (filp->f_op != &amdgpu_driver_kms_fops) {
1372 return -EINVAL;
1373 }
1374
1375 file = filp->private_data;
1376 *fpriv = file->driver_priv;
1377 return 0;
1378}
1379
1380static bool
1381amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
1382 bool in_vblank_irq, int *vpos, int *hpos,
1383 ktime_t *stime, ktime_t *etime,
1384 const struct drm_display_mode *mode)
1385{
1386 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos,
1387 stime, etime, mode);
1388}
1389
1390static struct drm_driver kms_driver = {
1391 .driver_features =
1392 DRIVER_ATOMIC |
1393 DRIVER_GEM |
1394 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
1395 DRIVER_SYNCOBJ_TIMELINE,
1396 .load = amdgpu_driver_load_kms,
1397 .open = amdgpu_driver_open_kms,
1398 .postclose = amdgpu_driver_postclose_kms,
1399 .lastclose = amdgpu_driver_lastclose_kms,
1400 .unload = amdgpu_driver_unload_kms,
1401 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
1402 .enable_vblank = amdgpu_enable_vblank_kms,
1403 .disable_vblank = amdgpu_disable_vblank_kms,
1404 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
1405 .get_scanout_position = amdgpu_get_crtc_scanout_position,
1406 .irq_handler = amdgpu_irq_handler,
1407 .ioctls = amdgpu_ioctls_kms,
1408 .gem_free_object_unlocked = amdgpu_gem_object_free,
1409 .gem_open_object = amdgpu_gem_object_open,
1410 .gem_close_object = amdgpu_gem_object_close,
1411 .dumb_create = amdgpu_mode_dumb_create,
1412 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1413 .fops = &amdgpu_driver_kms_fops,
1414
1415 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1416 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1417 .gem_prime_export = amdgpu_gem_prime_export,
1418 .gem_prime_import = amdgpu_gem_prime_import,
1419 .gem_prime_vmap = amdgpu_gem_prime_vmap,
1420 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
1421 .gem_prime_mmap = amdgpu_gem_prime_mmap,
1422
1423 .name = DRIVER_NAME,
1424 .desc = DRIVER_DESC,
1425 .date = DRIVER_DATE,
1426 .major = KMS_DRIVER_MAJOR,
1427 .minor = KMS_DRIVER_MINOR,
1428 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1429};
1430
1431static struct pci_driver amdgpu_kms_pci_driver = {
1432 .name = DRIVER_NAME,
1433 .id_table = pciidlist,
1434 .probe = amdgpu_pci_probe,
1435 .remove = amdgpu_pci_remove,
1436 .shutdown = amdgpu_pci_shutdown,
1437 .driver.pm = &amdgpu_pm_ops,
1438};
1439
1440
1441
1442static int __init amdgpu_init(void)
1443{
1444 int r;
1445
1446 if (vgacon_text_force()) {
1447 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1448 return -EINVAL;
1449 }
1450
1451 r = amdgpu_sync_init();
1452 if (r)
1453 goto error_sync;
1454
1455 r = amdgpu_fence_slab_init();
1456 if (r)
1457 goto error_fence;
1458
1459 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1460 kms_driver.num_ioctls = amdgpu_max_kms_ioctl;
1461 amdgpu_register_atpx_handler();
1462
1463
1464 amdgpu_amdkfd_init();
1465
1466
1467 return pci_register_driver(&amdgpu_kms_pci_driver);
1468
1469error_fence:
1470 amdgpu_sync_fini();
1471
1472error_sync:
1473 return r;
1474}
1475
1476static void __exit amdgpu_exit(void)
1477{
1478 amdgpu_amdkfd_fini();
1479 pci_unregister_driver(&amdgpu_kms_pci_driver);
1480 amdgpu_unregister_atpx_handler();
1481 amdgpu_sync_fini();
1482 amdgpu_fence_slab_fini();
1483 mmu_notifier_synchronize();
1484}
1485
1486module_init(amdgpu_init);
1487module_exit(amdgpu_exit);
1488
1489MODULE_AUTHOR(DRIVER_AUTHOR);
1490MODULE_DESCRIPTION(DRIVER_DESC);
1491MODULE_LICENSE("GPL and additional rights");
1492