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26#include <linux/firmware.h>
27
28#include "amdgpu.h"
29#include "amdgpu_psp.h"
30#include "amdgpu_ucode.h"
31#include "soc15_common.h"
32#include "psp_v3_1.h"
33#include "psp_v10_0.h"
34#include "psp_v11_0.h"
35#include "psp_v12_0.h"
36
37#include "amdgpu_ras.h"
38
39static void psp_set_funcs(struct amdgpu_device *adev);
40
41static int psp_early_init(void *handle)
42{
43 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
44 struct psp_context *psp = &adev->psp;
45
46 psp_set_funcs(adev);
47
48 switch (adev->asic_type) {
49 case CHIP_VEGA10:
50 case CHIP_VEGA12:
51 psp_v3_1_set_psp_funcs(psp);
52 psp->autoload_supported = false;
53 break;
54 case CHIP_RAVEN:
55 psp_v10_0_set_psp_funcs(psp);
56 psp->autoload_supported = false;
57 break;
58 case CHIP_VEGA20:
59 case CHIP_ARCTURUS:
60 psp_v11_0_set_psp_funcs(psp);
61 psp->autoload_supported = false;
62 break;
63 case CHIP_NAVI10:
64 case CHIP_NAVI14:
65 case CHIP_NAVI12:
66 psp_v11_0_set_psp_funcs(psp);
67 psp->autoload_supported = true;
68 break;
69 case CHIP_RENOIR:
70 psp_v12_0_set_psp_funcs(psp);
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 psp->adev = adev;
77
78 return 0;
79}
80
81static int psp_sw_init(void *handle)
82{
83 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
84 struct psp_context *psp = &adev->psp;
85 int ret;
86
87 ret = psp_init_microcode(psp);
88 if (ret) {
89 DRM_ERROR("Failed to load psp firmware!\n");
90 return ret;
91 }
92
93 ret = psp_mem_training_init(psp);
94 if (ret) {
95 DRM_ERROR("Failed to initialize memory training!\n");
96 return ret;
97 }
98 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
99 if (ret) {
100 DRM_ERROR("Failed to process memory training!\n");
101 return ret;
102 }
103
104 return 0;
105}
106
107static int psp_sw_fini(void *handle)
108{
109 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
110
111 psp_mem_training_fini(&adev->psp);
112 release_firmware(adev->psp.sos_fw);
113 adev->psp.sos_fw = NULL;
114 release_firmware(adev->psp.asd_fw);
115 adev->psp.asd_fw = NULL;
116 if (adev->psp.ta_fw) {
117 release_firmware(adev->psp.ta_fw);
118 adev->psp.ta_fw = NULL;
119 }
120 return 0;
121}
122
123int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
124 uint32_t reg_val, uint32_t mask, bool check_changed)
125{
126 uint32_t val;
127 int i;
128 struct amdgpu_device *adev = psp->adev;
129
130 for (i = 0; i < adev->usec_timeout; i++) {
131 val = RREG32(reg_index);
132 if (check_changed) {
133 if (val != reg_val)
134 return 0;
135 } else {
136 if ((val & mask) == reg_val)
137 return 0;
138 }
139 udelay(1);
140 }
141
142 return -ETIME;
143}
144
145static int
146psp_cmd_submit_buf(struct psp_context *psp,
147 struct amdgpu_firmware_info *ucode,
148 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
149{
150 int ret;
151 int index;
152 int timeout = 2000;
153
154 mutex_lock(&psp->mutex);
155
156 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
157
158 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
159
160 index = atomic_inc_return(&psp->fence_value);
161 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
162 if (ret) {
163 atomic_dec(&psp->fence_value);
164 mutex_unlock(&psp->mutex);
165 return ret;
166 }
167
168 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
169 while (*((unsigned int *)psp->fence_buf) != index) {
170 if (--timeout == 0)
171 break;
172
173
174
175
176
177 if (amdgpu_ras_intr_triggered())
178 break;
179 msleep(1);
180 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
181 }
182
183
184
185
186
187
188
189
190 if (psp->cmd_buf_mem->resp.status || !timeout) {
191 if (ucode)
192 DRM_WARN("failed to load ucode id (%d) ",
193 ucode->ucode_id);
194 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
195 psp->cmd_buf_mem->cmd_id,
196 psp->cmd_buf_mem->resp.status);
197 if (!timeout) {
198 mutex_unlock(&psp->mutex);
199 return -EINVAL;
200 }
201 }
202
203
204 cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
205
206 if (ucode) {
207 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
208 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
209 }
210 mutex_unlock(&psp->mutex);
211
212 return ret;
213}
214
215static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
216 struct psp_gfx_cmd_resp *cmd,
217 uint64_t tmr_mc, uint32_t size)
218{
219 if (psp_support_vmr_ring(psp))
220 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
221 else
222 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
223 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
224 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
225 cmd->cmd.cmd_setup_tmr.buf_size = size;
226}
227
228static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
229 uint64_t pri_buf_mc, uint32_t size)
230{
231 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
232 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
233 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
234 cmd->cmd.cmd_load_toc.toc_size = size;
235}
236
237
238static int psp_load_toc(struct psp_context *psp,
239 uint32_t *tmr_size)
240{
241 int ret;
242 struct psp_gfx_cmd_resp *cmd;
243
244 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
245 if (!cmd)
246 return -ENOMEM;
247
248 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
249 memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
250
251 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
252
253 ret = psp_cmd_submit_buf(psp, NULL, cmd,
254 psp->fence_buf_mc_addr);
255 if (!ret)
256 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
257 kfree(cmd);
258 return ret;
259}
260
261
262static int psp_tmr_init(struct psp_context *psp)
263{
264 int ret;
265 int tmr_size;
266 void *tmr_buf;
267 void **pptr;
268
269
270
271
272
273
274
275
276 tmr_size = PSP_TMR_SIZE;
277
278
279
280 if (!amdgpu_sriov_vf(psp->adev) &&
281 psp->toc_start_addr &&
282 psp->toc_bin_size &&
283 psp->fw_pri_buf) {
284 ret = psp_load_toc(psp, &tmr_size);
285 if (ret) {
286 DRM_ERROR("Failed to load toc\n");
287 return ret;
288 }
289 }
290
291 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
292 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
293 AMDGPU_GEM_DOMAIN_VRAM,
294 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
295
296 return ret;
297}
298
299static int psp_tmr_load(struct psp_context *psp)
300{
301 int ret;
302 struct psp_gfx_cmd_resp *cmd;
303
304 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
305 if (!cmd)
306 return -ENOMEM;
307
308 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
309 amdgpu_bo_size(psp->tmr_bo));
310 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
311 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
312
313 ret = psp_cmd_submit_buf(psp, NULL, cmd,
314 psp->fence_buf_mc_addr);
315
316 kfree(cmd);
317
318 return ret;
319}
320
321static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
322 uint64_t asd_mc, uint32_t size)
323{
324 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
325 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
326 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
327 cmd->cmd.cmd_load_ta.app_len = size;
328
329 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
330 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
331 cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
332}
333
334static int psp_asd_load(struct psp_context *psp)
335{
336 int ret;
337 struct psp_gfx_cmd_resp *cmd;
338
339
340
341
342
343 if (amdgpu_sriov_vf(psp->adev))
344 return 0;
345
346 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
347 if (!cmd)
348 return -ENOMEM;
349
350 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
351 memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
352
353 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
354 psp->asd_ucode_size);
355
356 ret = psp_cmd_submit_buf(psp, NULL, cmd,
357 psp->fence_buf_mc_addr);
358 if (!ret) {
359 psp->asd_context.asd_initialized = true;
360 psp->asd_context.session_id = cmd->resp.session_id;
361 }
362
363 kfree(cmd);
364
365 return ret;
366}
367
368static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
369 uint32_t session_id)
370{
371 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
372 cmd->cmd.cmd_unload_ta.session_id = session_id;
373}
374
375static int psp_asd_unload(struct psp_context *psp)
376{
377 int ret;
378 struct psp_gfx_cmd_resp *cmd;
379
380 if (amdgpu_sriov_vf(psp->adev))
381 return 0;
382
383 if (!psp->asd_context.asd_initialized)
384 return 0;
385
386 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
387 if (!cmd)
388 return -ENOMEM;
389
390 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
391
392 ret = psp_cmd_submit_buf(psp, NULL, cmd,
393 psp->fence_buf_mc_addr);
394 if (!ret)
395 psp->asd_context.asd_initialized = false;
396
397 kfree(cmd);
398
399 return ret;
400}
401
402static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
403 uint32_t id, uint32_t value)
404{
405 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
406 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
407 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
408}
409
410int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
411 uint32_t value)
412{
413 struct psp_gfx_cmd_resp *cmd = NULL;
414 int ret = 0;
415
416 if (reg >= PSP_REG_LAST)
417 return -EINVAL;
418
419 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
420 if (!cmd)
421 return -ENOMEM;
422
423 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
424 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
425
426 kfree(cmd);
427 return ret;
428}
429
430static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
431 uint64_t ta_bin_mc,
432 uint32_t ta_bin_size,
433 uint64_t ta_shared_mc,
434 uint32_t ta_shared_size)
435{
436 cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
437 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
438 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
439 cmd->cmd.cmd_load_ta.app_len = ta_bin_size;
440
441 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
442 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
443 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size;
444}
445
446static int psp_xgmi_init_shared_buf(struct psp_context *psp)
447{
448 int ret;
449
450
451
452
453
454 ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
455 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
456 &psp->xgmi_context.xgmi_shared_bo,
457 &psp->xgmi_context.xgmi_shared_mc_addr,
458 &psp->xgmi_context.xgmi_shared_buf);
459
460 return ret;
461}
462
463static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
464 uint32_t ta_cmd_id,
465 uint32_t session_id)
466{
467 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
468 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
469 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
470}
471
472int psp_ta_invoke(struct psp_context *psp,
473 uint32_t ta_cmd_id,
474 uint32_t session_id)
475{
476 int ret;
477 struct psp_gfx_cmd_resp *cmd;
478
479 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
480 if (!cmd)
481 return -ENOMEM;
482
483 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
484
485 ret = psp_cmd_submit_buf(psp, NULL, cmd,
486 psp->fence_buf_mc_addr);
487
488 kfree(cmd);
489
490 return ret;
491}
492
493static int psp_xgmi_load(struct psp_context *psp)
494{
495 int ret;
496 struct psp_gfx_cmd_resp *cmd;
497
498
499
500
501
502 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
503 if (!cmd)
504 return -ENOMEM;
505
506 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
507 memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
508
509 psp_prep_ta_load_cmd_buf(cmd,
510 psp->fw_pri_mc_addr,
511 psp->ta_xgmi_ucode_size,
512 psp->xgmi_context.xgmi_shared_mc_addr,
513 PSP_XGMI_SHARED_MEM_SIZE);
514
515 ret = psp_cmd_submit_buf(psp, NULL, cmd,
516 psp->fence_buf_mc_addr);
517
518 if (!ret) {
519 psp->xgmi_context.initialized = 1;
520 psp->xgmi_context.session_id = cmd->resp.session_id;
521 }
522
523 kfree(cmd);
524
525 return ret;
526}
527
528static int psp_xgmi_unload(struct psp_context *psp)
529{
530 int ret;
531 struct psp_gfx_cmd_resp *cmd;
532 struct amdgpu_device *adev = psp->adev;
533
534
535 if (adev->asic_type == CHIP_ARCTURUS)
536 return 0;
537
538
539
540
541
542 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
543 if (!cmd)
544 return -ENOMEM;
545
546 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
547
548 ret = psp_cmd_submit_buf(psp, NULL, cmd,
549 psp->fence_buf_mc_addr);
550
551 kfree(cmd);
552
553 return ret;
554}
555
556int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
557{
558 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
559}
560
561static int psp_xgmi_terminate(struct psp_context *psp)
562{
563 int ret;
564
565 if (!psp->xgmi_context.initialized)
566 return 0;
567
568 ret = psp_xgmi_unload(psp);
569 if (ret)
570 return ret;
571
572 psp->xgmi_context.initialized = 0;
573
574
575 amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
576 &psp->xgmi_context.xgmi_shared_mc_addr,
577 &psp->xgmi_context.xgmi_shared_buf);
578
579 return 0;
580}
581
582static int psp_xgmi_initialize(struct psp_context *psp)
583{
584 struct ta_xgmi_shared_memory *xgmi_cmd;
585 int ret;
586
587 if (!psp->adev->psp.ta_fw ||
588 !psp->adev->psp.ta_xgmi_ucode_size ||
589 !psp->adev->psp.ta_xgmi_start_addr)
590 return -ENOENT;
591
592 if (!psp->xgmi_context.initialized) {
593 ret = psp_xgmi_init_shared_buf(psp);
594 if (ret)
595 return ret;
596 }
597
598
599 ret = psp_xgmi_load(psp);
600 if (ret)
601 return ret;
602
603
604 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
605 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
606 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
607
608 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
609
610 return ret;
611}
612
613
614static int psp_ras_init_shared_buf(struct psp_context *psp)
615{
616 int ret;
617
618
619
620
621
622 ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
623 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
624 &psp->ras.ras_shared_bo,
625 &psp->ras.ras_shared_mc_addr,
626 &psp->ras.ras_shared_buf);
627
628 return ret;
629}
630
631static int psp_ras_load(struct psp_context *psp)
632{
633 int ret;
634 struct psp_gfx_cmd_resp *cmd;
635
636
637
638
639 if (amdgpu_sriov_vf(psp->adev))
640 return 0;
641
642 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
643 if (!cmd)
644 return -ENOMEM;
645
646 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
647 memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
648
649 psp_prep_ta_load_cmd_buf(cmd,
650 psp->fw_pri_mc_addr,
651 psp->ta_ras_ucode_size,
652 psp->ras.ras_shared_mc_addr,
653 PSP_RAS_SHARED_MEM_SIZE);
654
655 ret = psp_cmd_submit_buf(psp, NULL, cmd,
656 psp->fence_buf_mc_addr);
657
658 if (!ret) {
659 psp->ras.ras_initialized = true;
660 psp->ras.session_id = cmd->resp.session_id;
661 }
662
663 kfree(cmd);
664
665 return ret;
666}
667
668static int psp_ras_unload(struct psp_context *psp)
669{
670 int ret;
671 struct psp_gfx_cmd_resp *cmd;
672
673
674
675
676 if (amdgpu_sriov_vf(psp->adev))
677 return 0;
678
679 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
680 if (!cmd)
681 return -ENOMEM;
682
683 psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
684
685 ret = psp_cmd_submit_buf(psp, NULL, cmd,
686 psp->fence_buf_mc_addr);
687
688 kfree(cmd);
689
690 return ret;
691}
692
693int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
694{
695
696
697
698 if (amdgpu_sriov_vf(psp->adev))
699 return 0;
700
701 return psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
702}
703
704int psp_ras_enable_features(struct psp_context *psp,
705 union ta_ras_cmd_input *info, bool enable)
706{
707 struct ta_ras_shared_memory *ras_cmd;
708 int ret;
709
710 if (!psp->ras.ras_initialized)
711 return -EINVAL;
712
713 ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
714 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
715
716 if (enable)
717 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
718 else
719 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
720
721 ras_cmd->ras_in_message = *info;
722
723 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
724 if (ret)
725 return -EINVAL;
726
727 return ras_cmd->ras_status;
728}
729
730static int psp_ras_terminate(struct psp_context *psp)
731{
732 int ret;
733
734
735
736
737 if (amdgpu_sriov_vf(psp->adev))
738 return 0;
739
740 if (!psp->ras.ras_initialized)
741 return 0;
742
743 ret = psp_ras_unload(psp);
744 if (ret)
745 return ret;
746
747 psp->ras.ras_initialized = false;
748
749
750 amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
751 &psp->ras.ras_shared_mc_addr,
752 &psp->ras.ras_shared_buf);
753
754 return 0;
755}
756
757static int psp_ras_initialize(struct psp_context *psp)
758{
759 int ret;
760
761
762
763
764 if (amdgpu_sriov_vf(psp->adev))
765 return 0;
766
767 if (!psp->adev->psp.ta_ras_ucode_size ||
768 !psp->adev->psp.ta_ras_start_addr) {
769 dev_warn(psp->adev->dev, "RAS: ras ta ucode is not available\n");
770 return 0;
771 }
772
773 if (!psp->ras.ras_initialized) {
774 ret = psp_ras_init_shared_buf(psp);
775 if (ret)
776 return ret;
777 }
778
779 ret = psp_ras_load(psp);
780 if (ret)
781 return ret;
782
783 return 0;
784}
785
786
787
788static int psp_hdcp_init_shared_buf(struct psp_context *psp)
789{
790 int ret;
791
792
793
794
795
796 ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
797 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
798 &psp->hdcp_context.hdcp_shared_bo,
799 &psp->hdcp_context.hdcp_shared_mc_addr,
800 &psp->hdcp_context.hdcp_shared_buf);
801
802 return ret;
803}
804
805static int psp_hdcp_load(struct psp_context *psp)
806{
807 int ret;
808 struct psp_gfx_cmd_resp *cmd;
809
810
811
812
813 if (amdgpu_sriov_vf(psp->adev))
814 return 0;
815
816 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
817 if (!cmd)
818 return -ENOMEM;
819
820 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
821 memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
822 psp->ta_hdcp_ucode_size);
823
824 psp_prep_ta_load_cmd_buf(cmd,
825 psp->fw_pri_mc_addr,
826 psp->ta_hdcp_ucode_size,
827 psp->hdcp_context.hdcp_shared_mc_addr,
828 PSP_HDCP_SHARED_MEM_SIZE);
829
830 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
831
832 if (!ret) {
833 psp->hdcp_context.hdcp_initialized = true;
834 psp->hdcp_context.session_id = cmd->resp.session_id;
835 }
836
837 kfree(cmd);
838
839 return ret;
840}
841static int psp_hdcp_initialize(struct psp_context *psp)
842{
843 int ret;
844
845
846
847
848 if (amdgpu_sriov_vf(psp->adev))
849 return 0;
850
851 if (!psp->adev->psp.ta_hdcp_ucode_size ||
852 !psp->adev->psp.ta_hdcp_start_addr) {
853 dev_warn(psp->adev->dev, "HDCP: hdcp ta ucode is not available\n");
854 return 0;
855 }
856
857 if (!psp->hdcp_context.hdcp_initialized) {
858 ret = psp_hdcp_init_shared_buf(psp);
859 if (ret)
860 return ret;
861 }
862
863 ret = psp_hdcp_load(psp);
864 if (ret)
865 return ret;
866
867 return 0;
868}
869
870static int psp_hdcp_unload(struct psp_context *psp)
871{
872 int ret;
873 struct psp_gfx_cmd_resp *cmd;
874
875
876
877
878 if (amdgpu_sriov_vf(psp->adev))
879 return 0;
880
881 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
882 if (!cmd)
883 return -ENOMEM;
884
885 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
886
887 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
888
889 kfree(cmd);
890
891 return ret;
892}
893
894int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
895{
896
897
898
899 if (amdgpu_sriov_vf(psp->adev))
900 return 0;
901
902 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
903}
904
905static int psp_hdcp_terminate(struct psp_context *psp)
906{
907 int ret;
908
909
910
911
912 if (amdgpu_sriov_vf(psp->adev))
913 return 0;
914
915 if (!psp->hdcp_context.hdcp_initialized)
916 return 0;
917
918 ret = psp_hdcp_unload(psp);
919 if (ret)
920 return ret;
921
922 psp->hdcp_context.hdcp_initialized = false;
923
924
925 amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
926 &psp->hdcp_context.hdcp_shared_mc_addr,
927 &psp->hdcp_context.hdcp_shared_buf);
928
929 return 0;
930}
931
932
933
934static int psp_dtm_init_shared_buf(struct psp_context *psp)
935{
936 int ret;
937
938
939
940
941
942 ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
943 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
944 &psp->dtm_context.dtm_shared_bo,
945 &psp->dtm_context.dtm_shared_mc_addr,
946 &psp->dtm_context.dtm_shared_buf);
947
948 return ret;
949}
950
951static int psp_dtm_load(struct psp_context *psp)
952{
953 int ret;
954 struct psp_gfx_cmd_resp *cmd;
955
956
957
958
959 if (amdgpu_sriov_vf(psp->adev))
960 return 0;
961
962 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
963 if (!cmd)
964 return -ENOMEM;
965
966 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
967 memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
968
969 psp_prep_ta_load_cmd_buf(cmd,
970 psp->fw_pri_mc_addr,
971 psp->ta_dtm_ucode_size,
972 psp->dtm_context.dtm_shared_mc_addr,
973 PSP_DTM_SHARED_MEM_SIZE);
974
975 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
976
977 if (!ret) {
978 psp->dtm_context.dtm_initialized = true;
979 psp->dtm_context.session_id = cmd->resp.session_id;
980 }
981
982 kfree(cmd);
983
984 return ret;
985}
986
987static int psp_dtm_initialize(struct psp_context *psp)
988{
989 int ret;
990
991
992
993
994 if (amdgpu_sriov_vf(psp->adev))
995 return 0;
996
997 if (!psp->adev->psp.ta_dtm_ucode_size ||
998 !psp->adev->psp.ta_dtm_start_addr) {
999 dev_warn(psp->adev->dev, "DTM: dtm ta ucode is not available\n");
1000 return 0;
1001 }
1002
1003 if (!psp->dtm_context.dtm_initialized) {
1004 ret = psp_dtm_init_shared_buf(psp);
1005 if (ret)
1006 return ret;
1007 }
1008
1009 ret = psp_dtm_load(psp);
1010 if (ret)
1011 return ret;
1012
1013 return 0;
1014}
1015
1016static int psp_dtm_unload(struct psp_context *psp)
1017{
1018 int ret;
1019 struct psp_gfx_cmd_resp *cmd;
1020
1021
1022
1023
1024 if (amdgpu_sriov_vf(psp->adev))
1025 return 0;
1026
1027 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1028 if (!cmd)
1029 return -ENOMEM;
1030
1031 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1032
1033 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1034
1035 kfree(cmd);
1036
1037 return ret;
1038}
1039
1040int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1041{
1042
1043
1044
1045 if (amdgpu_sriov_vf(psp->adev))
1046 return 0;
1047
1048 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1049}
1050
1051static int psp_dtm_terminate(struct psp_context *psp)
1052{
1053 int ret;
1054
1055
1056
1057
1058 if (amdgpu_sriov_vf(psp->adev))
1059 return 0;
1060
1061 if (!psp->dtm_context.dtm_initialized)
1062 return 0;
1063
1064 ret = psp_dtm_unload(psp);
1065 if (ret)
1066 return ret;
1067
1068 psp->dtm_context.dtm_initialized = false;
1069
1070
1071 amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1072 &psp->dtm_context.dtm_shared_mc_addr,
1073 &psp->dtm_context.dtm_shared_buf);
1074
1075 return 0;
1076}
1077
1078
1079static int psp_hw_start(struct psp_context *psp)
1080{
1081 struct amdgpu_device *adev = psp->adev;
1082 int ret;
1083
1084 if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
1085 if (psp->kdb_bin_size &&
1086 (psp->funcs->bootloader_load_kdb != NULL)) {
1087 ret = psp_bootloader_load_kdb(psp);
1088 if (ret) {
1089 DRM_ERROR("PSP load kdb failed!\n");
1090 return ret;
1091 }
1092 }
1093
1094 ret = psp_bootloader_load_sysdrv(psp);
1095 if (ret) {
1096 DRM_ERROR("PSP load sysdrv failed!\n");
1097 return ret;
1098 }
1099
1100 ret = psp_bootloader_load_sos(psp);
1101 if (ret) {
1102 DRM_ERROR("PSP load sos failed!\n");
1103 return ret;
1104 }
1105 }
1106
1107 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1108 if (ret) {
1109 DRM_ERROR("PSP create ring failed!\n");
1110 return ret;
1111 }
1112
1113 ret = psp_tmr_init(psp);
1114 if (ret) {
1115 DRM_ERROR("PSP tmr init failed!\n");
1116 return ret;
1117 }
1118
1119 ret = psp_tmr_load(psp);
1120 if (ret) {
1121 DRM_ERROR("PSP load tmr failed!\n");
1122 return ret;
1123 }
1124
1125 return 0;
1126}
1127
1128static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1129 enum psp_gfx_fw_type *type)
1130{
1131 switch (ucode->ucode_id) {
1132 case AMDGPU_UCODE_ID_SDMA0:
1133 *type = GFX_FW_TYPE_SDMA0;
1134 break;
1135 case AMDGPU_UCODE_ID_SDMA1:
1136 *type = GFX_FW_TYPE_SDMA1;
1137 break;
1138 case AMDGPU_UCODE_ID_SDMA2:
1139 *type = GFX_FW_TYPE_SDMA2;
1140 break;
1141 case AMDGPU_UCODE_ID_SDMA3:
1142 *type = GFX_FW_TYPE_SDMA3;
1143 break;
1144 case AMDGPU_UCODE_ID_SDMA4:
1145 *type = GFX_FW_TYPE_SDMA4;
1146 break;
1147 case AMDGPU_UCODE_ID_SDMA5:
1148 *type = GFX_FW_TYPE_SDMA5;
1149 break;
1150 case AMDGPU_UCODE_ID_SDMA6:
1151 *type = GFX_FW_TYPE_SDMA6;
1152 break;
1153 case AMDGPU_UCODE_ID_SDMA7:
1154 *type = GFX_FW_TYPE_SDMA7;
1155 break;
1156 case AMDGPU_UCODE_ID_CP_CE:
1157 *type = GFX_FW_TYPE_CP_CE;
1158 break;
1159 case AMDGPU_UCODE_ID_CP_PFP:
1160 *type = GFX_FW_TYPE_CP_PFP;
1161 break;
1162 case AMDGPU_UCODE_ID_CP_ME:
1163 *type = GFX_FW_TYPE_CP_ME;
1164 break;
1165 case AMDGPU_UCODE_ID_CP_MEC1:
1166 *type = GFX_FW_TYPE_CP_MEC;
1167 break;
1168 case AMDGPU_UCODE_ID_CP_MEC1_JT:
1169 *type = GFX_FW_TYPE_CP_MEC_ME1;
1170 break;
1171 case AMDGPU_UCODE_ID_CP_MEC2:
1172 *type = GFX_FW_TYPE_CP_MEC;
1173 break;
1174 case AMDGPU_UCODE_ID_CP_MEC2_JT:
1175 *type = GFX_FW_TYPE_CP_MEC_ME2;
1176 break;
1177 case AMDGPU_UCODE_ID_RLC_G:
1178 *type = GFX_FW_TYPE_RLC_G;
1179 break;
1180 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
1181 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
1182 break;
1183 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
1184 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
1185 break;
1186 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
1187 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
1188 break;
1189 case AMDGPU_UCODE_ID_SMC:
1190 *type = GFX_FW_TYPE_SMU;
1191 break;
1192 case AMDGPU_UCODE_ID_UVD:
1193 *type = GFX_FW_TYPE_UVD;
1194 break;
1195 case AMDGPU_UCODE_ID_UVD1:
1196 *type = GFX_FW_TYPE_UVD1;
1197 break;
1198 case AMDGPU_UCODE_ID_VCE:
1199 *type = GFX_FW_TYPE_VCE;
1200 break;
1201 case AMDGPU_UCODE_ID_VCN:
1202 *type = GFX_FW_TYPE_VCN;
1203 break;
1204 case AMDGPU_UCODE_ID_VCN1:
1205 *type = GFX_FW_TYPE_VCN1;
1206 break;
1207 case AMDGPU_UCODE_ID_DMCU_ERAM:
1208 *type = GFX_FW_TYPE_DMCU_ERAM;
1209 break;
1210 case AMDGPU_UCODE_ID_DMCU_INTV:
1211 *type = GFX_FW_TYPE_DMCU_ISR;
1212 break;
1213 case AMDGPU_UCODE_ID_VCN0_RAM:
1214 *type = GFX_FW_TYPE_VCN0_RAM;
1215 break;
1216 case AMDGPU_UCODE_ID_VCN1_RAM:
1217 *type = GFX_FW_TYPE_VCN1_RAM;
1218 break;
1219 case AMDGPU_UCODE_ID_DMCUB:
1220 *type = GFX_FW_TYPE_DMUB;
1221 break;
1222 case AMDGPU_UCODE_ID_MAXIMUM:
1223 default:
1224 return -EINVAL;
1225 }
1226
1227 return 0;
1228}
1229
1230static void psp_print_fw_hdr(struct psp_context *psp,
1231 struct amdgpu_firmware_info *ucode)
1232{
1233 struct amdgpu_device *adev = psp->adev;
1234 struct common_firmware_header *hdr;
1235
1236 switch (ucode->ucode_id) {
1237 case AMDGPU_UCODE_ID_SDMA0:
1238 case AMDGPU_UCODE_ID_SDMA1:
1239 case AMDGPU_UCODE_ID_SDMA2:
1240 case AMDGPU_UCODE_ID_SDMA3:
1241 case AMDGPU_UCODE_ID_SDMA4:
1242 case AMDGPU_UCODE_ID_SDMA5:
1243 case AMDGPU_UCODE_ID_SDMA6:
1244 case AMDGPU_UCODE_ID_SDMA7:
1245 hdr = (struct common_firmware_header *)
1246 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
1247 amdgpu_ucode_print_sdma_hdr(hdr);
1248 break;
1249 case AMDGPU_UCODE_ID_CP_CE:
1250 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
1251 amdgpu_ucode_print_gfx_hdr(hdr);
1252 break;
1253 case AMDGPU_UCODE_ID_CP_PFP:
1254 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
1255 amdgpu_ucode_print_gfx_hdr(hdr);
1256 break;
1257 case AMDGPU_UCODE_ID_CP_ME:
1258 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
1259 amdgpu_ucode_print_gfx_hdr(hdr);
1260 break;
1261 case AMDGPU_UCODE_ID_CP_MEC1:
1262 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
1263 amdgpu_ucode_print_gfx_hdr(hdr);
1264 break;
1265 case AMDGPU_UCODE_ID_RLC_G:
1266 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
1267 amdgpu_ucode_print_rlc_hdr(hdr);
1268 break;
1269 case AMDGPU_UCODE_ID_SMC:
1270 hdr = (struct common_firmware_header *)adev->pm.fw->data;
1271 amdgpu_ucode_print_smc_hdr(hdr);
1272 break;
1273 default:
1274 break;
1275 }
1276}
1277
1278static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
1279 struct psp_gfx_cmd_resp *cmd)
1280{
1281 int ret;
1282 uint64_t fw_mem_mc_addr = ucode->mc_addr;
1283
1284 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
1285
1286 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1287 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
1288 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
1289 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
1290
1291 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
1292 if (ret)
1293 DRM_ERROR("Unknown firmware type\n");
1294
1295 return ret;
1296}
1297
1298static int psp_execute_np_fw_load(struct psp_context *psp,
1299 struct amdgpu_firmware_info *ucode)
1300{
1301 int ret = 0;
1302
1303 ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
1304 if (ret)
1305 return ret;
1306
1307 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
1308 psp->fence_buf_mc_addr);
1309
1310 return ret;
1311}
1312
1313static int psp_np_fw_load(struct psp_context *psp)
1314{
1315 int i, ret;
1316 struct amdgpu_firmware_info *ucode;
1317 struct amdgpu_device* adev = psp->adev;
1318
1319 if (psp->autoload_supported) {
1320 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
1321 if (!ucode->fw)
1322 goto out;
1323
1324 ret = psp_execute_np_fw_load(psp, ucode);
1325 if (ret)
1326 return ret;
1327 }
1328
1329out:
1330 for (i = 0; i < adev->firmware.max_ucodes; i++) {
1331 ucode = &adev->firmware.ucode[i];
1332 if (!ucode->fw)
1333 continue;
1334
1335 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
1336 (psp_smu_reload_quirk(psp) || psp->autoload_supported))
1337 continue;
1338
1339 if (amdgpu_sriov_vf(adev) &&
1340 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
1341 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
1342 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
1343 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
1344 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
1345 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
1346 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
1347 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
1348 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
1349 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
1350 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
1351 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
1352 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
1353
1354 continue;
1355
1356 if (psp->autoload_supported &&
1357 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
1358 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
1359
1360 continue;
1361
1362 psp_print_fw_hdr(psp, ucode);
1363
1364 ret = psp_execute_np_fw_load(psp, ucode);
1365 if (ret)
1366 return ret;
1367
1368
1369 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
1370 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
1371 ret = psp_rlc_autoload(psp);
1372 if (ret) {
1373 DRM_ERROR("Failed to start rlc autoload\n");
1374 return ret;
1375 }
1376 }
1377#if 0
1378
1379 if (!amdgpu_psp_check_fw_loading_status(adev, i))
1380 return -EINVAL;
1381#endif
1382 }
1383
1384 return 0;
1385}
1386
1387static int psp_load_fw(struct amdgpu_device *adev)
1388{
1389 int ret;
1390 struct psp_context *psp = &adev->psp;
1391
1392 if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset) {
1393 psp_ring_stop(psp, PSP_RING_TYPE__KM);
1394 goto skip_memalloc;
1395 }
1396
1397 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1398 if (!psp->cmd)
1399 return -ENOMEM;
1400
1401 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
1402 AMDGPU_GEM_DOMAIN_GTT,
1403 &psp->fw_pri_bo,
1404 &psp->fw_pri_mc_addr,
1405 &psp->fw_pri_buf);
1406 if (ret)
1407 goto failed;
1408
1409 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
1410 AMDGPU_GEM_DOMAIN_VRAM,
1411 &psp->fence_buf_bo,
1412 &psp->fence_buf_mc_addr,
1413 &psp->fence_buf);
1414 if (ret)
1415 goto failed;
1416
1417 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
1418 AMDGPU_GEM_DOMAIN_VRAM,
1419 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1420 (void **)&psp->cmd_buf_mem);
1421 if (ret)
1422 goto failed;
1423
1424 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
1425
1426 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
1427 if (ret) {
1428 DRM_ERROR("PSP ring init failed!\n");
1429 goto failed;
1430 }
1431
1432skip_memalloc:
1433 ret = psp_hw_start(psp);
1434 if (ret)
1435 goto failed;
1436
1437 ret = psp_np_fw_load(psp);
1438 if (ret)
1439 goto failed;
1440
1441 ret = psp_asd_load(psp);
1442 if (ret) {
1443 DRM_ERROR("PSP load asd failed!\n");
1444 return ret;
1445 }
1446
1447 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1448 ret = psp_xgmi_initialize(psp);
1449
1450
1451
1452 if (ret)
1453 dev_err(psp->adev->dev,
1454 "XGMI: Failed to initialize XGMI session\n");
1455 }
1456
1457 if (psp->adev->psp.ta_fw) {
1458 ret = psp_ras_initialize(psp);
1459 if (ret)
1460 dev_err(psp->adev->dev,
1461 "RAS: Failed to initialize RAS\n");
1462
1463 ret = psp_hdcp_initialize(psp);
1464 if (ret)
1465 dev_err(psp->adev->dev,
1466 "HDCP: Failed to initialize HDCP\n");
1467
1468 ret = psp_dtm_initialize(psp);
1469 if (ret)
1470 dev_err(psp->adev->dev,
1471 "DTM: Failed to initialize DTM\n");
1472 }
1473
1474 return 0;
1475
1476failed:
1477
1478
1479
1480
1481
1482 return ret;
1483}
1484
1485static int psp_hw_init(void *handle)
1486{
1487 int ret;
1488 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1489
1490 mutex_lock(&adev->firmware.mutex);
1491
1492
1493
1494
1495 ret = amdgpu_ucode_init_bo(adev);
1496 if (ret)
1497 goto failed;
1498
1499 ret = psp_load_fw(adev);
1500 if (ret) {
1501 DRM_ERROR("PSP firmware loading failed\n");
1502 goto failed;
1503 }
1504
1505 mutex_unlock(&adev->firmware.mutex);
1506 return 0;
1507
1508failed:
1509 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
1510 mutex_unlock(&adev->firmware.mutex);
1511 return -EINVAL;
1512}
1513
1514static int psp_hw_fini(void *handle)
1515{
1516 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1517 struct psp_context *psp = &adev->psp;
1518 void *tmr_buf;
1519 void **pptr;
1520
1521 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1522 psp->xgmi_context.initialized == 1)
1523 psp_xgmi_terminate(psp);
1524
1525 if (psp->adev->psp.ta_fw) {
1526 psp_ras_terminate(psp);
1527 psp_dtm_terminate(psp);
1528 psp_hdcp_terminate(psp);
1529 }
1530
1531 psp_asd_unload(psp);
1532
1533 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
1534
1535 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
1536 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
1537 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
1538 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
1539 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
1540 &psp->fence_buf_mc_addr, &psp->fence_buf);
1541 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
1542 (void **)&psp->cmd_buf_mem);
1543
1544 kfree(psp->cmd);
1545 psp->cmd = NULL;
1546
1547 return 0;
1548}
1549
1550static int psp_suspend(void *handle)
1551{
1552 int ret;
1553 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1554 struct psp_context *psp = &adev->psp;
1555
1556 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1557 psp->xgmi_context.initialized == 1) {
1558 ret = psp_xgmi_terminate(psp);
1559 if (ret) {
1560 DRM_ERROR("Failed to terminate xgmi ta\n");
1561 return ret;
1562 }
1563 }
1564
1565 if (psp->adev->psp.ta_fw) {
1566 ret = psp_ras_terminate(psp);
1567 if (ret) {
1568 DRM_ERROR("Failed to terminate ras ta\n");
1569 return ret;
1570 }
1571 ret = psp_hdcp_terminate(psp);
1572 if (ret) {
1573 DRM_ERROR("Failed to terminate hdcp ta\n");
1574 return ret;
1575 }
1576 ret = psp_dtm_terminate(psp);
1577 if (ret) {
1578 DRM_ERROR("Failed to terminate dtm ta\n");
1579 return ret;
1580 }
1581 }
1582
1583 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
1584 if (ret) {
1585 DRM_ERROR("PSP ring stop failed\n");
1586 return ret;
1587 }
1588
1589 return 0;
1590}
1591
1592static int psp_resume(void *handle)
1593{
1594 int ret;
1595 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1596 struct psp_context *psp = &adev->psp;
1597
1598 DRM_INFO("PSP is resuming...\n");
1599
1600 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
1601 if (ret) {
1602 DRM_ERROR("Failed to process memory training!\n");
1603 return ret;
1604 }
1605
1606 mutex_lock(&adev->firmware.mutex);
1607
1608 ret = psp_hw_start(psp);
1609 if (ret)
1610 goto failed;
1611
1612 ret = psp_np_fw_load(psp);
1613 if (ret)
1614 goto failed;
1615
1616 ret = psp_asd_load(psp);
1617 if (ret) {
1618 DRM_ERROR("PSP load asd failed!\n");
1619 goto failed;
1620 }
1621
1622 if (adev->gmc.xgmi.num_physical_nodes > 1) {
1623 ret = psp_xgmi_initialize(psp);
1624
1625
1626
1627 if (ret)
1628 dev_err(psp->adev->dev,
1629 "XGMI: Failed to initialize XGMI session\n");
1630 }
1631
1632 if (psp->adev->psp.ta_fw) {
1633 ret = psp_ras_initialize(psp);
1634 if (ret)
1635 dev_err(psp->adev->dev,
1636 "RAS: Failed to initialize RAS\n");
1637
1638 ret = psp_hdcp_initialize(psp);
1639 if (ret)
1640 dev_err(psp->adev->dev,
1641 "HDCP: Failed to initialize HDCP\n");
1642
1643 ret = psp_dtm_initialize(psp);
1644 if (ret)
1645 dev_err(psp->adev->dev,
1646 "DTM: Failed to initialize DTM\n");
1647 }
1648
1649 mutex_unlock(&adev->firmware.mutex);
1650
1651 return 0;
1652
1653failed:
1654 DRM_ERROR("PSP resume failed\n");
1655 mutex_unlock(&adev->firmware.mutex);
1656 return ret;
1657}
1658
1659int psp_gpu_reset(struct amdgpu_device *adev)
1660{
1661 int ret;
1662
1663 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1664 return 0;
1665
1666 mutex_lock(&adev->psp.mutex);
1667 ret = psp_mode1_reset(&adev->psp);
1668 mutex_unlock(&adev->psp.mutex);
1669
1670 return ret;
1671}
1672
1673int psp_rlc_autoload_start(struct psp_context *psp)
1674{
1675 int ret;
1676 struct psp_gfx_cmd_resp *cmd;
1677
1678 cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1679 if (!cmd)
1680 return -ENOMEM;
1681
1682 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
1683
1684 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1685 psp->fence_buf_mc_addr);
1686 kfree(cmd);
1687 return ret;
1688}
1689
1690int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
1691 uint64_t cmd_gpu_addr, int cmd_size)
1692{
1693 struct amdgpu_firmware_info ucode = {0};
1694
1695 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
1696 AMDGPU_UCODE_ID_VCN0_RAM;
1697 ucode.mc_addr = cmd_gpu_addr;
1698 ucode.ucode_size = cmd_size;
1699
1700 return psp_execute_np_fw_load(&adev->psp, &ucode);
1701}
1702
1703int psp_ring_cmd_submit(struct psp_context *psp,
1704 uint64_t cmd_buf_mc_addr,
1705 uint64_t fence_mc_addr,
1706 int index)
1707{
1708 unsigned int psp_write_ptr_reg = 0;
1709 struct psp_gfx_rb_frame *write_frame;
1710 struct psp_ring *ring = &psp->km_ring;
1711 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
1712 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
1713 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
1714 struct amdgpu_device *adev = psp->adev;
1715 uint32_t ring_size_dw = ring->ring_size / 4;
1716 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
1717
1718
1719 psp_write_ptr_reg = psp_ring_get_wptr(psp);
1720
1721
1722
1723
1724 if ((psp_write_ptr_reg % ring_size_dw) == 0)
1725 write_frame = ring_buffer_start;
1726 else
1727 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
1728
1729 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
1730 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
1731 ring_buffer_start, ring_buffer_end, write_frame);
1732 DRM_ERROR("write_frame is pointing to address out of bounds\n");
1733 return -EINVAL;
1734 }
1735
1736
1737 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
1738
1739
1740 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
1741 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
1742 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
1743 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
1744 write_frame->fence_value = index;
1745 amdgpu_asic_flush_hdp(adev, NULL);
1746
1747
1748 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
1749 psp_ring_set_wptr(psp, psp_write_ptr_reg);
1750 return 0;
1751}
1752
1753static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
1754 enum AMDGPU_UCODE_ID ucode_type)
1755{
1756 struct amdgpu_firmware_info *ucode = NULL;
1757
1758 if (!adev->firmware.fw_size)
1759 return false;
1760
1761 ucode = &adev->firmware.ucode[ucode_type];
1762 if (!ucode->fw || !ucode->ucode_size)
1763 return false;
1764
1765 return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
1766}
1767
1768static int psp_set_clockgating_state(void *handle,
1769 enum amd_clockgating_state state)
1770{
1771 return 0;
1772}
1773
1774static int psp_set_powergating_state(void *handle,
1775 enum amd_powergating_state state)
1776{
1777 return 0;
1778}
1779
1780const struct amd_ip_funcs psp_ip_funcs = {
1781 .name = "psp",
1782 .early_init = psp_early_init,
1783 .late_init = NULL,
1784 .sw_init = psp_sw_init,
1785 .sw_fini = psp_sw_fini,
1786 .hw_init = psp_hw_init,
1787 .hw_fini = psp_hw_fini,
1788 .suspend = psp_suspend,
1789 .resume = psp_resume,
1790 .is_idle = NULL,
1791 .check_soft_reset = NULL,
1792 .wait_for_idle = NULL,
1793 .soft_reset = NULL,
1794 .set_clockgating_state = psp_set_clockgating_state,
1795 .set_powergating_state = psp_set_powergating_state,
1796};
1797
1798static const struct amdgpu_psp_funcs psp_funcs = {
1799 .check_fw_loading_status = psp_check_fw_loading_status,
1800};
1801
1802static void psp_set_funcs(struct amdgpu_device *adev)
1803{
1804 if (NULL == adev->firmware.funcs)
1805 adev->firmware.funcs = &psp_funcs;
1806}
1807
1808const struct amdgpu_ip_block_version psp_v3_1_ip_block =
1809{
1810 .type = AMD_IP_BLOCK_TYPE_PSP,
1811 .major = 3,
1812 .minor = 1,
1813 .rev = 0,
1814 .funcs = &psp_ip_funcs,
1815};
1816
1817const struct amdgpu_ip_block_version psp_v10_0_ip_block =
1818{
1819 .type = AMD_IP_BLOCK_TYPE_PSP,
1820 .major = 10,
1821 .minor = 0,
1822 .rev = 0,
1823 .funcs = &psp_ip_funcs,
1824};
1825
1826const struct amdgpu_ip_block_version psp_v11_0_ip_block =
1827{
1828 .type = AMD_IP_BLOCK_TYPE_PSP,
1829 .major = 11,
1830 .minor = 0,
1831 .rev = 0,
1832 .funcs = &psp_ip_funcs,
1833};
1834
1835const struct amdgpu_ip_block_version psp_v12_0_ip_block =
1836{
1837 .type = AMD_IP_BLOCK_TYPE_PSP,
1838 .major = 12,
1839 .minor = 0,
1840 .rev = 0,
1841 .funcs = &psp_ip_funcs,
1842};
1843
