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24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "amdgpu.h"
30#include "amdgpu_gfx.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_smu.h"
33#include "nv.h"
34#include "nvd.h"
35
36#include "gc/gc_10_1_0_offset.h"
37#include "gc/gc_10_1_0_sh_mask.h"
38#include "navi10_enum.h"
39#include "hdp/hdp_5_0_0_offset.h"
40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42#include "soc15.h"
43#include "soc15d.h"
44#include "soc15_common.h"
45#include "clearstate_gfx10.h"
46#include "v10_structs.h"
47#include "gfx_v10_0.h"
48#include "nbio_v2_3.h"
49
50
51
52
53
54
55#define GFX10_NUM_GFX_RINGS_NV1X 1
56#define GFX10_MEC_HPD_SIZE 2048
57
58#define F32_CE_PROGRAM_RAM_SIZE 65536
59#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
60
61#define mmCGTT_GS_NGG_CLK_CTRL 0x5087
62#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
63
64MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
65MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
66MODULE_FIRMWARE("amdgpu/navi10_me.bin");
67MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
68MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
69MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
70
71MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
72MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
73MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
74MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
75MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
76MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
77MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
78MODULE_FIRMWARE("amdgpu/navi14_me.bin");
79MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
80MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
81MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
82
83MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
84MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
85MODULE_FIRMWARE("amdgpu/navi12_me.bin");
86MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
87MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
88MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
89
90static const struct soc15_reg_golden golden_settings_gc_10_1[] =
91{
92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
132};
133
134static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
135{
136
137};
138
139static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
140{
141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
179};
180
181static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
182{
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
223};
224
225static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
226{
227
228};
229
230static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
231{
232
233};
234
235#define DEFAULT_SH_MEM_CONFIG \
236 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
237 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
238 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
239 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
240
241
242static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
243static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
244static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
245static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
246static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
247 struct amdgpu_cu_info *cu_info);
248static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
249static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
250 u32 sh_num, u32 instance);
251static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
252
253static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
254static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
255static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
256static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
257static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
258static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
259static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start);
260
261static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
262{
263 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
264 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
265 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
266 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));
267 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));
268 amdgpu_ring_write(kiq_ring, 0);
269 amdgpu_ring_write(kiq_ring, 0);
270 amdgpu_ring_write(kiq_ring, 0);
271 amdgpu_ring_write(kiq_ring, 0);
272}
273
274static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
275 struct amdgpu_ring *ring)
276{
277 struct amdgpu_device *adev = kiq_ring->adev;
278 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
279 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
280 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
281
282 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
283
284 amdgpu_ring_write(kiq_ring,
285 PACKET3_MAP_QUEUES_QUEUE_SEL(0) |
286 PACKET3_MAP_QUEUES_VMID(0) |
287 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
288 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
289 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
290 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
291 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
292 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
293 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
294 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
295 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
296 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
297 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
298 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
299}
300
301static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
302 struct amdgpu_ring *ring,
303 enum amdgpu_unmap_queues_action action,
304 u64 gpu_addr, u64 seq)
305{
306 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
307
308 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
309 amdgpu_ring_write(kiq_ring,
310 PACKET3_UNMAP_QUEUES_ACTION(action) |
311 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
312 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
313 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
314 amdgpu_ring_write(kiq_ring,
315 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
316
317 if (action == PREEMPT_QUEUES_NO_UNMAP) {
318 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
319 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
320 amdgpu_ring_write(kiq_ring, seq);
321 } else {
322 amdgpu_ring_write(kiq_ring, 0);
323 amdgpu_ring_write(kiq_ring, 0);
324 amdgpu_ring_write(kiq_ring, 0);
325 }
326}
327
328static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
329 struct amdgpu_ring *ring,
330 u64 addr,
331 u64 seq)
332{
333 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
334
335 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
336 amdgpu_ring_write(kiq_ring,
337 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
338 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
339 PACKET3_QUERY_STATUS_COMMAND(2));
340 amdgpu_ring_write(kiq_ring,
341 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
342 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
343 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
344 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
345 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
346 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
347}
348
349static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
350 uint16_t pasid, uint32_t flush_type,
351 bool all_hub)
352{
353 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
354 amdgpu_ring_write(kiq_ring,
355 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
356 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
357 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
358 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
359}
360
361static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
362 .kiq_set_resources = gfx10_kiq_set_resources,
363 .kiq_map_queues = gfx10_kiq_map_queues,
364 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
365 .kiq_query_status = gfx10_kiq_query_status,
366 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
367 .set_resources_size = 8,
368 .map_queues_size = 7,
369 .unmap_queues_size = 6,
370 .query_status_size = 7,
371 .invalidate_tlbs_size = 2,
372};
373
374static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
375{
376 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
377}
378
379static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
380{
381 switch (adev->asic_type) {
382 case CHIP_NAVI10:
383 soc15_program_register_sequence(adev,
384 golden_settings_gc_10_1,
385 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
386 soc15_program_register_sequence(adev,
387 golden_settings_gc_10_0_nv10,
388 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
389 break;
390 case CHIP_NAVI14:
391 soc15_program_register_sequence(adev,
392 golden_settings_gc_10_1_1,
393 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
394 soc15_program_register_sequence(adev,
395 golden_settings_gc_10_1_nv14,
396 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
397 break;
398 case CHIP_NAVI12:
399 soc15_program_register_sequence(adev,
400 golden_settings_gc_10_1_2,
401 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
402 soc15_program_register_sequence(adev,
403 golden_settings_gc_10_1_2_nv12,
404 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
405 break;
406 default:
407 break;
408 }
409}
410
411static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
412{
413 adev->gfx.scratch.num_reg = 8;
414 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
415 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
416}
417
418static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
419 bool wc, uint32_t reg, uint32_t val)
420{
421 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
422 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
423 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
424 amdgpu_ring_write(ring, reg);
425 amdgpu_ring_write(ring, 0);
426 amdgpu_ring_write(ring, val);
427}
428
429static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
430 int mem_space, int opt, uint32_t addr0,
431 uint32_t addr1, uint32_t ref, uint32_t mask,
432 uint32_t inv)
433{
434 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
435 amdgpu_ring_write(ring,
436
437 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
438 WAIT_REG_MEM_OPERATION(opt) |
439 WAIT_REG_MEM_FUNCTION(3) |
440 WAIT_REG_MEM_ENGINE(eng_sel)));
441
442 if (mem_space)
443 BUG_ON(addr0 & 0x3);
444 amdgpu_ring_write(ring, addr0);
445 amdgpu_ring_write(ring, addr1);
446 amdgpu_ring_write(ring, ref);
447 amdgpu_ring_write(ring, mask);
448 amdgpu_ring_write(ring, inv);
449}
450
451static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
452{
453 struct amdgpu_device *adev = ring->adev;
454 uint32_t scratch;
455 uint32_t tmp = 0;
456 unsigned i;
457 int r;
458
459 r = amdgpu_gfx_scratch_get(adev, &scratch);
460 if (r) {
461 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
462 return r;
463 }
464
465 WREG32(scratch, 0xCAFEDEAD);
466
467 r = amdgpu_ring_alloc(ring, 3);
468 if (r) {
469 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
470 ring->idx, r);
471 amdgpu_gfx_scratch_free(adev, scratch);
472 return r;
473 }
474
475 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
476 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
477 amdgpu_ring_write(ring, 0xDEADBEEF);
478 amdgpu_ring_commit(ring);
479
480 for (i = 0; i < adev->usec_timeout; i++) {
481 tmp = RREG32(scratch);
482 if (tmp == 0xDEADBEEF)
483 break;
484 if (amdgpu_emu_mode == 1)
485 msleep(1);
486 else
487 udelay(1);
488 }
489
490 if (i >= adev->usec_timeout)
491 r = -ETIMEDOUT;
492
493 amdgpu_gfx_scratch_free(adev, scratch);
494
495 return r;
496}
497
498static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
499{
500 struct amdgpu_device *adev = ring->adev;
501 struct amdgpu_ib ib;
502 struct dma_fence *f = NULL;
503 uint32_t scratch;
504 uint32_t tmp = 0;
505 long r;
506
507 r = amdgpu_gfx_scratch_get(adev, &scratch);
508 if (r) {
509 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
510 return r;
511 }
512
513 WREG32(scratch, 0xCAFEDEAD);
514
515 memset(&ib, 0, sizeof(ib));
516 r = amdgpu_ib_get(adev, NULL, 256, &ib);
517 if (r) {
518 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
519 goto err1;
520 }
521
522 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
523 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
524 ib.ptr[2] = 0xDEADBEEF;
525 ib.length_dw = 3;
526
527 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
528 if (r)
529 goto err2;
530
531 r = dma_fence_wait_timeout(f, false, timeout);
532 if (r == 0) {
533 DRM_ERROR("amdgpu: IB test timed out.\n");
534 r = -ETIMEDOUT;
535 goto err2;
536 } else if (r < 0) {
537 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
538 goto err2;
539 }
540
541 tmp = RREG32(scratch);
542 if (tmp == 0xDEADBEEF)
543 r = 0;
544 else
545 r = -EINVAL;
546err2:
547 amdgpu_ib_free(adev, &ib, NULL);
548 dma_fence_put(f);
549err1:
550 amdgpu_gfx_scratch_free(adev, scratch);
551
552 return r;
553}
554
555static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
556{
557 release_firmware(adev->gfx.pfp_fw);
558 adev->gfx.pfp_fw = NULL;
559 release_firmware(adev->gfx.me_fw);
560 adev->gfx.me_fw = NULL;
561 release_firmware(adev->gfx.ce_fw);
562 adev->gfx.ce_fw = NULL;
563 release_firmware(adev->gfx.rlc_fw);
564 adev->gfx.rlc_fw = NULL;
565 release_firmware(adev->gfx.mec_fw);
566 adev->gfx.mec_fw = NULL;
567 release_firmware(adev->gfx.mec2_fw);
568 adev->gfx.mec2_fw = NULL;
569
570 kfree(adev->gfx.rlc.register_list_format);
571}
572
573static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
574{
575 adev->gfx.cp_fw_write_wait = false;
576
577 switch (adev->asic_type) {
578 case CHIP_NAVI10:
579 case CHIP_NAVI12:
580 case CHIP_NAVI14:
581 if ((adev->gfx.me_fw_version >= 0x00000046) &&
582 (adev->gfx.me_feature_version >= 27) &&
583 (adev->gfx.pfp_fw_version >= 0x00000068) &&
584 (adev->gfx.pfp_feature_version >= 27) &&
585 (adev->gfx.mec_fw_version >= 0x0000005b) &&
586 (adev->gfx.mec_feature_version >= 27))
587 adev->gfx.cp_fw_write_wait = true;
588 break;
589 default:
590 break;
591 }
592
593 if (adev->gfx.cp_fw_write_wait == false)
594 DRM_WARN_ONCE("CP firmware version too old, please update!");
595}
596
597
598static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
599{
600 const struct rlc_firmware_header_v2_1 *rlc_hdr;
601
602 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
603 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
604 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
605 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
606 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
607 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
608 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
609 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
610 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
611 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
612 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
613 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
614 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
615 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
616 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
617}
618
619static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
620{
621 bool ret = false;
622
623 switch (adev->pdev->revision) {
624 case 0xc2:
625 case 0xc3:
626 ret = true;
627 break;
628 default:
629 ret = false;
630 break;
631 }
632
633 return ret ;
634}
635
636static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
637{
638 switch (adev->asic_type) {
639 case CHIP_NAVI10:
640 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
641 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
642 break;
643 default:
644 break;
645 }
646}
647
648static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
649{
650 const char *chip_name;
651 char fw_name[40];
652 char wks[10];
653 int err;
654 struct amdgpu_firmware_info *info = NULL;
655 const struct common_firmware_header *header = NULL;
656 const struct gfx_firmware_header_v1_0 *cp_hdr;
657 const struct rlc_firmware_header_v2_0 *rlc_hdr;
658 unsigned int *tmp = NULL;
659 unsigned int i = 0;
660 uint16_t version_major;
661 uint16_t version_minor;
662
663 DRM_DEBUG("\n");
664
665 memset(wks, 0, sizeof(wks));
666 switch (adev->asic_type) {
667 case CHIP_NAVI10:
668 chip_name = "navi10";
669 break;
670 case CHIP_NAVI14:
671 chip_name = "navi14";
672 if (!(adev->pdev->device == 0x7340 &&
673 adev->pdev->revision != 0x00))
674 snprintf(wks, sizeof(wks), "_wks");
675 break;
676 case CHIP_NAVI12:
677 chip_name = "navi12";
678 break;
679 default:
680 BUG();
681 }
682
683 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
684 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
685 if (err)
686 goto out;
687 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
688 if (err)
689 goto out;
690 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
691 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
692 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
693
694 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
695 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
696 if (err)
697 goto out;
698 err = amdgpu_ucode_validate(adev->gfx.me_fw);
699 if (err)
700 goto out;
701 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
702 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
703 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
704
705 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
706 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
707 if (err)
708 goto out;
709 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
710 if (err)
711 goto out;
712 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
713 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
714 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
715
716 if (!amdgpu_sriov_vf(adev)) {
717 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
718 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
719 if (err)
720 goto out;
721 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
722 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
723 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
724 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
725 if (version_major == 2 && version_minor == 1)
726 adev->gfx.rlc.is_rlc_v2_1 = true;
727
728 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
729 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
730 adev->gfx.rlc.save_and_restore_offset =
731 le32_to_cpu(rlc_hdr->save_and_restore_offset);
732 adev->gfx.rlc.clear_state_descriptor_offset =
733 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
734 adev->gfx.rlc.avail_scratch_ram_locations =
735 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
736 adev->gfx.rlc.reg_restore_list_size =
737 le32_to_cpu(rlc_hdr->reg_restore_list_size);
738 adev->gfx.rlc.reg_list_format_start =
739 le32_to_cpu(rlc_hdr->reg_list_format_start);
740 adev->gfx.rlc.reg_list_format_separate_start =
741 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
742 adev->gfx.rlc.starting_offsets_start =
743 le32_to_cpu(rlc_hdr->starting_offsets_start);
744 adev->gfx.rlc.reg_list_format_size_bytes =
745 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
746 adev->gfx.rlc.reg_list_size_bytes =
747 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
748 adev->gfx.rlc.register_list_format =
749 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
750 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
751 if (!adev->gfx.rlc.register_list_format) {
752 err = -ENOMEM;
753 goto out;
754 }
755
756 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
757 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
758 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
759 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
760
761 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
762
763 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
764 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
765 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
766 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
767
768 if (adev->gfx.rlc.is_rlc_v2_1)
769 gfx_v10_0_init_rlc_ext_microcode(adev);
770 }
771
772 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
773 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
774 if (err)
775 goto out;
776 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
777 if (err)
778 goto out;
779 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
780 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
781 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
782
783 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
784 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
785 if (!err) {
786 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
787 if (err)
788 goto out;
789 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
790 adev->gfx.mec2_fw->data;
791 adev->gfx.mec2_fw_version =
792 le32_to_cpu(cp_hdr->header.ucode_version);
793 adev->gfx.mec2_feature_version =
794 le32_to_cpu(cp_hdr->ucode_feature_version);
795 } else {
796 err = 0;
797 adev->gfx.mec2_fw = NULL;
798 }
799
800 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
801 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
802 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
803 info->fw = adev->gfx.pfp_fw;
804 header = (const struct common_firmware_header *)info->fw->data;
805 adev->firmware.fw_size +=
806 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
807
808 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
809 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
810 info->fw = adev->gfx.me_fw;
811 header = (const struct common_firmware_header *)info->fw->data;
812 adev->firmware.fw_size +=
813 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
814
815 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
816 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
817 info->fw = adev->gfx.ce_fw;
818 header = (const struct common_firmware_header *)info->fw->data;
819 adev->firmware.fw_size +=
820 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
821
822 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
823 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
824 info->fw = adev->gfx.rlc_fw;
825 if (info->fw) {
826 header = (const struct common_firmware_header *)info->fw->data;
827 adev->firmware.fw_size +=
828 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
829 }
830 if (adev->gfx.rlc.is_rlc_v2_1 &&
831 adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
832 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
833 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
834 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
835 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
836 info->fw = adev->gfx.rlc_fw;
837 adev->firmware.fw_size +=
838 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
839
840 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
841 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
842 info->fw = adev->gfx.rlc_fw;
843 adev->firmware.fw_size +=
844 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
845
846 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
847 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
848 info->fw = adev->gfx.rlc_fw;
849 adev->firmware.fw_size +=
850 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
851 }
852
853 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
854 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
855 info->fw = adev->gfx.mec_fw;
856 header = (const struct common_firmware_header *)info->fw->data;
857 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
858 adev->firmware.fw_size +=
859 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
860 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
861
862 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
863 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
864 info->fw = adev->gfx.mec_fw;
865 adev->firmware.fw_size +=
866 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
867
868 if (adev->gfx.mec2_fw) {
869 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
870 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
871 info->fw = adev->gfx.mec2_fw;
872 header = (const struct common_firmware_header *)info->fw->data;
873 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
874 adev->firmware.fw_size +=
875 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
876 le32_to_cpu(cp_hdr->jt_size) * 4,
877 PAGE_SIZE);
878 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
879 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
880 info->fw = adev->gfx.mec2_fw;
881 adev->firmware.fw_size +=
882 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
883 PAGE_SIZE);
884 }
885 }
886
887 gfx_v10_0_check_fw_write_wait(adev);
888out:
889 if (err) {
890 dev_err(adev->dev,
891 "gfx10: Failed to load firmware \"%s\"\n",
892 fw_name);
893 release_firmware(adev->gfx.pfp_fw);
894 adev->gfx.pfp_fw = NULL;
895 release_firmware(adev->gfx.me_fw);
896 adev->gfx.me_fw = NULL;
897 release_firmware(adev->gfx.ce_fw);
898 adev->gfx.ce_fw = NULL;
899 release_firmware(adev->gfx.rlc_fw);
900 adev->gfx.rlc_fw = NULL;
901 release_firmware(adev->gfx.mec_fw);
902 adev->gfx.mec_fw = NULL;
903 release_firmware(adev->gfx.mec2_fw);
904 adev->gfx.mec2_fw = NULL;
905 }
906
907 gfx_v10_0_check_gfxoff_flag(adev);
908
909 return err;
910}
911
912static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
913{
914 u32 count = 0;
915 const struct cs_section_def *sect = NULL;
916 const struct cs_extent_def *ext = NULL;
917
918
919 count += 2;
920
921 count += 3;
922
923 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
924 for (ext = sect->section; ext->extent != NULL; ++ext) {
925 if (sect->id == SECT_CONTEXT)
926 count += 2 + ext->reg_count;
927 else
928 return 0;
929 }
930 }
931
932
933 count += 3;
934
935 count += 2;
936
937 count += 2;
938
939 return count;
940}
941
942static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
943 volatile u32 *buffer)
944{
945 u32 count = 0, i;
946 const struct cs_section_def *sect = NULL;
947 const struct cs_extent_def *ext = NULL;
948 int ctx_reg_offset;
949
950 if (adev->gfx.rlc.cs_data == NULL)
951 return;
952 if (buffer == NULL)
953 return;
954
955 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
956 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
957
958 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
959 buffer[count++] = cpu_to_le32(0x80000000);
960 buffer[count++] = cpu_to_le32(0x80000000);
961
962 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
963 for (ext = sect->section; ext->extent != NULL; ++ext) {
964 if (sect->id == SECT_CONTEXT) {
965 buffer[count++] =
966 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
967 buffer[count++] = cpu_to_le32(ext->reg_index -
968 PACKET3_SET_CONTEXT_REG_START);
969 for (i = 0; i < ext->reg_count; i++)
970 buffer[count++] = cpu_to_le32(ext->extent[i]);
971 } else {
972 return;
973 }
974 }
975 }
976
977 ctx_reg_offset =
978 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
979 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
980 buffer[count++] = cpu_to_le32(ctx_reg_offset);
981 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
982
983 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
984 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
985
986 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
987 buffer[count++] = cpu_to_le32(0);
988}
989
990static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
991{
992
993 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
994 &adev->gfx.rlc.clear_state_gpu_addr,
995 (void **)&adev->gfx.rlc.cs_ptr);
996
997
998 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
999 &adev->gfx.rlc.cp_table_gpu_addr,
1000 (void **)&adev->gfx.rlc.cp_table_ptr);
1001}
1002
1003static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
1004{
1005 const struct cs_section_def *cs_data;
1006 int r;
1007
1008 adev->gfx.rlc.cs_data = gfx10_cs_data;
1009
1010 cs_data = adev->gfx.rlc.cs_data;
1011
1012 if (cs_data) {
1013
1014 r = amdgpu_gfx_rlc_init_csb(adev);
1015 if (r)
1016 return r;
1017 }
1018
1019 return 0;
1020}
1021
1022static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
1023{
1024 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1025 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1026}
1027
1028static int gfx_v10_0_me_init(struct amdgpu_device *adev)
1029{
1030 int r;
1031
1032 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
1033
1034 amdgpu_gfx_graphics_queue_acquire(adev);
1035
1036 r = gfx_v10_0_init_microcode(adev);
1037 if (r)
1038 DRM_ERROR("Failed to load gfx firmware!\n");
1039
1040 return r;
1041}
1042
1043static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
1044{
1045 int r;
1046 u32 *hpd;
1047 const __le32 *fw_data = NULL;
1048 unsigned fw_size;
1049 u32 *fw = NULL;
1050 size_t mec_hpd_size;
1051
1052 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
1053
1054 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1055
1056
1057 amdgpu_gfx_compute_queue_acquire(adev);
1058 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
1059
1060 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1061 AMDGPU_GEM_DOMAIN_GTT,
1062 &adev->gfx.mec.hpd_eop_obj,
1063 &adev->gfx.mec.hpd_eop_gpu_addr,
1064 (void **)&hpd);
1065 if (r) {
1066 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1067 gfx_v10_0_mec_fini(adev);
1068 return r;
1069 }
1070
1071 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1072
1073 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1074 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1075
1076 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1077 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1078
1079 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1080 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1081 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
1082
1083 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1084 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1085 &adev->gfx.mec.mec_fw_obj,
1086 &adev->gfx.mec.mec_fw_gpu_addr,
1087 (void **)&fw);
1088 if (r) {
1089 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
1090 gfx_v10_0_mec_fini(adev);
1091 return r;
1092 }
1093
1094 memcpy(fw, fw_data, fw_size);
1095
1096 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1097 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1098 }
1099
1100 return 0;
1101}
1102
1103static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1104{
1105 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1106 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1107 (address << SQ_IND_INDEX__INDEX__SHIFT));
1108 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1109}
1110
1111static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1112 uint32_t thread, uint32_t regno,
1113 uint32_t num, uint32_t *out)
1114{
1115 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1116 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1117 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1118 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
1119 (SQ_IND_INDEX__AUTO_INCR_MASK));
1120 while (num--)
1121 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1122}
1123
1124static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1125{
1126
1127
1128
1129 WARN_ON(simd != 0);
1130
1131
1132 dst[(*no_fields)++] = 2;
1133 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1134 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1135 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1136 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
1137 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
1138 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
1139 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
1145 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
1146 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
1147 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
1148}
1149
1150static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1151 uint32_t wave, uint32_t start,
1152 uint32_t size, uint32_t *dst)
1153{
1154 WARN_ON(simd != 0);
1155
1156 wave_read_regs(
1157 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
1158 dst);
1159}
1160
1161static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1162 uint32_t wave, uint32_t thread,
1163 uint32_t start, uint32_t size,
1164 uint32_t *dst)
1165{
1166 wave_read_regs(
1167 adev, wave, thread,
1168 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1169}
1170
1171static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
1172 u32 me, u32 pipe, u32 q, u32 vm)
1173 {
1174 nv_grbm_select(adev, me, pipe, q, vm);
1175 }
1176
1177
1178static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
1179 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
1180 .select_se_sh = &gfx_v10_0_select_se_sh,
1181 .read_wave_data = &gfx_v10_0_read_wave_data,
1182 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
1183 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
1184 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
1185};
1186
1187static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
1188{
1189 u32 gb_addr_config;
1190
1191 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
1192
1193 switch (adev->asic_type) {
1194 case CHIP_NAVI10:
1195 case CHIP_NAVI14:
1196 case CHIP_NAVI12:
1197 adev->gfx.config.max_hw_contexts = 8;
1198 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1199 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1200 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
1201 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1202 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1203 break;
1204 default:
1205 BUG();
1206 break;
1207 }
1208
1209 adev->gfx.config.gb_addr_config = gb_addr_config;
1210
1211 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1212 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1213 GB_ADDR_CONFIG, NUM_PIPES);
1214
1215 adev->gfx.config.max_tile_pipes =
1216 adev->gfx.config.gb_addr_config_fields.num_pipes;
1217
1218 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1219 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1220 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
1221 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1222 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1223 GB_ADDR_CONFIG, NUM_RB_PER_SE);
1224 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1225 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1226 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
1227 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1228 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
1229 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
1230}
1231
1232static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
1233 int me, int pipe, int queue)
1234{
1235 int r;
1236 struct amdgpu_ring *ring;
1237 unsigned int irq_type;
1238
1239 ring = &adev->gfx.gfx_ring[ring_id];
1240
1241 ring->me = me;
1242 ring->pipe = pipe;
1243 ring->queue = queue;
1244
1245 ring->ring_obj = NULL;
1246 ring->use_doorbell = true;
1247
1248 if (!ring_id)
1249 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
1250 else
1251 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
1252 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1253
1254 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
1255 r = amdgpu_ring_init(adev, ring, 1024,
1256 &adev->gfx.eop_irq, irq_type);
1257 if (r)
1258 return r;
1259 return 0;
1260}
1261
1262static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1263 int mec, int pipe, int queue)
1264{
1265 int r;
1266 unsigned irq_type;
1267 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1268
1269 ring = &adev->gfx.compute_ring[ring_id];
1270
1271
1272 ring->me = mec + 1;
1273 ring->pipe = pipe;
1274 ring->queue = queue;
1275
1276 ring->ring_obj = NULL;
1277 ring->use_doorbell = true;
1278 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
1279 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1280 + (ring_id * GFX10_MEC_HPD_SIZE);
1281 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1282
1283 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1284 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1285 + ring->pipe;
1286
1287
1288 r = amdgpu_ring_init(adev, ring, 1024,
1289 &adev->gfx.eop_irq, irq_type);
1290 if (r)
1291 return r;
1292
1293 return 0;
1294}
1295
1296static int gfx_v10_0_sw_init(void *handle)
1297{
1298 int i, j, k, r, ring_id = 0;
1299 struct amdgpu_kiq *kiq;
1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301
1302 switch (adev->asic_type) {
1303 case CHIP_NAVI10:
1304 case CHIP_NAVI14:
1305 case CHIP_NAVI12:
1306 adev->gfx.me.num_me = 1;
1307 adev->gfx.me.num_pipe_per_me = 1;
1308 adev->gfx.me.num_queue_per_pipe = 1;
1309 adev->gfx.mec.num_mec = 2;
1310 adev->gfx.mec.num_pipe_per_mec = 4;
1311 adev->gfx.mec.num_queue_per_pipe = 8;
1312 break;
1313 default:
1314 adev->gfx.me.num_me = 1;
1315 adev->gfx.me.num_pipe_per_me = 1;
1316 adev->gfx.me.num_queue_per_pipe = 1;
1317 adev->gfx.mec.num_mec = 1;
1318 adev->gfx.mec.num_pipe_per_mec = 4;
1319 adev->gfx.mec.num_queue_per_pipe = 8;
1320 break;
1321 }
1322
1323
1324 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1325 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
1326 &adev->gfx.kiq.irq);
1327 if (r)
1328 return r;
1329
1330
1331 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
1332 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
1333 &adev->gfx.eop_irq);
1334 if (r)
1335 return r;
1336
1337
1338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
1339 &adev->gfx.priv_reg_irq);
1340 if (r)
1341 return r;
1342
1343
1344 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
1345 &adev->gfx.priv_inst_irq);
1346 if (r)
1347 return r;
1348
1349 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1350
1351 gfx_v10_0_scratch_init(adev);
1352
1353 r = gfx_v10_0_me_init(adev);
1354 if (r)
1355 return r;
1356
1357 r = gfx_v10_0_rlc_init(adev);
1358 if (r) {
1359 DRM_ERROR("Failed to init rlc BOs!\n");
1360 return r;
1361 }
1362
1363 r = gfx_v10_0_mec_init(adev);
1364 if (r) {
1365 DRM_ERROR("Failed to init MEC BOs!\n");
1366 return r;
1367 }
1368
1369
1370 for (i = 0; i < adev->gfx.me.num_me; i++) {
1371 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1372 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1373 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1374 continue;
1375
1376 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
1377 i, k, j);
1378 if (r)
1379 return r;
1380 ring_id++;
1381 }
1382 }
1383 }
1384
1385 ring_id = 0;
1386
1387 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1388 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1389 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1390 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1391 j))
1392 continue;
1393
1394 r = gfx_v10_0_compute_ring_init(adev, ring_id,
1395 i, k, j);
1396 if (r)
1397 return r;
1398
1399 ring_id++;
1400 }
1401 }
1402 }
1403
1404 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
1405 if (r) {
1406 DRM_ERROR("Failed to init KIQ BOs!\n");
1407 return r;
1408 }
1409
1410 kiq = &adev->gfx.kiq;
1411 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1412 if (r)
1413 return r;
1414
1415 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
1416 if (r)
1417 return r;
1418
1419
1420 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1421 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
1422 if (r)
1423 return r;
1424 }
1425
1426 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
1427
1428 gfx_v10_0_gpu_early_init(adev);
1429
1430 return 0;
1431}
1432
1433static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
1434{
1435 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1436 &adev->gfx.pfp.pfp_fw_gpu_addr,
1437 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1438}
1439
1440static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
1441{
1442 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
1443 &adev->gfx.ce.ce_fw_gpu_addr,
1444 (void **)&adev->gfx.ce.ce_fw_ptr);
1445}
1446
1447static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
1448{
1449 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1450 &adev->gfx.me.me_fw_gpu_addr,
1451 (void **)&adev->gfx.me.me_fw_ptr);
1452}
1453
1454static int gfx_v10_0_sw_fini(void *handle)
1455{
1456 int i;
1457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1458
1459 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1460 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1461 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1462 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1463
1464 amdgpu_gfx_mqd_sw_fini(adev);
1465 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1466 amdgpu_gfx_kiq_fini(adev);
1467
1468 gfx_v10_0_pfp_fini(adev);
1469 gfx_v10_0_ce_fini(adev);
1470 gfx_v10_0_me_fini(adev);
1471 gfx_v10_0_rlc_fini(adev);
1472 gfx_v10_0_mec_fini(adev);
1473
1474 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1475 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
1476
1477 gfx_v10_0_free_microcode(adev);
1478
1479 return 0;
1480}
1481
1482
1483static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
1484{
1485
1486}
1487
1488static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1489 u32 sh_num, u32 instance)
1490{
1491 u32 data;
1492
1493 if (instance == 0xffffffff)
1494 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1495 INSTANCE_BROADCAST_WRITES, 1);
1496 else
1497 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1498 instance);
1499
1500 if (se_num == 0xffffffff)
1501 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1502 1);
1503 else
1504 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1505
1506 if (sh_num == 0xffffffff)
1507 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1508 1);
1509 else
1510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1511
1512 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1513}
1514
1515static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1516{
1517 u32 data, mask;
1518
1519 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1520 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1521
1522 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1523 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1524
1525 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1526 adev->gfx.config.max_sh_per_se);
1527
1528 return (~data) & mask;
1529}
1530
1531static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
1532{
1533 int i, j;
1534 u32 data;
1535 u32 active_rbs = 0;
1536 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1537 adev->gfx.config.max_sh_per_se;
1538
1539 mutex_lock(&adev->grbm_idx_mutex);
1540 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1541 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1542 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1543 data = gfx_v10_0_get_rb_active_bitmap(adev);
1544 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1545 rb_bitmap_width_per_sh);
1546 }
1547 }
1548 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1549 mutex_unlock(&adev->grbm_idx_mutex);
1550
1551 adev->gfx.config.backend_enable_mask = active_rbs;
1552 adev->gfx.config.num_rbs = hweight32(active_rbs);
1553}
1554
1555static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
1556{
1557 uint32_t num_sc;
1558 uint32_t enabled_rb_per_sh;
1559 uint32_t active_rb_bitmap;
1560 uint32_t num_rb_per_sc;
1561 uint32_t num_packer_per_sc;
1562 uint32_t pa_sc_tile_steering_override;
1563
1564
1565 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
1566 adev->gfx.config.num_sc_per_sh;
1567
1568 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
1569 enabled_rb_per_sh = hweight32(active_rb_bitmap);
1570 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
1571
1572 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
1573
1574 pa_sc_tile_steering_override = 0;
1575 pa_sc_tile_steering_override |=
1576 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
1577 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
1578 pa_sc_tile_steering_override |=
1579 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
1580 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
1581 pa_sc_tile_steering_override |=
1582 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
1583 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
1584
1585 return pa_sc_tile_steering_override;
1586}
1587
1588#define DEFAULT_SH_MEM_BASES (0x6000)
1589#define FIRST_COMPUTE_VMID (8)
1590#define LAST_COMPUTE_VMID (16)
1591
1592static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
1593{
1594 int i;
1595 uint32_t sh_mem_bases;
1596
1597
1598
1599
1600
1601
1602
1603 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1604
1605 mutex_lock(&adev->srbm_mutex);
1606 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1607 nv_grbm_select(adev, 0, 0, 0, i);
1608
1609 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1610 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1611 }
1612 nv_grbm_select(adev, 0, 0, 0, 0);
1613 mutex_unlock(&adev->srbm_mutex);
1614
1615
1616
1617 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1618 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
1619 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
1620 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
1621 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
1622 }
1623}
1624
1625static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
1626{
1627 int vmid;
1628
1629
1630
1631
1632
1633
1634
1635 for (vmid = 1; vmid < 16; vmid++) {
1636 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
1637 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
1638 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
1639 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
1640 }
1641}
1642
1643
1644static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
1645{
1646 int i, j, k;
1647 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
1648 u32 tmp, wgp_active_bitmap = 0;
1649 u32 gcrd_targets_disable_tcp = 0;
1650 u32 utcl_invreq_disable = 0;
1651
1652
1653
1654
1655
1656 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
1657 2 * max_wgp_per_sh +
1658 max_wgp_per_sh +
1659 4);
1660
1661
1662
1663
1664
1665 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
1666 2 * max_wgp_per_sh +
1667 2 * max_wgp_per_sh +
1668 4 +
1669 1);
1670
1671 if (adev->asic_type == CHIP_NAVI10 ||
1672 adev->asic_type == CHIP_NAVI14 ||
1673 adev->asic_type == CHIP_NAVI12) {
1674 mutex_lock(&adev->grbm_idx_mutex);
1675 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1676 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1677 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
1678 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
1679
1680
1681
1682
1683 gcrd_targets_disable_tcp = 0;
1684
1685 utcl_invreq_disable = 0;
1686
1687 for (k = 0; k < max_wgp_per_sh; k++) {
1688 if (!(wgp_active_bitmap & (1 << k))) {
1689 gcrd_targets_disable_tcp |= 3 << (2 * k);
1690 utcl_invreq_disable |= (3 << (2 * k)) |
1691 (3 << (2 * (max_wgp_per_sh + k)));
1692 }
1693 }
1694
1695 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
1696
1697 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
1698 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
1699 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
1700
1701 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
1702
1703 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
1704 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
1705 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
1706 }
1707 }
1708
1709 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1710 mutex_unlock(&adev->grbm_idx_mutex);
1711 }
1712}
1713
1714static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
1715{
1716
1717 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
1718 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
1719
1720 adev->gfx.config.tcc_disabled_mask =
1721 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1722 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1723}
1724
1725static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
1726{
1727 u32 tmp;
1728 int i;
1729
1730 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1731
1732 gfx_v10_0_tiling_mode_table_init(adev);
1733
1734 gfx_v10_0_setup_rb(adev);
1735 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
1736 gfx_v10_0_get_tcc_info(adev);
1737 adev->gfx.config.pa_sc_tile_steering_override =
1738 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
1739
1740
1741
1742 mutex_lock(&adev->srbm_mutex);
1743 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1744 nv_grbm_select(adev, 0, 0, 0, i);
1745
1746 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1747 if (i != 0) {
1748 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1749 (adev->gmc.private_aperture_start >> 48));
1750 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1751 (adev->gmc.shared_aperture_start >> 48));
1752 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1753 }
1754 }
1755 nv_grbm_select(adev, 0, 0, 0, 0);
1756
1757 mutex_unlock(&adev->srbm_mutex);
1758
1759 gfx_v10_0_init_compute_vmid(adev);
1760 gfx_v10_0_init_gds_vmid(adev);
1761
1762}
1763
1764static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1765 bool enable)
1766{
1767 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1768
1769 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1770 enable ? 1 : 0);
1771 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1772 enable ? 1 : 0);
1773 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1774 enable ? 1 : 0);
1775 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1776 enable ? 1 : 0);
1777
1778 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1779}
1780
1781static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
1782{
1783 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1784
1785
1786 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
1787 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1788 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
1789 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1790 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1791
1792 return 0;
1793}
1794
1795void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
1796{
1797 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
1798
1799 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1800 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
1801}
1802
1803static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
1804{
1805 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1806 udelay(50);
1807 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1808 udelay(50);
1809}
1810
1811static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1812 bool enable)
1813{
1814 uint32_t rlc_pg_cntl;
1815
1816 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
1817
1818 if (!enable) {
1819
1820
1821
1822
1823
1824
1825
1826
1827 rlc_pg_cntl |= 0x800000;
1828 } else
1829 rlc_pg_cntl &= ~0x800000;
1830 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
1831}
1832
1833static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
1834{
1835
1836
1837 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1838 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
1839
1840 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1841 udelay(50);
1842}
1843
1844static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
1845{
1846 uint32_t tmp;
1847
1848
1849 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
1850 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1851 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1852 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
1853}
1854
1855static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
1856{
1857 const struct rlc_firmware_header_v2_0 *hdr;
1858 const __le32 *fw_data;
1859 unsigned i, fw_size;
1860
1861 if (!adev->gfx.rlc_fw)
1862 return -EINVAL;
1863
1864 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1865 amdgpu_ucode_print_rlc_hdr(&hdr->header);
1866
1867 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1868 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1869 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1870
1871 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
1872 RLCG_UCODE_LOADING_START_ADDRESS);
1873
1874 for (i = 0; i < fw_size; i++)
1875 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
1876 le32_to_cpup(fw_data++));
1877
1878 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1879
1880 return 0;
1881}
1882
1883static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
1884{
1885 int r;
1886
1887 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1888
1889 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1890 if (r)
1891 return r;
1892
1893 gfx_v10_0_init_csb(adev);
1894
1895 if (!amdgpu_sriov_vf(adev))
1896 gfx_v10_0_rlc_enable_srm(adev);
1897 } else {
1898 adev->gfx.rlc.funcs->stop(adev);
1899
1900
1901 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
1902
1903
1904 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
1905
1906 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1907
1908 r = gfx_v10_0_rlc_load_microcode(adev);
1909 if (r)
1910 return r;
1911 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1912
1913 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
1914 if (r)
1915 return r;
1916 }
1917
1918 gfx_v10_0_init_csb(adev);
1919
1920 adev->gfx.rlc.funcs->start(adev);
1921
1922 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1923 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
1924 if (r)
1925 return r;
1926 }
1927 }
1928 return 0;
1929}
1930
1931static struct {
1932 FIRMWARE_ID id;
1933 unsigned int offset;
1934 unsigned int size;
1935} rlc_autoload_info[FIRMWARE_ID_MAX];
1936
1937static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
1938{
1939 int ret;
1940 RLC_TABLE_OF_CONTENT *rlc_toc;
1941
1942 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
1943 AMDGPU_GEM_DOMAIN_GTT,
1944 &adev->gfx.rlc.rlc_toc_bo,
1945 &adev->gfx.rlc.rlc_toc_gpu_addr,
1946 (void **)&adev->gfx.rlc.rlc_toc_buf);
1947 if (ret) {
1948 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
1949 return ret;
1950 }
1951
1952
1953 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
1954
1955 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
1956 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
1957 (rlc_toc->id < FIRMWARE_ID_MAX)) {
1958 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
1959 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
1960
1961 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
1962 }
1963
1964 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
1965 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
1966 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
1967
1968 rlc_toc++;
1969 }
1970
1971 return 0;
1972}
1973
1974static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
1975{
1976 uint32_t total_size = 0;
1977 FIRMWARE_ID id;
1978 int ret;
1979
1980 ret = gfx_v10_0_parse_rlc_toc(adev);
1981 if (ret) {
1982 dev_err(adev->dev, "failed to parse rlc toc\n");
1983 return 0;
1984 }
1985
1986 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
1987 total_size += rlc_autoload_info[id].size;
1988
1989
1990 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
1991 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
1992 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
1993
1994 return total_size;
1995}
1996
1997static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
1998{
1999 int r;
2000 uint32_t total_size;
2001
2002 total_size = gfx_v10_0_calc_toc_total_size(adev);
2003
2004 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
2005 AMDGPU_GEM_DOMAIN_GTT,
2006 &adev->gfx.rlc.rlc_autoload_bo,
2007 &adev->gfx.rlc.rlc_autoload_gpu_addr,
2008 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2009 if (r) {
2010 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
2011 return r;
2012 }
2013
2014 return 0;
2015}
2016
2017static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
2018{
2019 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
2020 &adev->gfx.rlc.rlc_toc_gpu_addr,
2021 (void **)&adev->gfx.rlc.rlc_toc_buf);
2022 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
2023 &adev->gfx.rlc.rlc_autoload_gpu_addr,
2024 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
2025}
2026
2027static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
2028 FIRMWARE_ID id,
2029 const void *fw_data,
2030 uint32_t fw_size)
2031{
2032 uint32_t toc_offset;
2033 uint32_t toc_fw_size;
2034 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
2035
2036 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
2037 return;
2038
2039 toc_offset = rlc_autoload_info[id].offset;
2040 toc_fw_size = rlc_autoload_info[id].size;
2041
2042 if (fw_size == 0)
2043 fw_size = toc_fw_size;
2044
2045 if (fw_size > toc_fw_size)
2046 fw_size = toc_fw_size;
2047
2048 memcpy(ptr + toc_offset, fw_data, fw_size);
2049
2050 if (fw_size < toc_fw_size)
2051 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
2052}
2053
2054static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
2055{
2056 void *data;
2057 uint32_t size;
2058
2059 data = adev->gfx.rlc.rlc_toc_buf;
2060 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
2061
2062 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2063 FIRMWARE_ID_RLC_TOC,
2064 data, size);
2065}
2066
2067static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
2068{
2069 const __le32 *fw_data;
2070 uint32_t fw_size;
2071 const struct gfx_firmware_header_v1_0 *cp_hdr;
2072 const struct rlc_firmware_header_v2_0 *rlc_hdr;
2073
2074
2075 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2076 adev->gfx.pfp_fw->data;
2077 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2078 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2079 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2080 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2081 FIRMWARE_ID_CP_PFP,
2082 fw_data, fw_size);
2083
2084
2085 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2086 adev->gfx.ce_fw->data;
2087 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2088 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2089 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2090 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2091 FIRMWARE_ID_CP_CE,
2092 fw_data, fw_size);
2093
2094
2095 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2096 adev->gfx.me_fw->data;
2097 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2098 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2099 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
2100 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2101 FIRMWARE_ID_CP_ME,
2102 fw_data, fw_size);
2103
2104
2105 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
2106 adev->gfx.rlc_fw->data;
2107 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2108 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
2109 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
2110 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2111 FIRMWARE_ID_RLC_G_UCODE,
2112 fw_data, fw_size);
2113
2114
2115 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
2116 adev->gfx.mec_fw->data;
2117 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
2118 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
2119 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
2120 cp_hdr->jt_size * 4;
2121 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2122 FIRMWARE_ID_CP_MEC,
2123 fw_data, fw_size);
2124
2125}
2126
2127
2128static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
2129{
2130 const __le32 *fw_data;
2131 uint32_t fw_size;
2132 const struct sdma_firmware_header_v1_0 *sdma_hdr;
2133 int i;
2134
2135 for (i = 0; i < adev->sdma.num_instances; i++) {
2136 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
2137 adev->sdma.instance[i].fw->data;
2138 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
2139 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
2140 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
2141
2142 if (i == 0) {
2143 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2144 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
2145 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2146 FIRMWARE_ID_SDMA0_JT,
2147 (uint32_t *)fw_data +
2148 sdma_hdr->jt_offset,
2149 sdma_hdr->jt_size * 4);
2150 } else if (i == 1) {
2151 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2152 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
2153 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
2154 FIRMWARE_ID_SDMA1_JT,
2155 (uint32_t *)fw_data +
2156 sdma_hdr->jt_offset,
2157 sdma_hdr->jt_size * 4);
2158 }
2159 }
2160}
2161
2162static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
2163{
2164 uint32_t rlc_g_offset, rlc_g_size, tmp;
2165 uint64_t gpu_addr;
2166
2167 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
2168 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
2169 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
2170
2171 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
2172 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
2173 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
2174
2175 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
2176 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
2177 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
2178
2179 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
2180 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
2181 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
2182 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
2183 return -EINVAL;
2184 }
2185
2186 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
2187 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2188 DRM_ERROR("RLC ROM should halt itself\n");
2189 return -EINVAL;
2190 }
2191
2192 return 0;
2193}
2194
2195static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
2196{
2197 uint32_t usec_timeout = 50000;
2198 uint32_t tmp;
2199 int i;
2200 uint64_t addr;
2201
2202
2203 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2204 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2205 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2206
2207
2208 for (i = 0; i < usec_timeout; i++) {
2209 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2210 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2211 INVALIDATE_CACHE_COMPLETE))
2212 break;
2213 udelay(1);
2214 }
2215
2216 if (i >= usec_timeout) {
2217 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2218 return -EINVAL;
2219 }
2220
2221
2222 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2223 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
2224 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2225 lower_32_bits(addr) & 0xFFFFF000);
2226 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2227 upper_32_bits(addr));
2228
2229 return 0;
2230}
2231
2232static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
2233{
2234 uint32_t usec_timeout = 50000;
2235 uint32_t tmp;
2236 int i;
2237 uint64_t addr;
2238
2239
2240 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2241 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2242 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2243
2244
2245 for (i = 0; i < usec_timeout; i++) {
2246 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2247 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2248 INVALIDATE_CACHE_COMPLETE))
2249 break;
2250 udelay(1);
2251 }
2252
2253 if (i >= usec_timeout) {
2254 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2255 return -EINVAL;
2256 }
2257
2258
2259 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2260 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
2261 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2262 lower_32_bits(addr) & 0xFFFFF000);
2263 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2264 upper_32_bits(addr));
2265
2266 return 0;
2267}
2268
2269static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
2270{
2271 uint32_t usec_timeout = 50000;
2272 uint32_t tmp;
2273 int i;
2274 uint64_t addr;
2275
2276
2277 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2278 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2279 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2280
2281
2282 for (i = 0; i < usec_timeout; i++) {
2283 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2284 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2285 INVALIDATE_CACHE_COMPLETE))
2286 break;
2287 udelay(1);
2288 }
2289
2290 if (i >= usec_timeout) {
2291 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2292 return -EINVAL;
2293 }
2294
2295
2296 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2297 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
2298 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2299 lower_32_bits(addr) & 0xFFFFF000);
2300 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2301 upper_32_bits(addr));
2302
2303 return 0;
2304}
2305
2306static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
2307{
2308 uint32_t usec_timeout = 50000;
2309 uint32_t tmp;
2310 int i;
2311 uint64_t addr;
2312
2313
2314 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2315 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2316 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2317
2318
2319 for (i = 0; i < usec_timeout; i++) {
2320 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2321 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2322 INVALIDATE_CACHE_COMPLETE))
2323 break;
2324 udelay(1);
2325 }
2326
2327 if (i >= usec_timeout) {
2328 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2329 return -EINVAL;
2330 }
2331
2332
2333 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2334 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
2335 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2336 lower_32_bits(addr) & 0xFFFFF000);
2337 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2338 upper_32_bits(addr));
2339
2340 return 0;
2341}
2342
2343static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2344{
2345 uint32_t cp_status;
2346 uint32_t bootload_status;
2347 int i, r;
2348
2349 for (i = 0; i < adev->usec_timeout; i++) {
2350 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
2351 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
2352 if ((cp_status == 0) &&
2353 (REG_GET_FIELD(bootload_status,
2354 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2355 break;
2356 }
2357 udelay(1);
2358 }
2359
2360 if (i >= adev->usec_timeout) {
2361 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2362 return -ETIMEDOUT;
2363 }
2364
2365 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2366 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
2367 if (r)
2368 return r;
2369
2370 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
2371 if (r)
2372 return r;
2373
2374 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
2375 if (r)
2376 return r;
2377
2378 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
2379 if (r)
2380 return r;
2381 }
2382
2383 return 0;
2384}
2385
2386static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2387{
2388 int i;
2389 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2390
2391 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2392 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2393 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2394 if (!enable) {
2395 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2396 adev->gfx.gfx_ring[i].sched.ready = false;
2397 }
2398 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2399
2400 for (i = 0; i < adev->usec_timeout; i++) {
2401 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
2402 break;
2403 udelay(1);
2404 }
2405
2406 if (i >= adev->usec_timeout)
2407 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2408
2409 return 0;
2410}
2411
2412static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2413{
2414 int r;
2415 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2416 const __le32 *fw_data;
2417 unsigned i, fw_size;
2418 uint32_t tmp;
2419 uint32_t usec_timeout = 50000;
2420
2421 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2422 adev->gfx.pfp_fw->data;
2423
2424 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2425
2426 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2427 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2428 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2429
2430 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2431 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2432 &adev->gfx.pfp.pfp_fw_obj,
2433 &adev->gfx.pfp.pfp_fw_gpu_addr,
2434 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2435 if (r) {
2436 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2437 gfx_v10_0_pfp_fini(adev);
2438 return r;
2439 }
2440
2441 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2442
2443 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2444 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2445
2446
2447 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2448 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2449 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
2450
2451
2452 for (i = 0; i < usec_timeout; i++) {
2453 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
2454 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2455 INVALIDATE_CACHE_COMPLETE))
2456 break;
2457 udelay(1);
2458 }
2459
2460 if (i >= usec_timeout) {
2461 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2462 return -EINVAL;
2463 }
2464
2465 if (amdgpu_emu_mode == 1)
2466 adev->nbio.funcs->hdp_flush(adev, NULL);
2467
2468 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
2469 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2470 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2471 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2472 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2473 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
2474 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
2475 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
2476 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
2477 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2478
2479 return 0;
2480}
2481
2482static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
2483{
2484 int r;
2485 const struct gfx_firmware_header_v1_0 *ce_hdr;
2486 const __le32 *fw_data;
2487 unsigned i, fw_size;
2488 uint32_t tmp;
2489 uint32_t usec_timeout = 50000;
2490
2491 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2492 adev->gfx.ce_fw->data;
2493
2494 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2495
2496 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
2497 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2498 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
2499
2500 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
2501 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2502 &adev->gfx.ce.ce_fw_obj,
2503 &adev->gfx.ce.ce_fw_gpu_addr,
2504 (void **)&adev->gfx.ce.ce_fw_ptr);
2505 if (r) {
2506 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
2507 gfx_v10_0_ce_fini(adev);
2508 return r;
2509 }
2510
2511 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
2512
2513 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
2514 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
2515
2516
2517 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2518 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2519 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
2520
2521
2522 for (i = 0; i < usec_timeout; i++) {
2523 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
2524 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
2525 INVALIDATE_CACHE_COMPLETE))
2526 break;
2527 udelay(1);
2528 }
2529
2530 if (i >= usec_timeout) {
2531 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2532 return -EINVAL;
2533 }
2534
2535 if (amdgpu_emu_mode == 1)
2536 adev->nbio.funcs->hdp_flush(adev, NULL);
2537
2538 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
2539 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
2540 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
2541 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
2542 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2543 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
2544 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
2545 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
2546 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
2547
2548 return 0;
2549}
2550
2551static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2552{
2553 int r;
2554 const struct gfx_firmware_header_v1_0 *me_hdr;
2555 const __le32 *fw_data;
2556 unsigned i, fw_size;
2557 uint32_t tmp;
2558 uint32_t usec_timeout = 50000;
2559
2560 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2561 adev->gfx.me_fw->data;
2562
2563 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2564
2565 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2566 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2567 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2568
2569 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2570 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2571 &adev->gfx.me.me_fw_obj,
2572 &adev->gfx.me.me_fw_gpu_addr,
2573 (void **)&adev->gfx.me.me_fw_ptr);
2574 if (r) {
2575 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2576 gfx_v10_0_me_fini(adev);
2577 return r;
2578 }
2579
2580 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2581
2582 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2583 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2584
2585
2586 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2587 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2588 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
2589
2590
2591 for (i = 0; i < usec_timeout; i++) {
2592 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
2593 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2594 INVALIDATE_CACHE_COMPLETE))
2595 break;
2596 udelay(1);
2597 }
2598
2599 if (i >= usec_timeout) {
2600 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2601 return -EINVAL;
2602 }
2603
2604 if (amdgpu_emu_mode == 1)
2605 adev->nbio.funcs->hdp_flush(adev, NULL);
2606
2607 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
2608 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2609 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2610 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2611 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2612 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
2613 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
2614 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
2615 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2616
2617 return 0;
2618}
2619
2620static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2621{
2622 int r;
2623
2624 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2625 return -EINVAL;
2626
2627 gfx_v10_0_cp_gfx_enable(adev, false);
2628
2629 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
2630 if (r) {
2631 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
2632 return r;
2633 }
2634
2635 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
2636 if (r) {
2637 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
2638 return r;
2639 }
2640
2641 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
2642 if (r) {
2643 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
2644 return r;
2645 }
2646
2647 return 0;
2648}
2649
2650static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
2651{
2652 struct amdgpu_ring *ring;
2653 const struct cs_section_def *sect = NULL;
2654 const struct cs_extent_def *ext = NULL;
2655 int r, i;
2656 int ctx_reg_offset;
2657
2658
2659 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
2660 adev->gfx.config.max_hw_contexts - 1);
2661 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2662
2663 gfx_v10_0_cp_gfx_enable(adev, true);
2664
2665 ring = &adev->gfx.gfx_ring[0];
2666 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
2667 if (r) {
2668 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2669 return r;
2670 }
2671
2672 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2673 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2674
2675 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2676 amdgpu_ring_write(ring, 0x80000000);
2677 amdgpu_ring_write(ring, 0x80000000);
2678
2679 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
2680 for (ext = sect->section; ext->extent != NULL; ++ext) {
2681 if (sect->id == SECT_CONTEXT) {
2682 amdgpu_ring_write(ring,
2683 PACKET3(PACKET3_SET_CONTEXT_REG,
2684 ext->reg_count));
2685 amdgpu_ring_write(ring, ext->reg_index -
2686 PACKET3_SET_CONTEXT_REG_START);
2687 for (i = 0; i < ext->reg_count; i++)
2688 amdgpu_ring_write(ring, ext->extent[i]);
2689 }
2690 }
2691 }
2692
2693 ctx_reg_offset =
2694 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
2695 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2696 amdgpu_ring_write(ring, ctx_reg_offset);
2697 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
2698
2699 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2700 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2701
2702 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2703 amdgpu_ring_write(ring, 0);
2704
2705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2706 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2707 amdgpu_ring_write(ring, 0x8000);
2708 amdgpu_ring_write(ring, 0x8000);
2709
2710 amdgpu_ring_commit(ring);
2711
2712
2713 if (adev->gfx.num_gfx_rings > 1) {
2714
2715 ring = &adev->gfx.gfx_ring[1];
2716 r = amdgpu_ring_alloc(ring, 2);
2717 if (r) {
2718 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2719 return r;
2720 }
2721
2722 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2723 amdgpu_ring_write(ring, 0);
2724
2725 amdgpu_ring_commit(ring);
2726 }
2727 return 0;
2728}
2729
2730static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
2731 CP_PIPE_ID pipe)
2732{
2733 u32 tmp;
2734
2735 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
2736 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
2737
2738 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
2739}
2740
2741static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
2742 struct amdgpu_ring *ring)
2743{
2744 u32 tmp;
2745
2746 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2747 if (ring->use_doorbell) {
2748 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2749 DOORBELL_OFFSET, ring->doorbell_index);
2750 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2751 DOORBELL_EN, 1);
2752 } else {
2753 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2754 DOORBELL_EN, 0);
2755 }
2756 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2757 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2758 DOORBELL_RANGE_LOWER, ring->doorbell_index);
2759 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2760
2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2762 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2763}
2764
2765static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
2766{
2767 struct amdgpu_ring *ring;
2768 u32 tmp;
2769 u32 rb_bufsz;
2770 u64 rb_addr, rptr_addr, wptr_gpu_addr;
2771 u32 i;
2772
2773
2774 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2775
2776
2777 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2778
2779
2780 mutex_lock(&adev->srbm_mutex);
2781 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2782
2783
2784 ring = &adev->gfx.gfx_ring[0];
2785 rb_bufsz = order_base_2(ring->ring_size / 8);
2786 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2787 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2788#ifdef __BIG_ENDIAN
2789 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2790#endif
2791 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2792
2793
2794 ring->wptr = 0;
2795 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2796 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2797
2798
2799 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2800 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2801 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2802 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2803
2804 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2805 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2806 lower_32_bits(wptr_gpu_addr));
2807 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2808 upper_32_bits(wptr_gpu_addr));
2809
2810 mdelay(1);
2811 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2812
2813 rb_addr = ring->gpu_addr >> 8;
2814 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2815 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2816
2817 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
2818
2819 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2820 mutex_unlock(&adev->srbm_mutex);
2821
2822
2823 if (adev->gfx.num_gfx_rings > 1) {
2824 mutex_lock(&adev->srbm_mutex);
2825 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
2826
2827 ring = &adev->gfx.gfx_ring[1];
2828 rb_bufsz = order_base_2(ring->ring_size / 8);
2829 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2830 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2832
2833 ring->wptr = 0;
2834 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2835 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
2836
2837 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2838 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2839 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2840 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2841 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2842 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
2843 lower_32_bits(wptr_gpu_addr));
2844 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
2845 upper_32_bits(wptr_gpu_addr));
2846
2847 mdelay(1);
2848 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
2849
2850 rb_addr = ring->gpu_addr >> 8;
2851 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
2852 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
2853 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
2854
2855 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
2856 mutex_unlock(&adev->srbm_mutex);
2857 }
2858
2859 mutex_lock(&adev->srbm_mutex);
2860 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
2861 mutex_unlock(&adev->srbm_mutex);
2862
2863
2864 gfx_v10_0_cp_gfx_start(adev);
2865
2866 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2867 ring = &adev->gfx.gfx_ring[i];
2868 ring->sched.ready = true;
2869 }
2870
2871 return 0;
2872}
2873
2874static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2875{
2876 int i;
2877
2878 if (enable) {
2879 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2880 } else {
2881 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2882 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
2883 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2884 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2885 adev->gfx.compute_ring[i].sched.ready = false;
2886 adev->gfx.kiq.ring.sched.ready = false;
2887 }
2888 udelay(50);
2889}
2890
2891static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2892{
2893 const struct gfx_firmware_header_v1_0 *mec_hdr;
2894 const __le32 *fw_data;
2895 unsigned i;
2896 u32 tmp;
2897 u32 usec_timeout = 50000;
2898
2899 if (!adev->gfx.mec_fw)
2900 return -EINVAL;
2901
2902 gfx_v10_0_cp_compute_enable(adev, false);
2903
2904 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2905 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2906
2907 fw_data = (const __le32 *)
2908 (adev->gfx.mec_fw->data +
2909 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2910
2911
2912 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2913 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2914 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
2915
2916
2917 for (i = 0; i < usec_timeout; i++) {
2918 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
2919 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2920 INVALIDATE_CACHE_COMPLETE))
2921 break;
2922 udelay(1);
2923 }
2924
2925 if (i >= usec_timeout) {
2926 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2927 return -EINVAL;
2928 }
2929
2930 if (amdgpu_emu_mode == 1)
2931 adev->nbio.funcs->hdp_flush(adev, NULL);
2932
2933 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
2934 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2935 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2936 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2937 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2938
2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
2940 0xFFFFF000);
2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2942 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2943
2944
2945 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
2946
2947 for (i = 0; i < mec_hdr->jt_size; i++)
2948 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2949 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2950
2951 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2952
2953
2954
2955
2956
2957
2958 return 0;
2959}
2960
2961static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
2962{
2963 uint32_t tmp;
2964 struct amdgpu_device *adev = ring->adev;
2965
2966
2967 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2968 tmp &= 0xffffff00;
2969 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2970 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2971 tmp |= 0x80;
2972 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2973}
2974
2975static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
2976{
2977 struct amdgpu_device *adev = ring->adev;
2978 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
2979 uint64_t hqd_gpu_addr, wb_gpu_addr;
2980 uint32_t tmp;
2981 uint32_t rb_bufsz;
2982
2983
2984 mqd->cp_gfx_hqd_wptr = 0;
2985 mqd->cp_gfx_hqd_wptr_hi = 0;
2986
2987
2988 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
2989 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2990
2991
2992 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
2993 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
2994 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
2995 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
2996 mqd->cp_gfx_mqd_control = tmp;
2997
2998
2999 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
3000 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3001 mqd->cp_gfx_hqd_vmid = 0;
3002
3003
3004
3005 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
3006 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3007 mqd->cp_gfx_hqd_queue_priority = tmp;
3008
3009
3010 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
3011 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3012 mqd->cp_gfx_hqd_quantum = tmp;
3013
3014
3015 hqd_gpu_addr = ring->gpu_addr >> 8;
3016 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3017 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3018
3019
3020 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3021 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3022 mqd->cp_gfx_hqd_rptr_addr_hi =
3023 upper_32_bits(wb_gpu_addr) & 0xffff;
3024
3025
3026 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3027 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3028 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3029
3030
3031 rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
3032 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
3033 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3034 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3035#ifdef __BIG_ENDIAN
3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3037#endif
3038 mqd->cp_gfx_hqd_cntl = tmp;
3039
3040
3041 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
3042 if (ring->use_doorbell) {
3043 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3044 DOORBELL_OFFSET, ring->doorbell_index);
3045 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3046 DOORBELL_EN, 1);
3047 } else
3048 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3049 DOORBELL_EN, 0);
3050 mqd->cp_rb_doorbell_control = tmp;
3051
3052
3053 ring->wptr = 0;
3054 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
3055
3056
3057 mqd->cp_gfx_hqd_active = 1;
3058
3059 return 0;
3060}
3061
3062#ifdef BRING_UP_DEBUG
3063static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3064{
3065 struct amdgpu_device *adev = ring->adev;
3066 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3067
3068
3069 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3070 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3071
3072
3073 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3074 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3075
3076
3077 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3078
3079
3080 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3081
3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
3083 mqd->cp_gfx_hqd_queue_priority);
3084 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3085
3086
3087 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3088 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3089
3090
3091 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3092 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3093
3094
3095 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3096
3097
3098 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3099 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3100
3101
3102 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3103
3104
3105 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3106
3107 return 0;
3108}
3109#endif
3110
3111static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
3112{
3113 struct amdgpu_device *adev = ring->adev;
3114 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
3115 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3116
3117 if (!adev->in_gpu_reset && !adev->in_suspend) {
3118 memset((void *)mqd, 0, sizeof(*mqd));
3119 mutex_lock(&adev->srbm_mutex);
3120 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3121 gfx_v10_0_gfx_mqd_init(ring);
3122#ifdef BRING_UP_DEBUG
3123 gfx_v10_0_gfx_queue_init_register(ring);
3124#endif
3125 nv_grbm_select(adev, 0, 0, 0, 0);
3126 mutex_unlock(&adev->srbm_mutex);
3127 if (adev->gfx.me.mqd_backup[mqd_idx])
3128 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3129 } else if (adev->in_gpu_reset) {
3130
3131 if (adev->gfx.me.mqd_backup[mqd_idx])
3132 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3133
3134 ring->wptr = 0;
3135 adev->wb.wb[ring->wptr_offs] = 0;
3136 amdgpu_ring_clear_ring(ring);
3137#ifdef BRING_UP_DEBUG
3138 mutex_lock(&adev->srbm_mutex);
3139 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3140 gfx_v10_0_gfx_queue_init_register(ring);
3141 nv_grbm_select(adev, 0, 0, 0, 0);
3142 mutex_unlock(&adev->srbm_mutex);
3143#endif
3144 } else {
3145 amdgpu_ring_clear_ring(ring);
3146 }
3147
3148 return 0;
3149}
3150
3151#ifndef BRING_UP_DEBUG
3152static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
3153{
3154 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3155 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3156 int r, i;
3157
3158 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3159 return -EINVAL;
3160
3161 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3162 adev->gfx.num_gfx_rings);
3163 if (r) {
3164 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3165 return r;
3166 }
3167
3168 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3169 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3170
3171 r = amdgpu_ring_test_ring(kiq_ring);
3172 if (r) {
3173 DRM_ERROR("kfq enable failed\n");
3174 kiq_ring->sched.ready = false;
3175 }
3176 return r;
3177}
3178#endif
3179
3180static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3181{
3182 int r, i;
3183 struct amdgpu_ring *ring;
3184
3185 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3186 ring = &adev->gfx.gfx_ring[i];
3187
3188 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3189 if (unlikely(r != 0))
3190 goto done;
3191
3192 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3193 if (!r) {
3194 r = gfx_v10_0_gfx_init_queue(ring);
3195 amdgpu_bo_kunmap(ring->mqd_obj);
3196 ring->mqd_ptr = NULL;
3197 }
3198 amdgpu_bo_unreserve(ring->mqd_obj);
3199 if (r)
3200 goto done;
3201 }
3202#ifndef BRING_UP_DEBUG
3203 r = gfx_v10_0_kiq_enable_kgq(adev);
3204 if (r)
3205 goto done;
3206#endif
3207 r = gfx_v10_0_cp_gfx_start(adev);
3208 if (r)
3209 goto done;
3210
3211 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3212 ring = &adev->gfx.gfx_ring[i];
3213 ring->sched.ready = true;
3214 }
3215done:
3216 return r;
3217}
3218
3219static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
3220{
3221 struct amdgpu_device *adev = ring->adev;
3222 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3223 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3224 uint32_t tmp;
3225
3226 mqd->header = 0xC0310800;
3227 mqd->compute_pipelinestat_enable = 0x00000001;
3228 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3229 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3230 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3231 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3232 mqd->compute_misc_reserved = 0x00000003;
3233
3234 eop_base_addr = ring->eop_gpu_addr >> 8;
3235 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3236 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3237
3238
3239 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
3240 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3241 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
3242
3243 mqd->cp_hqd_eop_control = tmp;
3244
3245
3246 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3247
3248 if (ring->use_doorbell) {
3249 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3250 DOORBELL_OFFSET, ring->doorbell_index);
3251 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3252 DOORBELL_EN, 1);
3253 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3254 DOORBELL_SOURCE, 0);
3255 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3256 DOORBELL_HIT, 0);
3257 } else {
3258 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3259 DOORBELL_EN, 0);
3260 }
3261
3262 mqd->cp_hqd_pq_doorbell_control = tmp;
3263
3264
3265 ring->wptr = 0;
3266 mqd->cp_hqd_dequeue_request = 0;
3267 mqd->cp_hqd_pq_rptr = 0;
3268 mqd->cp_hqd_pq_wptr_lo = 0;
3269 mqd->cp_hqd_pq_wptr_hi = 0;
3270
3271
3272 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
3273 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
3274
3275
3276 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
3277 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3278 mqd->cp_mqd_control = tmp;
3279
3280
3281 hqd_gpu_addr = ring->gpu_addr >> 8;
3282 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3283 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3284
3285
3286 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
3287 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3288 (order_base_2(ring->ring_size / 4) - 1));
3289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3290 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3291#ifdef __BIG_ENDIAN
3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3293#endif
3294 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3295 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3296 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3297 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3298 mqd->cp_hqd_pq_control = tmp;
3299
3300
3301 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3302 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3303 mqd->cp_hqd_pq_rptr_report_addr_hi =
3304 upper_32_bits(wb_gpu_addr) & 0xffff;
3305
3306
3307 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3308 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3309 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3310
3311 tmp = 0;
3312
3313 if (ring->use_doorbell) {
3314 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
3315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3316 DOORBELL_OFFSET, ring->doorbell_index);
3317
3318 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3319 DOORBELL_EN, 1);
3320 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3321 DOORBELL_SOURCE, 0);
3322 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3323 DOORBELL_HIT, 0);
3324 }
3325
3326 mqd->cp_hqd_pq_doorbell_control = tmp;
3327
3328
3329 ring->wptr = 0;
3330 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
3331
3332
3333 mqd->cp_hqd_vmid = 0;
3334
3335 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
3336 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3337 mqd->cp_hqd_persistent_state = tmp;
3338
3339
3340 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
3341 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3342 mqd->cp_hqd_ib_control = tmp;
3343
3344
3345
3346
3347 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
3348 mqd->cp_hqd_active = 1;
3349
3350 return 0;
3351}
3352
3353static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
3354{
3355 struct amdgpu_device *adev = ring->adev;
3356 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3357 int j;
3358
3359
3360 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3361
3362
3363 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
3364 mqd->cp_hqd_eop_base_addr_lo);
3365 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
3366 mqd->cp_hqd_eop_base_addr_hi);
3367
3368
3369 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
3370 mqd->cp_hqd_eop_control);
3371
3372
3373 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3374 mqd->cp_hqd_pq_doorbell_control);
3375
3376
3377 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3378 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3379 for (j = 0; j < adev->usec_timeout; j++) {
3380 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3381 break;
3382 udelay(1);
3383 }
3384 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3385 mqd->cp_hqd_dequeue_request);
3386 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
3387 mqd->cp_hqd_pq_rptr);
3388 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3389 mqd->cp_hqd_pq_wptr_lo);
3390 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3391 mqd->cp_hqd_pq_wptr_hi);
3392 }
3393
3394
3395 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
3396 mqd->cp_mqd_base_addr_lo);
3397 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
3398 mqd->cp_mqd_base_addr_hi);
3399
3400
3401 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
3402 mqd->cp_mqd_control);
3403
3404
3405 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
3406 mqd->cp_hqd_pq_base_lo);
3407 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
3408 mqd->cp_hqd_pq_base_hi);
3409
3410
3411 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
3412 mqd->cp_hqd_pq_control);
3413
3414
3415 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3416 mqd->cp_hqd_pq_rptr_report_addr_lo);
3417 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3418 mqd->cp_hqd_pq_rptr_report_addr_hi);
3419
3420
3421 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
3422 mqd->cp_hqd_pq_wptr_poll_addr_lo);
3423 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3424 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3425
3426
3427 if (ring->use_doorbell) {
3428 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
3429 (adev->doorbell_index.kiq * 2) << 2);
3430 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
3431 (adev->doorbell_index.userqueue_end * 2) << 2);
3432 }
3433
3434 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
3435 mqd->cp_hqd_pq_doorbell_control);
3436
3437
3438 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
3439 mqd->cp_hqd_pq_wptr_lo);
3440 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
3441 mqd->cp_hqd_pq_wptr_hi);
3442
3443
3444 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3445
3446 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
3447 mqd->cp_hqd_persistent_state);
3448
3449
3450 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3451 mqd->cp_hqd_active);
3452
3453 if (ring->use_doorbell)
3454 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3455
3456 return 0;
3457}
3458
3459static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
3460{
3461 struct amdgpu_device *adev = ring->adev;
3462 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3463 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3464
3465 gfx_v10_0_kiq_setting(ring);
3466
3467 if (adev->in_gpu_reset) {
3468
3469 if (adev->gfx.mec.mqd_backup[mqd_idx])
3470 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3471
3472
3473 ring->wptr = 0;
3474 amdgpu_ring_clear_ring(ring);
3475
3476 mutex_lock(&adev->srbm_mutex);
3477 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3478 gfx_v10_0_kiq_init_register(ring);
3479 nv_grbm_select(adev, 0, 0, 0, 0);
3480 mutex_unlock(&adev->srbm_mutex);
3481 } else {
3482 memset((void *)mqd, 0, sizeof(*mqd));
3483 mutex_lock(&adev->srbm_mutex);
3484 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3485 gfx_v10_0_compute_mqd_init(ring);
3486 gfx_v10_0_kiq_init_register(ring);
3487 nv_grbm_select(adev, 0, 0, 0, 0);
3488 mutex_unlock(&adev->srbm_mutex);
3489
3490 if (adev->gfx.mec.mqd_backup[mqd_idx])
3491 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3492 }
3493
3494 return 0;
3495}
3496
3497static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
3498{
3499 struct amdgpu_device *adev = ring->adev;
3500 struct v10_compute_mqd *mqd = ring->mqd_ptr;
3501 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3502
3503 if (!adev->in_gpu_reset && !adev->in_suspend) {
3504 memset((void *)mqd, 0, sizeof(*mqd));
3505 mutex_lock(&adev->srbm_mutex);
3506 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3507 gfx_v10_0_compute_mqd_init(ring);
3508 nv_grbm_select(adev, 0, 0, 0, 0);
3509 mutex_unlock(&adev->srbm_mutex);
3510
3511 if (adev->gfx.mec.mqd_backup[mqd_idx])
3512 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3513 } else if (adev->in_gpu_reset) {
3514
3515 if (adev->gfx.mec.mqd_backup[mqd_idx])
3516 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3517
3518
3519 ring->wptr = 0;
3520 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
3521 amdgpu_ring_clear_ring(ring);
3522 } else {
3523 amdgpu_ring_clear_ring(ring);
3524 }
3525
3526 return 0;
3527}
3528
3529static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
3530{
3531 struct amdgpu_ring *ring;
3532 int r;
3533
3534 ring = &adev->gfx.kiq.ring;
3535
3536 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3537 if (unlikely(r != 0))
3538 return r;
3539
3540 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3541 if (unlikely(r != 0))
3542 return r;
3543
3544 gfx_v10_0_kiq_init_queue(ring);
3545 amdgpu_bo_kunmap(ring->mqd_obj);
3546 ring->mqd_ptr = NULL;
3547 amdgpu_bo_unreserve(ring->mqd_obj);
3548 ring->sched.ready = true;
3549 return 0;
3550}
3551
3552static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
3553{
3554 struct amdgpu_ring *ring = NULL;
3555 int r = 0, i;
3556
3557 gfx_v10_0_cp_compute_enable(adev, true);
3558
3559 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3560 ring = &adev->gfx.compute_ring[i];
3561
3562 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3563 if (unlikely(r != 0))
3564 goto done;
3565 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3566 if (!r) {
3567 r = gfx_v10_0_kcq_init_queue(ring);
3568 amdgpu_bo_kunmap(ring->mqd_obj);
3569 ring->mqd_ptr = NULL;
3570 }
3571 amdgpu_bo_unreserve(ring->mqd_obj);
3572 if (r)
3573 goto done;
3574 }
3575
3576 r = amdgpu_gfx_enable_kcq(adev);
3577done:
3578 return r;
3579}
3580
3581static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
3582{
3583 int r, i;
3584 struct amdgpu_ring *ring;
3585
3586 if (!(adev->flags & AMD_IS_APU))
3587 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3588
3589 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3590
3591 r = gfx_v10_0_cp_gfx_load_microcode(adev);
3592 if (r)
3593 return r;
3594
3595 r = gfx_v10_0_cp_compute_load_microcode(adev);
3596 if (r)
3597 return r;
3598 }
3599
3600 r = gfx_v10_0_kiq_resume(adev);
3601 if (r)
3602 return r;
3603
3604 r = gfx_v10_0_kcq_resume(adev);
3605 if (r)
3606 return r;
3607
3608 if (!amdgpu_async_gfx_ring) {
3609 r = gfx_v10_0_cp_gfx_resume(adev);
3610 if (r)
3611 return r;
3612 } else {
3613 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
3614 if (r)
3615 return r;
3616 }
3617
3618 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3619 ring = &adev->gfx.gfx_ring[i];
3620 r = amdgpu_ring_test_helper(ring);
3621 if (r)
3622 return r;
3623 }
3624
3625 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3626 ring = &adev->gfx.compute_ring[i];
3627 r = amdgpu_ring_test_helper(ring);
3628 if (r)
3629 return r;
3630 }
3631
3632 return 0;
3633}
3634
3635static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
3636{
3637 gfx_v10_0_cp_gfx_enable(adev, enable);
3638 gfx_v10_0_cp_compute_enable(adev, enable);
3639}
3640
3641static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
3642{
3643 uint32_t data, pattern = 0xDEADBEEF;
3644
3645
3646
3647 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
3648
3649 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
3650
3651 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
3652
3653 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
3654 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
3655 return true;
3656 } else {
3657 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
3658 return false;
3659 }
3660}
3661
3662static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
3663{
3664 uint32_t data;
3665
3666
3667
3668 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
3669
3670
3671 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
3672 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3673 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
3674 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3675 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3676 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3677
3678
3679 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
3680 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3681 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
3682 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3683 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3684 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3685
3686
3687 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
3688 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3689 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
3690 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3691 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3692 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3693
3694
3695 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
3696 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3697 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
3698 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3699 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3700 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3701
3702
3703 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
3704 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3705 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
3706 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3707 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3708 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3709
3710
3711 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
3712 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3713 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
3714 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3715 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3716 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3717
3718
3719 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
3720 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
3721 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
3722 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
3723 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
3724 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
3725}
3726
3727static int gfx_v10_0_hw_init(void *handle)
3728{
3729 int r;
3730 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3731
3732 if (!amdgpu_emu_mode)
3733 gfx_v10_0_init_golden_registers(adev);
3734
3735 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3736
3737
3738
3739
3740
3741 r = smu_load_microcode(&adev->smu);
3742 if (r)
3743 return r;
3744
3745 r = smu_check_fw_status(&adev->smu);
3746 if (r) {
3747 pr_err("SMC firmware status is not correct\n");
3748 return r;
3749 }
3750 }
3751
3752
3753 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
3754 gfx_v10_0_setup_grbm_cam_remapping(adev);
3755
3756 gfx_v10_0_constants_init(adev);
3757
3758 r = gfx_v10_0_rlc_resume(adev);
3759 if (r)
3760 return r;
3761
3762
3763
3764
3765
3766 gfx_v10_0_tcp_harvest(adev);
3767
3768 r = gfx_v10_0_cp_resume(adev);
3769 if (r)
3770 return r;
3771
3772 return r;
3773}
3774
3775#ifndef BRING_UP_DEBUG
3776static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
3777{
3778 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3779 struct amdgpu_ring *kiq_ring = &kiq->ring;
3780 int i;
3781
3782 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
3783 return -EINVAL;
3784
3785 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
3786 adev->gfx.num_gfx_rings))
3787 return -ENOMEM;
3788
3789 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3790 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
3791 PREEMPT_QUEUES, 0, 0);
3792
3793 return amdgpu_ring_test_ring(kiq_ring);
3794}
3795#endif
3796
3797static int gfx_v10_0_hw_fini(void *handle)
3798{
3799 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3800 int r;
3801
3802 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3803 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3804#ifndef BRING_UP_DEBUG
3805 if (amdgpu_async_gfx_ring) {
3806 r = gfx_v10_0_kiq_disable_kgq(adev);
3807 if (r)
3808 DRM_ERROR("KGQ disable failed\n");
3809 }
3810#endif
3811 if (amdgpu_gfx_disable_kcq(adev))
3812 DRM_ERROR("KCQ disable failed\n");
3813 if (amdgpu_sriov_vf(adev)) {
3814 gfx_v10_0_cp_gfx_enable(adev, false);
3815 return 0;
3816 }
3817 gfx_v10_0_cp_enable(adev, false);
3818 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
3819
3820 return 0;
3821}
3822
3823static int gfx_v10_0_suspend(void *handle)
3824{
3825 return gfx_v10_0_hw_fini(handle);
3826}
3827
3828static int gfx_v10_0_resume(void *handle)
3829{
3830 return gfx_v10_0_hw_init(handle);
3831}
3832
3833static bool gfx_v10_0_is_idle(void *handle)
3834{
3835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3836
3837 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3838 GRBM_STATUS, GUI_ACTIVE))
3839 return false;
3840 else
3841 return true;
3842}
3843
3844static int gfx_v10_0_wait_for_idle(void *handle)
3845{
3846 unsigned i;
3847 u32 tmp;
3848 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3849
3850 for (i = 0; i < adev->usec_timeout; i++) {
3851
3852 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
3853 GRBM_STATUS__GUI_ACTIVE_MASK;
3854
3855 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3856 return 0;
3857 udelay(1);
3858 }
3859 return -ETIMEDOUT;
3860}
3861
3862static int gfx_v10_0_soft_reset(void *handle)
3863{
3864 u32 grbm_soft_reset = 0;
3865 u32 tmp;
3866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3867
3868
3869 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3870 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3871 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3872 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
3873 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
3874 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
3875 | GRBM_STATUS__BCI_BUSY_MASK)) {
3876 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3877 GRBM_SOFT_RESET, SOFT_RESET_CP,
3878 1);
3879 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3880 GRBM_SOFT_RESET, SOFT_RESET_GFX,
3881 1);
3882 }
3883
3884 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3885 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3886 GRBM_SOFT_RESET, SOFT_RESET_CP,
3887 1);
3888 }
3889
3890
3891 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3892 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3893 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3894 GRBM_SOFT_RESET, SOFT_RESET_RLC,
3895 1);
3896
3897 if (grbm_soft_reset) {
3898
3899 gfx_v10_0_rlc_stop(adev);
3900
3901
3902 gfx_v10_0_cp_gfx_enable(adev, false);
3903
3904
3905 gfx_v10_0_cp_compute_enable(adev, false);
3906
3907 if (grbm_soft_reset) {
3908 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3909 tmp |= grbm_soft_reset;
3910 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3911 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3912 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3913
3914 udelay(50);
3915
3916 tmp &= ~grbm_soft_reset;
3917 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3918 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3919 }
3920
3921
3922 udelay(50);
3923 }
3924 return 0;
3925}
3926
3927static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3928{
3929 uint64_t clock;
3930
3931 amdgpu_gfx_off_ctrl(adev, false);
3932 mutex_lock(&adev->gfx.gpu_clock_mutex);
3933 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3934 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3935 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3936 mutex_unlock(&adev->gfx.gpu_clock_mutex);
3937 amdgpu_gfx_off_ctrl(adev, true);
3938 return clock;
3939}
3940
3941static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3942 uint32_t vmid,
3943 uint32_t gds_base, uint32_t gds_size,
3944 uint32_t gws_base, uint32_t gws_size,
3945 uint32_t oa_base, uint32_t oa_size)
3946{
3947 struct amdgpu_device *adev = ring->adev;
3948
3949
3950 gfx_v10_0_write_data_to_reg(ring, 0, false,
3951 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3952 gds_base);
3953
3954
3955 gfx_v10_0_write_data_to_reg(ring, 0, false,
3956 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3957 gds_size);
3958
3959
3960 gfx_v10_0_write_data_to_reg(ring, 0, false,
3961 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3962 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3963
3964
3965 gfx_v10_0_write_data_to_reg(ring, 0, false,
3966 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3967 (1 << (oa_size + oa_base)) - (1 << oa_base));
3968}
3969
3970static int gfx_v10_0_early_init(void *handle)
3971{
3972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3973
3974 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
3975
3976 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3977
3978 gfx_v10_0_set_kiq_pm4_funcs(adev);
3979 gfx_v10_0_set_ring_funcs(adev);
3980 gfx_v10_0_set_irq_funcs(adev);
3981 gfx_v10_0_set_gds_init(adev);
3982 gfx_v10_0_set_rlc_funcs(adev);
3983
3984 return 0;
3985}
3986
3987static int gfx_v10_0_late_init(void *handle)
3988{
3989 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3990 int r;
3991
3992 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3993 if (r)
3994 return r;
3995
3996 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3997 if (r)
3998 return r;
3999
4000 return 0;
4001}
4002
4003static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
4004{
4005 uint32_t rlc_cntl;
4006
4007
4008 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4009 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4010}
4011
4012static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
4013{
4014 uint32_t data;
4015 unsigned i;
4016
4017 data = RLC_SAFE_MODE__CMD_MASK;
4018 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4019 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4020
4021
4022 for (i = 0; i < adev->usec_timeout; i++) {
4023 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
4024 break;
4025 udelay(1);
4026 }
4027}
4028
4029static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
4030{
4031 uint32_t data;
4032
4033 data = RLC_SAFE_MODE__CMD_MASK;
4034 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
4035}
4036
4037static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4038 bool enable)
4039{
4040 uint32_t data, def;
4041
4042
4043 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
4044
4045 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4046 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4047 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4048 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4049
4050
4051 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
4052
4053 if (def != data)
4054 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4055
4056
4057 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
4058
4059 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
4060 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4061 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4062 if (def != data)
4063 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4064 }
4065
4066 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
4067 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4068 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4069 if (def != data)
4070 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4071 }
4072 }
4073 } else {
4074
4075 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4076 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4077 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4078 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
4079 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
4080 if (def != data)
4081 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4082
4083
4084 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4085 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4086 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4087 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
4088 }
4089
4090
4091 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4092 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4093 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4094 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
4095 }
4096 }
4097}
4098
4099static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
4100 bool enable)
4101{
4102 uint32_t data, def;
4103
4104
4105 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
4106
4107 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4108
4109 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4110
4111 if (def != data)
4112 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4113
4114 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4115 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4116 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4117 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4118 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4119 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4120 if (def != data)
4121 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4122
4123
4124 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4125 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4126 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4127 if (def != data)
4128 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4129 } else {
4130
4131 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4132
4133 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
4134 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
4135
4136 if (def != data)
4137 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
4138 }
4139}
4140
4141static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4142 bool enable)
4143{
4144 uint32_t def, data;
4145
4146 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
4147 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4148
4149 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4150 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4151 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4152 else
4153 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4154
4155 if (def != data)
4156 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
4157
4158
4159 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4160 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4161 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4162 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4163 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4164 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4165 if (def != data)
4166 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4167
4168
4169 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
4170 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4171 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4172 if (def != data)
4173 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
4174 } else {
4175 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4176
4177 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4178
4179 if (def != data)
4180 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
4181 }
4182}
4183
4184static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4185 bool enable)
4186{
4187 amdgpu_gfx_rlc_enter_safe_mode(adev);
4188
4189 if (enable) {
4190
4191
4192
4193 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4194
4195 gfx_v10_0_update_3d_clock_gating(adev, enable);
4196
4197 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4198 } else {
4199
4200
4201
4202 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
4203
4204 gfx_v10_0_update_3d_clock_gating(adev, enable);
4205
4206 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
4207 }
4208
4209 if (adev->cg_flags &
4210 (AMD_CG_SUPPORT_GFX_MGCG |
4211 AMD_CG_SUPPORT_GFX_CGLS |
4212 AMD_CG_SUPPORT_GFX_CGCG |
4213 AMD_CG_SUPPORT_GFX_CGLS |
4214 AMD_CG_SUPPORT_GFX_3D_CGCG |
4215 AMD_CG_SUPPORT_GFX_3D_CGLS))
4216 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
4217
4218 amdgpu_gfx_rlc_exit_safe_mode(adev);
4219
4220 return 0;
4221}
4222
4223static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
4224 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
4225 .set_safe_mode = gfx_v10_0_set_safe_mode,
4226 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
4227 .init = gfx_v10_0_rlc_init,
4228 .get_csb_size = gfx_v10_0_get_csb_size,
4229 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
4230 .resume = gfx_v10_0_rlc_resume,
4231 .stop = gfx_v10_0_rlc_stop,
4232 .reset = gfx_v10_0_rlc_reset,
4233 .start = gfx_v10_0_rlc_start
4234};
4235
4236static int gfx_v10_0_set_powergating_state(void *handle,
4237 enum amd_powergating_state state)
4238{
4239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4240 bool enable = (state == AMD_PG_STATE_GATE);
4241 switch (adev->asic_type) {
4242 case CHIP_NAVI10:
4243 case CHIP_NAVI14:
4244 if (!enable) {
4245 amdgpu_gfx_off_ctrl(adev, false);
4246 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
4247 } else
4248 amdgpu_gfx_off_ctrl(adev, true);
4249 break;
4250 default:
4251 break;
4252 }
4253 return 0;
4254}
4255
4256static int gfx_v10_0_set_clockgating_state(void *handle,
4257 enum amd_clockgating_state state)
4258{
4259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4260
4261 switch (adev->asic_type) {
4262 case CHIP_NAVI10:
4263 case CHIP_NAVI14:
4264 case CHIP_NAVI12:
4265 gfx_v10_0_update_gfx_clock_gating(adev,
4266 state == AMD_CG_STATE_GATE);
4267 break;
4268 default:
4269 break;
4270 }
4271 return 0;
4272}
4273
4274static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
4275{
4276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4277 int data;
4278
4279
4280 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
4281 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
4282 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
4283
4284
4285 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
4286 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
4287 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
4288
4289
4290 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
4291 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
4292
4293
4294 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
4295 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
4296 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
4297
4298
4299 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
4300 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
4301 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
4302
4303
4304 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
4305 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
4306 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
4307
4308
4309 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
4310 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
4311}
4312
4313static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4314{
4315 return ring->adev->wb.wb[ring->rptr_offs];
4316}
4317
4318static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4319{
4320 struct amdgpu_device *adev = ring->adev;
4321 u64 wptr;
4322
4323
4324 if (ring->use_doorbell) {
4325 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
4326 } else {
4327 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
4328 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
4329 }
4330
4331 return wptr;
4332}
4333
4334static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4335{
4336 struct amdgpu_device *adev = ring->adev;
4337
4338 if (ring->use_doorbell) {
4339
4340 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4341 WDOORBELL64(ring->doorbell_index, ring->wptr);
4342 } else {
4343 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4344 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
4345 }
4346}
4347
4348static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4349{
4350 return ring->adev->wb.wb[ring->rptr_offs];
4351}
4352
4353static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4354{
4355 u64 wptr;
4356
4357
4358 if (ring->use_doorbell)
4359 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4360 else
4361 BUG();
4362 return wptr;
4363}
4364
4365static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4366{
4367 struct amdgpu_device *adev = ring->adev;
4368
4369
4370 if (ring->use_doorbell) {
4371 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4372 WDOORBELL64(ring->doorbell_index, ring->wptr);
4373 } else {
4374 BUG();
4375 }
4376}
4377
4378static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4379{
4380 struct amdgpu_device *adev = ring->adev;
4381 u32 ref_and_mask, reg_mem_engine;
4382 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4383
4384 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
4385 switch (ring->me) {
4386 case 1:
4387 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4388 break;
4389 case 2:
4390 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4391 break;
4392 default:
4393 return;
4394 }
4395 reg_mem_engine = 0;
4396 } else {
4397 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4398 reg_mem_engine = 1;
4399 }
4400
4401 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
4402 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4403 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
4404 ref_and_mask, ref_and_mask, 0x20);
4405}
4406
4407static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4408 struct amdgpu_job *job,
4409 struct amdgpu_ib *ib,
4410 uint32_t flags)
4411{
4412 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4413 u32 header, control = 0;
4414
4415 if (ib->flags & AMDGPU_IB_FLAG_CE)
4416 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
4417 else
4418 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4419
4420 control |= ib->length_dw | (vmid << 24);
4421
4422 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
4423 control |= INDIRECT_BUFFER_PRE_ENB(1);
4424
4425 if (flags & AMDGPU_IB_PREEMPTED)
4426 control |= INDIRECT_BUFFER_PRE_RESUME(1);
4427
4428 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
4429 gfx_v10_0_ring_emit_de_meta(ring,
4430 flags & AMDGPU_IB_PREEMPTED ? true : false);
4431 }
4432
4433 amdgpu_ring_write(ring, header);
4434 BUG_ON(ib->gpu_addr & 0x3);
4435 amdgpu_ring_write(ring,
4436#ifdef __BIG_ENDIAN
4437 (2 << 0) |
4438#endif
4439 lower_32_bits(ib->gpu_addr));
4440 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4441 amdgpu_ring_write(ring, control);
4442}
4443
4444static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4445 struct amdgpu_job *job,
4446 struct amdgpu_ib *ib,
4447 uint32_t flags)
4448{
4449 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
4450 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
4463 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
4464 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
4465 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
4466 }
4467
4468 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4469 BUG_ON(ib->gpu_addr & 0x3);
4470 amdgpu_ring_write(ring,
4471#ifdef __BIG_ENDIAN
4472 (2 << 0) |
4473#endif
4474 lower_32_bits(ib->gpu_addr));
4475 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4476 amdgpu_ring_write(ring, control);
4477}
4478
4479static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4480 u64 seq, unsigned flags)
4481{
4482 struct amdgpu_device *adev = ring->adev;
4483 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4484 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4485
4486
4487 if (adev->pdev->device == 0x50)
4488 int_sel = false;
4489
4490
4491 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4492 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4493 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4494 PACKET3_RELEASE_MEM_GCR_GLM_INV |
4495 PACKET3_RELEASE_MEM_GCR_GLM_WB |
4496 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4497 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4498 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
4499 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
4500 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
4501
4502
4503
4504
4505
4506 if (write64bit)
4507 BUG_ON(addr & 0x7);
4508 else
4509 BUG_ON(addr & 0x3);
4510 amdgpu_ring_write(ring, lower_32_bits(addr));
4511 amdgpu_ring_write(ring, upper_32_bits(addr));
4512 amdgpu_ring_write(ring, lower_32_bits(seq));
4513 amdgpu_ring_write(ring, upper_32_bits(seq));
4514 amdgpu_ring_write(ring, 0);
4515}
4516
4517static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4518{
4519 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4520 uint32_t seq = ring->fence_drv.sync_seq;
4521 uint64_t addr = ring->fence_drv.gpu_addr;
4522
4523 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
4524 upper_32_bits(addr), seq, 0xffffffff, 4);
4525}
4526
4527static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4528 unsigned vmid, uint64_t pd_addr)
4529{
4530 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4531
4532
4533 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4534
4535 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4536 amdgpu_ring_write(ring, 0x0);
4537 }
4538}
4539
4540static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4541 u64 seq, unsigned int flags)
4542{
4543 struct amdgpu_device *adev = ring->adev;
4544
4545
4546 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4547
4548
4549 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4550 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4551 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4552 amdgpu_ring_write(ring, lower_32_bits(addr));
4553 amdgpu_ring_write(ring, upper_32_bits(addr));
4554 amdgpu_ring_write(ring, lower_32_bits(seq));
4555
4556 if (flags & AMDGPU_FENCE_FLAG_INT) {
4557
4558 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4559 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4560 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4561 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4562 amdgpu_ring_write(ring, 0);
4563 amdgpu_ring_write(ring, 0x20000000);
4564 }
4565}
4566
4567static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
4568{
4569 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4570 amdgpu_ring_write(ring, 0);
4571}
4572
4573static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4574{
4575 uint32_t dw2 = 0;
4576
4577 if (amdgpu_mcbp)
4578 gfx_v10_0_ring_emit_ce_meta(ring,
4579 flags & AMDGPU_IB_PREEMPTED ? true : false);
4580
4581 gfx_v10_0_ring_emit_tmz(ring, true);
4582
4583 dw2 |= 0x80000000;
4584 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4585
4586 dw2 |= 0x8001;
4587
4588 dw2 |= 0x01000000;
4589
4590 dw2 |= 0x10002;
4591
4592
4593 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4594 dw2 |= 0x10000000;
4595 } else {
4596
4597
4598
4599 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4600 dw2 |= 0x10000000;
4601 }
4602
4603 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4604 amdgpu_ring_write(ring, dw2);
4605 amdgpu_ring_write(ring, 0);
4606}
4607
4608static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4609{
4610 unsigned ret;
4611
4612 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4613 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4614 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4615 amdgpu_ring_write(ring, 0);
4616 ret = ring->wptr & ring->buf_mask;
4617 amdgpu_ring_write(ring, 0x55aa55aa);
4618
4619 return ret;
4620}
4621
4622static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4623{
4624 unsigned cur;
4625 BUG_ON(offset > ring->buf_mask);
4626 BUG_ON(ring->ring[offset] != 0x55aa55aa);
4627
4628 cur = (ring->wptr - 1) & ring->buf_mask;
4629 if (likely(cur > offset))
4630 ring->ring[offset] = cur - offset;
4631 else
4632 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
4633}
4634
4635static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
4636{
4637 int i, r = 0;
4638 struct amdgpu_device *adev = ring->adev;
4639 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4640 struct amdgpu_ring *kiq_ring = &kiq->ring;
4641
4642 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4643 return -EINVAL;
4644
4645 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
4646 return -ENOMEM;
4647
4648
4649 amdgpu_ring_set_preempt_cond_exec(ring, false);
4650
4651
4652 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
4653 ring->trail_fence_gpu_addr,
4654 ++ring->trail_seq);
4655 amdgpu_ring_commit(kiq_ring);
4656
4657
4658 for (i = 0; i < adev->usec_timeout; i++) {
4659 if (ring->trail_seq ==
4660 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
4661 break;
4662 udelay(1);
4663 }
4664
4665 if (i >= adev->usec_timeout) {
4666 r = -EINVAL;
4667 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
4668 }
4669
4670
4671 amdgpu_ring_set_preempt_cond_exec(ring, true);
4672 return r;
4673}
4674
4675static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
4676{
4677 struct amdgpu_device *adev = ring->adev;
4678 struct v10_ce_ib_state ce_payload = {0};
4679 uint64_t csa_addr;
4680 int cnt;
4681
4682 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4683 csa_addr = amdgpu_csa_vaddr(ring->adev);
4684
4685 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4686 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4687 WRITE_DATA_DST_SEL(8) |
4688 WR_CONFIRM) |
4689 WRITE_DATA_CACHE_POLICY(0));
4690 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4691 offsetof(struct v10_gfx_meta_data, ce_payload)));
4692 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4693 offsetof(struct v10_gfx_meta_data, ce_payload)));
4694
4695 if (resume)
4696 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4697 offsetof(struct v10_gfx_meta_data,
4698 ce_payload),
4699 sizeof(ce_payload) >> 2);
4700 else
4701 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
4702 sizeof(ce_payload) >> 2);
4703}
4704
4705static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
4706{
4707 struct amdgpu_device *adev = ring->adev;
4708 struct v10_de_ib_state de_payload = {0};
4709 uint64_t csa_addr, gds_addr;
4710 int cnt;
4711
4712 csa_addr = amdgpu_csa_vaddr(ring->adev);
4713 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
4714 PAGE_SIZE);
4715 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4716 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4717
4718 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4719 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4720 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4721 WRITE_DATA_DST_SEL(8) |
4722 WR_CONFIRM) |
4723 WRITE_DATA_CACHE_POLICY(0));
4724 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
4725 offsetof(struct v10_gfx_meta_data, de_payload)));
4726 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
4727 offsetof(struct v10_gfx_meta_data, de_payload)));
4728
4729 if (resume)
4730 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
4731 offsetof(struct v10_gfx_meta_data,
4732 de_payload),
4733 sizeof(de_payload) >> 2);
4734 else
4735 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
4736 sizeof(de_payload) >> 2);
4737}
4738
4739static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4740{
4741 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4742 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1));
4743}
4744
4745static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4746{
4747 struct amdgpu_device *adev = ring->adev;
4748 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4749
4750 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4751 amdgpu_ring_write(ring, 0 |
4752 (5 << 8) |
4753 (1 << 20));
4754 amdgpu_ring_write(ring, reg);
4755 amdgpu_ring_write(ring, 0);
4756 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4757 kiq->reg_val_offs * 4));
4758 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4759 kiq->reg_val_offs * 4));
4760}
4761
4762static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4763 uint32_t val)
4764{
4765 uint32_t cmd = 0;
4766
4767 switch (ring->funcs->type) {
4768 case AMDGPU_RING_TYPE_GFX:
4769 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4770 break;
4771 case AMDGPU_RING_TYPE_KIQ:
4772 cmd = (1 << 16);
4773 break;
4774 default:
4775 cmd = WR_CONFIRM;
4776 break;
4777 }
4778 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4779 amdgpu_ring_write(ring, cmd);
4780 amdgpu_ring_write(ring, reg);
4781 amdgpu_ring_write(ring, 0);
4782 amdgpu_ring_write(ring, val);
4783}
4784
4785static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4786 uint32_t val, uint32_t mask)
4787{
4788 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4789}
4790
4791static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4792 uint32_t reg0, uint32_t reg1,
4793 uint32_t ref, uint32_t mask)
4794{
4795 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4796 struct amdgpu_device *adev = ring->adev;
4797 bool fw_version_ok = false;
4798
4799 fw_version_ok = adev->gfx.cp_fw_write_wait;
4800
4801 if (fw_version_ok)
4802 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4803 ref, mask, 0x20);
4804 else
4805 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4806 ref, mask);
4807}
4808
4809static void
4810gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4811 uint32_t me, uint32_t pipe,
4812 enum amdgpu_interrupt_state state)
4813{
4814 uint32_t cp_int_cntl, cp_int_cntl_reg;
4815
4816 if (!me) {
4817 switch (pipe) {
4818 case 0:
4819 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
4820 break;
4821 case 1:
4822 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
4823 break;
4824 default:
4825 DRM_DEBUG("invalid pipe %d\n", pipe);
4826 return;
4827 }
4828 } else {
4829 DRM_DEBUG("invalid me %d\n", me);
4830 return;
4831 }
4832
4833 switch (state) {
4834 case AMDGPU_IRQ_STATE_DISABLE:
4835 cp_int_cntl = RREG32(cp_int_cntl_reg);
4836 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4837 TIME_STAMP_INT_ENABLE, 0);
4838 WREG32(cp_int_cntl_reg, cp_int_cntl);
4839 break;
4840 case AMDGPU_IRQ_STATE_ENABLE:
4841 cp_int_cntl = RREG32(cp_int_cntl_reg);
4842 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4843 TIME_STAMP_INT_ENABLE, 1);
4844 WREG32(cp_int_cntl_reg, cp_int_cntl);
4845 break;
4846 default:
4847 break;
4848 }
4849}
4850
4851static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4852 int me, int pipe,
4853 enum amdgpu_interrupt_state state)
4854{
4855 u32 mec_int_cntl, mec_int_cntl_reg;
4856
4857
4858
4859
4860
4861
4862
4863 if (me == 1) {
4864 switch (pipe) {
4865 case 0:
4866 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4867 break;
4868 case 1:
4869 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4870 break;
4871 case 2:
4872 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4873 break;
4874 case 3:
4875 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4876 break;
4877 default:
4878 DRM_DEBUG("invalid pipe %d\n", pipe);
4879 return;
4880 }
4881 } else {
4882 DRM_DEBUG("invalid me %d\n", me);
4883 return;
4884 }
4885
4886 switch (state) {
4887 case AMDGPU_IRQ_STATE_DISABLE:
4888 mec_int_cntl = RREG32(mec_int_cntl_reg);
4889 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4890 TIME_STAMP_INT_ENABLE, 0);
4891 WREG32(mec_int_cntl_reg, mec_int_cntl);
4892 break;
4893 case AMDGPU_IRQ_STATE_ENABLE:
4894 mec_int_cntl = RREG32(mec_int_cntl_reg);
4895 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4896 TIME_STAMP_INT_ENABLE, 1);
4897 WREG32(mec_int_cntl_reg, mec_int_cntl);
4898 break;
4899 default:
4900 break;
4901 }
4902}
4903
4904static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4905 struct amdgpu_irq_src *src,
4906 unsigned type,
4907 enum amdgpu_interrupt_state state)
4908{
4909 switch (type) {
4910 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
4911 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
4912 break;
4913 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
4914 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
4915 break;
4916 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4917 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4918 break;
4919 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4920 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4921 break;
4922 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4923 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4924 break;
4925 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4926 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4927 break;
4928 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4929 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4930 break;
4931 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4932 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4933 break;
4934 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4935 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4936 break;
4937 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4938 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4939 break;
4940 default:
4941 break;
4942 }
4943 return 0;
4944}
4945
4946static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
4947 struct amdgpu_irq_src *source,
4948 struct amdgpu_iv_entry *entry)
4949{
4950 int i;
4951 u8 me_id, pipe_id, queue_id;
4952 struct amdgpu_ring *ring;
4953
4954 DRM_DEBUG("IH: CP EOP\n");
4955 me_id = (entry->ring_id & 0x0c) >> 2;
4956 pipe_id = (entry->ring_id & 0x03) >> 0;
4957 queue_id = (entry->ring_id & 0x70) >> 4;
4958
4959 switch (me_id) {
4960 case 0:
4961 if (pipe_id == 0)
4962 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4963 else
4964 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
4965 break;
4966 case 1:
4967 case 2:
4968 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4969 ring = &adev->gfx.compute_ring[i];
4970
4971
4972
4973 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4974 amdgpu_fence_process(ring);
4975 }
4976 break;
4977 }
4978 return 0;
4979}
4980
4981static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4982 struct amdgpu_irq_src *source,
4983 unsigned type,
4984 enum amdgpu_interrupt_state state)
4985{
4986 switch (state) {
4987 case AMDGPU_IRQ_STATE_DISABLE:
4988 case AMDGPU_IRQ_STATE_ENABLE:
4989 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4990 PRIV_REG_INT_ENABLE,
4991 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4992 break;
4993 default:
4994 break;
4995 }
4996
4997 return 0;
4998}
4999
5000static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5001 struct amdgpu_irq_src *source,
5002 unsigned type,
5003 enum amdgpu_interrupt_state state)
5004{
5005 switch (state) {
5006 case AMDGPU_IRQ_STATE_DISABLE:
5007 case AMDGPU_IRQ_STATE_ENABLE:
5008 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
5009 PRIV_INSTR_INT_ENABLE,
5010 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5011 default:
5012 break;
5013 }
5014
5015 return 0;
5016}
5017
5018static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
5019 struct amdgpu_iv_entry *entry)
5020{
5021 u8 me_id, pipe_id, queue_id;
5022 struct amdgpu_ring *ring;
5023 int i;
5024
5025 me_id = (entry->ring_id & 0x0c) >> 2;
5026 pipe_id = (entry->ring_id & 0x03) >> 0;
5027 queue_id = (entry->ring_id & 0x70) >> 4;
5028
5029 switch (me_id) {
5030 case 0:
5031 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5032 ring = &adev->gfx.gfx_ring[i];
5033
5034 if (ring->me == me_id && ring->pipe == pipe_id)
5035 drm_sched_fault(&ring->sched);
5036 }
5037 break;
5038 case 1:
5039 case 2:
5040 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5041 ring = &adev->gfx.compute_ring[i];
5042 if (ring->me == me_id && ring->pipe == pipe_id &&
5043 ring->queue == queue_id)
5044 drm_sched_fault(&ring->sched);
5045 }
5046 break;
5047 default:
5048 BUG();
5049 }
5050}
5051
5052static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
5053 struct amdgpu_irq_src *source,
5054 struct amdgpu_iv_entry *entry)
5055{
5056 DRM_ERROR("Illegal register access in command stream\n");
5057 gfx_v10_0_handle_priv_fault(adev, entry);
5058 return 0;
5059}
5060
5061static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
5062 struct amdgpu_irq_src *source,
5063 struct amdgpu_iv_entry *entry)
5064{
5065 DRM_ERROR("Illegal instruction in command stream\n");
5066 gfx_v10_0_handle_priv_fault(adev, entry);
5067 return 0;
5068}
5069
5070static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5071 struct amdgpu_irq_src *src,
5072 unsigned int type,
5073 enum amdgpu_interrupt_state state)
5074{
5075 uint32_t tmp, target;
5076 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5077
5078 if (ring->me == 1)
5079 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
5080 else
5081 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
5082 target += ring->pipe;
5083
5084 switch (type) {
5085 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5086 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5087 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5088 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5089 GENERIC2_INT_ENABLE, 0);
5090 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5091
5092 tmp = RREG32(target);
5093 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5094 GENERIC2_INT_ENABLE, 0);
5095 WREG32(target, tmp);
5096 } else {
5097 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
5098 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5099 GENERIC2_INT_ENABLE, 1);
5100 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
5101
5102 tmp = RREG32(target);
5103 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
5104 GENERIC2_INT_ENABLE, 1);
5105 WREG32(target, tmp);
5106 }
5107 break;
5108 default:
5109 BUG();
5110 break;
5111 }
5112 return 0;
5113}
5114
5115static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
5116 struct amdgpu_irq_src *source,
5117 struct amdgpu_iv_entry *entry)
5118{
5119 u8 me_id, pipe_id, queue_id;
5120 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5121
5122 me_id = (entry->ring_id & 0x0c) >> 2;
5123 pipe_id = (entry->ring_id & 0x03) >> 0;
5124 queue_id = (entry->ring_id & 0x70) >> 4;
5125 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
5126 me_id, pipe_id, queue_id);
5127
5128 amdgpu_fence_process(ring);
5129 return 0;
5130}
5131
5132static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
5133 .name = "gfx_v10_0",
5134 .early_init = gfx_v10_0_early_init,
5135 .late_init = gfx_v10_0_late_init,
5136 .sw_init = gfx_v10_0_sw_init,
5137 .sw_fini = gfx_v10_0_sw_fini,
5138 .hw_init = gfx_v10_0_hw_init,
5139 .hw_fini = gfx_v10_0_hw_fini,
5140 .suspend = gfx_v10_0_suspend,
5141 .resume = gfx_v10_0_resume,
5142 .is_idle = gfx_v10_0_is_idle,
5143 .wait_for_idle = gfx_v10_0_wait_for_idle,
5144 .soft_reset = gfx_v10_0_soft_reset,
5145 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
5146 .set_powergating_state = gfx_v10_0_set_powergating_state,
5147 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
5148};
5149
5150static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
5151 .type = AMDGPU_RING_TYPE_GFX,
5152 .align_mask = 0xff,
5153 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5154 .support_64bit_ptrs = true,
5155 .vmhub = AMDGPU_GFXHUB_0,
5156 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
5157 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
5158 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5159 .emit_frame_size =
5160 5 +
5161 7 +
5162 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5163 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5164 2 +
5165 8 +
5166 20 +
5167 4 +
5168
5169
5170
5171 5 +
5172 7 +
5173 4 +
5174 14 +
5175 31 +
5176 3 +
5177 5 +
5178 8 + 8 +
5179 2,
5180 .emit_ib_size = 4,
5181 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
5182 .emit_fence = gfx_v10_0_ring_emit_fence,
5183 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5184 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5185 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5186 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5187 .test_ring = gfx_v10_0_ring_test_ring,
5188 .test_ib = gfx_v10_0_ring_test_ib,
5189 .insert_nop = amdgpu_ring_insert_nop,
5190 .pad_ib = amdgpu_ring_generic_pad_ib,
5191 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
5192 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
5193 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
5194 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
5195 .preempt_ib = gfx_v10_0_ring_preempt_ib,
5196 .emit_tmz = gfx_v10_0_ring_emit_tmz,
5197 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5198 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5199 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5200};
5201
5202static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
5203 .type = AMDGPU_RING_TYPE_COMPUTE,
5204 .align_mask = 0xff,
5205 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5206 .support_64bit_ptrs = true,
5207 .vmhub = AMDGPU_GFXHUB_0,
5208 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5209 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5210 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5211 .emit_frame_size =
5212 20 +
5213 7 +
5214 5 +
5215 7 +
5216 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5217 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5218 2 +
5219 8 + 8 + 8,
5220 .emit_ib_size = 7,
5221 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5222 .emit_fence = gfx_v10_0_ring_emit_fence,
5223 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
5224 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
5225 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
5226 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
5227 .test_ring = gfx_v10_0_ring_test_ring,
5228 .test_ib = gfx_v10_0_ring_test_ib,
5229 .insert_nop = amdgpu_ring_insert_nop,
5230 .pad_ib = amdgpu_ring_generic_pad_ib,
5231 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5232 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5233 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5234};
5235
5236static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
5237 .type = AMDGPU_RING_TYPE_KIQ,
5238 .align_mask = 0xff,
5239 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5240 .support_64bit_ptrs = true,
5241 .vmhub = AMDGPU_GFXHUB_0,
5242 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
5243 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
5244 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5245 .emit_frame_size =
5246 20 +
5247 7 +
5248 5 +
5249 7 +
5250 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
5251 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
5252 2 +
5253 8 + 8 + 8,
5254 .emit_ib_size = 7,
5255 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
5256 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
5257 .test_ring = gfx_v10_0_ring_test_ring,
5258 .test_ib = gfx_v10_0_ring_test_ib,
5259 .insert_nop = amdgpu_ring_insert_nop,
5260 .pad_ib = amdgpu_ring_generic_pad_ib,
5261 .emit_rreg = gfx_v10_0_ring_emit_rreg,
5262 .emit_wreg = gfx_v10_0_ring_emit_wreg,
5263 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
5264 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
5265};
5266
5267static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
5268{
5269 int i;
5270
5271 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
5272
5273 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5274 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
5275
5276 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5277 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
5278}
5279
5280static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
5281 .set = gfx_v10_0_set_eop_interrupt_state,
5282 .process = gfx_v10_0_eop_irq,
5283};
5284
5285static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
5286 .set = gfx_v10_0_set_priv_reg_fault_state,
5287 .process = gfx_v10_0_priv_reg_irq,
5288};
5289
5290static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
5291 .set = gfx_v10_0_set_priv_inst_fault_state,
5292 .process = gfx_v10_0_priv_inst_irq,
5293};
5294
5295static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
5296 .set = gfx_v10_0_kiq_set_interrupt_state,
5297 .process = gfx_v10_0_kiq_irq,
5298};
5299
5300static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
5301{
5302 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5303 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
5304
5305 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
5306 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
5307
5308 adev->gfx.priv_reg_irq.num_types = 1;
5309 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
5310
5311 adev->gfx.priv_inst_irq.num_types = 1;
5312 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
5313}
5314
5315static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
5316{
5317 switch (adev->asic_type) {
5318 case CHIP_NAVI10:
5319 case CHIP_NAVI14:
5320 case CHIP_NAVI12:
5321 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
5322 break;
5323 default:
5324 break;
5325 }
5326}
5327
5328static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
5329{
5330 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
5331 adev->gfx.config.max_sh_per_se *
5332 adev->gfx.config.max_shader_engines;
5333
5334 adev->gds.gds_size = 0x10000;
5335 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
5336 adev->gds.gws_size = 64;
5337 adev->gds.oa_size = 16;
5338}
5339
5340static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
5341 u32 bitmap)
5342{
5343 u32 data;
5344
5345 if (!bitmap)
5346 return;
5347
5348 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5349 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5350
5351 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
5352}
5353
5354static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
5355{
5356 u32 data, wgp_bitmask;
5357 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
5358 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
5359
5360 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
5361 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
5362
5363 wgp_bitmask =
5364 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
5365
5366 return (~data) & wgp_bitmask;
5367}
5368
5369static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
5370{
5371 u32 wgp_idx, wgp_active_bitmap;
5372 u32 cu_bitmap_per_wgp, cu_active_bitmap;
5373
5374 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5375 cu_active_bitmap = 0;
5376
5377 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
5378
5379 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
5380 if (wgp_active_bitmap & (1 << wgp_idx))
5381 cu_active_bitmap |= cu_bitmap_per_wgp;
5382 }
5383
5384 return cu_active_bitmap;
5385}
5386
5387static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
5388 struct amdgpu_cu_info *cu_info)
5389{
5390 int i, j, k, counter, active_cu_number = 0;
5391 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5392 unsigned disable_masks[4 * 2];
5393
5394 if (!adev || !cu_info)
5395 return -EINVAL;
5396
5397 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
5398
5399 mutex_lock(&adev->grbm_idx_mutex);
5400 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5401 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5402 mask = 1;
5403 ao_bitmap = 0;
5404 counter = 0;
5405 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5406 if (i < 4 && j < 2)
5407 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
5408 adev, disable_masks[i * 2 + j]);
5409 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
5410 cu_info->bitmap[i][j] = bitmap;
5411
5412 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
5413 if (bitmap & mask) {
5414 if (counter < adev->gfx.config.max_cu_per_sh)
5415 ao_bitmap |= mask;
5416 counter++;
5417 }
5418 mask <<= 1;
5419 }
5420 active_cu_number += counter;
5421 if (i < 2 && j < 2)
5422 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5423 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
5424 }
5425 }
5426 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5427 mutex_unlock(&adev->grbm_idx_mutex);
5428
5429 cu_info->number = active_cu_number;
5430 cu_info->ao_cu_mask = ao_cu_mask;
5431 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
5432
5433 return 0;
5434}
5435
5436const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
5437{
5438 .type = AMD_IP_BLOCK_TYPE_GFX,
5439 .major = 10,
5440 .minor = 0,
5441 .rev = 0,
5442 .funcs = &gfx_v10_0_ip_funcs,
5443};
5444
