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27#ifndef __DML2_DISPLAY_MODE_VBA_H__
28#define __DML2_DISPLAY_MODE_VBA_H__
29
30#include "dml_common_defs.h"
31
32struct display_mode_lib;
33
34void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
35
36#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
37
38dml_get_attr_decl(clk_dcf_deepsleep);
39dml_get_attr_decl(wm_urgent);
40dml_get_attr_decl(wm_memory_trip);
41dml_get_attr_decl(wm_writeback_urgent);
42dml_get_attr_decl(wm_stutter_exit);
43dml_get_attr_decl(wm_stutter_enter_exit);
44dml_get_attr_decl(wm_dram_clock_change);
45dml_get_attr_decl(wm_writeback_dram_clock_change);
46dml_get_attr_decl(wm_xfc_underflow);
47dml_get_attr_decl(stutter_efficiency_no_vblank);
48dml_get_attr_decl(stutter_efficiency);
49dml_get_attr_decl(urgent_latency);
50dml_get_attr_decl(urgent_extra_latency);
51dml_get_attr_decl(nonurgent_latency);
52dml_get_attr_decl(dram_clock_change_latency);
53dml_get_attr_decl(dispclk_calculated);
54dml_get_attr_decl(total_data_read_bw);
55dml_get_attr_decl(return_bw);
56dml_get_attr_decl(tcalc);
57dml_get_attr_decl(fraction_of_urgent_bandwidth);
58dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
59
60#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
61
62dml_get_pipe_attr_decl(dsc_delay);
63dml_get_pipe_attr_decl(dppclk_calculated);
64dml_get_pipe_attr_decl(dscclk_calculated);
65dml_get_pipe_attr_decl(min_ttu_vblank);
66dml_get_pipe_attr_decl(vratio_prefetch_l);
67dml_get_pipe_attr_decl(vratio_prefetch_c);
68dml_get_pipe_attr_decl(dst_x_after_scaler);
69dml_get_pipe_attr_decl(dst_y_after_scaler);
70dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
71dml_get_pipe_attr_decl(dst_y_per_row_vblank);
72dml_get_pipe_attr_decl(dst_y_prefetch);
73dml_get_pipe_attr_decl(dst_y_per_vm_flip);
74dml_get_pipe_attr_decl(dst_y_per_row_flip);
75dml_get_pipe_attr_decl(xfc_transfer_delay);
76dml_get_pipe_attr_decl(xfc_precharge_delay);
77dml_get_pipe_attr_decl(xfc_remote_surface_flip_latency);
78dml_get_pipe_attr_decl(xfc_prefetch_margin);
79dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
80dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
81dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
82dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
83
84unsigned int get_vstartup_calculated(
85 struct display_mode_lib *mode_lib,
86 const display_e2e_pipe_params_st *pipes,
87 unsigned int num_pipes,
88 unsigned int which_pipe);
89
90double get_total_immediate_flip_bytes(
91 struct display_mode_lib *mode_lib,
92 const display_e2e_pipe_params_st *pipes,
93 unsigned int num_pipes);
94double get_total_immediate_flip_bw(
95 struct display_mode_lib *mode_lib,
96 const display_e2e_pipe_params_st *pipes,
97 unsigned int num_pipes);
98double get_total_prefetch_bw(
99 struct display_mode_lib *mode_lib,
100 const display_e2e_pipe_params_st *pipes,
101 unsigned int num_pipes);
102unsigned int dml_get_voltage_level(
103 struct display_mode_lib *mode_lib,
104 const display_e2e_pipe_params_st *pipes,
105 unsigned int num_pipes);
106
107void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
108
109bool Calculate256BBlockSizes(
110 enum source_format_class SourcePixelFormat,
111 enum dm_swizzle_mode SurfaceTiling,
112 unsigned int BytePerPixelY,
113 unsigned int BytePerPixelC,
114 unsigned int *BlockHeight256BytesY,
115 unsigned int *BlockHeight256BytesC,
116 unsigned int *BlockWidth256BytesY,
117 unsigned int *BlockWidth256BytesC);
118
119struct vba_vars_st {
120 ip_params_st ip;
121 soc_bounding_box_st soc;
122
123 int maxMpcComb;
124 bool UseMaximumVStartup;
125
126 double WritebackDISPCLK;
127 double DPPCLKUsingSingleDPPLuma;
128 double DPPCLKUsingSingleDPPChroma;
129 double DISPCLKWithRamping;
130 double DISPCLKWithoutRamping;
131 double GlobalDPPCLK;
132 double DISPCLKWithRampingRoundedToDFSGranularity;
133 double DISPCLKWithoutRampingRoundedToDFSGranularity;
134 double MaxDispclkRoundedToDFSGranularity;
135 bool DCCEnabledAnyPlane;
136 double ReturnBandwidthToDCN;
137 unsigned int TotalActiveDPP;
138 unsigned int TotalDCCActiveDPP;
139 double UrgentRoundTripAndOutOfOrderLatency;
140 double StutterPeriod;
141 double FrameTimeForMinFullDETBufferingTime;
142 double AverageReadBandwidth;
143 double TotalRowReadBandwidth;
144 double PartOfBurstThatFitsInROB;
145 double StutterBurstTime;
146 unsigned int NextPrefetchMode;
147 double NextMaxVStartup;
148 double VBlankTime;
149 double SmallestVBlank;
150 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
151 double EffectiveDETPlusLBLinesLuma;
152 double EffectiveDETPlusLBLinesChroma;
153 double UrgentLatencySupportUsLuma;
154 double UrgentLatencySupportUsChroma;
155 unsigned int DSCFormatFactor;
156
157 bool DummyPStateCheck;
158 bool DRAMClockChangeSupportsVActive;
159 bool PrefetchModeSupported;
160 bool PrefetchAndImmediateFlipSupported;
161 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank;
162 double XFCRemoteSurfaceFlipDelay;
163 double TInitXFill;
164 double TslvChk;
165 double SrcActiveDrainRate;
166 bool ImmediateFlipSupported;
167 enum mpc_combine_affinity WhenToDoMPCCombine;
168
169 bool PrefetchERROR;
170
171 unsigned int VStartupLines;
172 unsigned int ActiveDPPs;
173 unsigned int LBLatencyHidingSourceLinesY;
174 unsigned int LBLatencyHidingSourceLinesC;
175 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
176 double MinActiveDRAMClockChangeMargin;
177 double InitFillLevel;
178 double FinalFillMargin;
179 double FinalFillLevel;
180 double RemainingFillLevel;
181 double TFinalxFill;
182
183
184
185
186 double SRExitTime;
187 double SREnterPlusExitTime;
188 double UrgentLatencyPixelDataOnly;
189 double UrgentLatencyPixelMixedWithVMData;
190 double UrgentLatencyVMDataOnly;
191 double UrgentLatency;
192 double WritebackLatency;
193 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly;
194 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData;
195 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
196 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation;
197 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation;
198 double NumberOfChannels;
199 double DRAMChannelWidth;
200 double FabricDatapathToDCNDataReturn;
201 double ReturnBusWidth;
202 double Downspreading;
203 double DISPCLKDPPCLKDSCCLKDownSpreading;
204 double DISPCLKDPPCLKVCOSpeed;
205 double RoundTripPingLatencyCycles;
206 double UrgentOutOfOrderReturnPerChannel;
207 double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
208 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
209 double UrgentOutOfOrderReturnPerChannelVMDataOnly;
210 unsigned int VMMPageSize;
211 double DRAMClockChangeLatency;
212 double XFCBusTransportTime;
213 bool UseUrgentBurstBandwidth;
214 double XFCXBUFLatencyTolerance;
215
216
217
218
219 unsigned int ROBBufferSizeInKByte;
220 double DETBufferSizeInKByte;
221 double DETBufferSizeInTime;
222 unsigned int DPPOutputBufferPixels;
223 unsigned int OPPOutputBufferLines;
224 unsigned int PixelChunkSizeInKByte;
225 double ReturnBW;
226 bool GPUVMEnable;
227 bool HostVMEnable;
228 unsigned int GPUVMMaxPageTableLevels;
229 unsigned int HostVMMaxPageTableLevels;
230 unsigned int HostVMCachedPageTableLevels;
231 unsigned int OverrideGPUVMPageTableLevels;
232 unsigned int OverrideHostVMPageTableLevels;
233 unsigned int MetaChunkSize;
234 double MinPixelChunkSizeBytes;
235 double MinMetaChunkSizeBytes;
236 unsigned int WritebackChunkSize;
237 bool ODMCapability;
238 unsigned int NumberOfDSC;
239 unsigned int LineBufferSize;
240 unsigned int MaxLineBufferLines;
241 unsigned int WritebackInterfaceLumaBufferSize;
242 unsigned int WritebackInterfaceChromaBufferSize;
243 unsigned int WritebackChromaLineBufferWidth;
244 enum writeback_config WritebackConfiguration;
245 double MaxDCHUBToPSCLThroughput;
246 double MaxPSCLToLBThroughput;
247 unsigned int PTEBufferSizeInRequestsLuma;
248 unsigned int PTEBufferSizeInRequestsChroma;
249 double DISPCLKRampingMargin;
250 unsigned int MaxInterDCNTileRepeaters;
251 bool XFCSupported;
252 double XFCSlvChunkSize;
253 double XFCFillBWOverhead;
254 double XFCFillConstant;
255 double XFCTSlvVupdateOffset;
256 double XFCTSlvVupdateWidth;
257 double XFCTSlvVreadyOffset;
258 double DPPCLKDelaySubtotal;
259 double DPPCLKDelaySCL;
260 double DPPCLKDelaySCLLBOnly;
261 double DPPCLKDelayCNVCFormater;
262 double DPPCLKDelayCNVCCursor;
263 double DISPCLKDelaySubtotal;
264 bool ProgressiveToInterlaceUnitInOPP;
265
266 int VoltageLevel;
267 double FabricClock;
268 double DRAMSpeed;
269 double DISPCLK;
270 double SOCCLK;
271 double DCFCLK;
272
273 unsigned int NumberOfActivePlanes;
274 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
275 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
276 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
277 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
278 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
279 unsigned int PitchY[DC__NUM_DPP__MAX];
280 unsigned int PitchC[DC__NUM_DPP__MAX];
281 double HRatio[DC__NUM_DPP__MAX];
282 double VRatio[DC__NUM_DPP__MAX];
283 unsigned int htaps[DC__NUM_DPP__MAX];
284 unsigned int vtaps[DC__NUM_DPP__MAX];
285 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
286 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
287 unsigned int HTotal[DC__NUM_DPP__MAX];
288 unsigned int VTotal[DC__NUM_DPP__MAX];
289 unsigned int VTotal_Max[DC__NUM_DPP__MAX];
290 unsigned int VTotal_Min[DC__NUM_DPP__MAX];
291 int DPPPerPlane[DC__NUM_DPP__MAX];
292 double PixelClock[DC__NUM_DPP__MAX];
293 double PixelClockBackEnd[DC__NUM_DPP__MAX];
294 bool DCCEnable[DC__NUM_DPP__MAX];
295 bool FECEnable[DC__NUM_DPP__MAX];
296 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
297 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
298 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
299 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
300 bool WritebackEnable[DC__NUM_DPP__MAX];
301 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
302 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
303 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
304 double WritebackSourceHeight[DC__NUM_DPP__MAX];
305 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
306 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
307 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
308 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
309 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
310 double WritebackHRatio[DC__NUM_DPP__MAX];
311 double WritebackVRatio[DC__NUM_DPP__MAX];
312 unsigned int HActive[DC__NUM_DPP__MAX];
313 unsigned int VActive[DC__NUM_DPP__MAX];
314 bool Interlace[DC__NUM_DPP__MAX];
315 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
316 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
317 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
318 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
319 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
320 double DCCRate[DC__NUM_DPP__MAX];
321 double AverageDCCCompressionRate;
322 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
323 double OutputBpp[DC__NUM_DPP__MAX];
324 bool DSCEnabled[DC__NUM_DPP__MAX];
325 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
326 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
327 enum output_encoder_class Output[DC__NUM_DPP__MAX];
328 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
329 bool SynchronizedVBlank;
330 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
331 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
332 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
333 bool XFCEnabled[DC__NUM_DPP__MAX];
334 bool ScalerEnabled[DC__NUM_DPP__MAX];
335
336
337 bool ImmediateFlipSupport;
338 double DETBufferSizeY[DC__NUM_DPP__MAX];
339 double DETBufferSizeC[DC__NUM_DPP__MAX];
340 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
341 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
342 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
343 double LastPixelOfLineExtraWatermark;
344 double TotalDataReadBandwidth;
345 unsigned int TotalActiveWriteback;
346 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
347 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
348 double BandwidthAvailableForImmediateFlip;
349 unsigned int PrefetchMode[DC__VOLTAGE_STATES + 1][2];
350 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES + 1][2];
351 unsigned int MinPrefetchMode;
352 unsigned int MaxPrefetchMode;
353 bool AnyLinesForVMOrRowTooLarge;
354 double MaxVStartup;
355 bool IgnoreViewportPositioning;
356 bool ErrorResult[DC__NUM_DPP__MAX];
357
358
359
360 double DCFCLKDeepSleep;
361 double UrgentWatermark;
362 double UrgentExtraLatency;
363 double WritebackUrgentWatermark;
364 double StutterExitWatermark;
365 double StutterEnterPlusExitWatermark;
366 double DRAMClockChangeWatermark;
367 double WritebackDRAMClockChangeWatermark;
368 double StutterEfficiency;
369 double StutterEfficiencyNotIncludingVBlank;
370 double NonUrgentLatencyTolerance;
371 double MinActiveDRAMClockChangeLatencySupported;
372
373
374
375
376 double DISPCLK_calculated;
377 double DPPCLK_calculated[DC__NUM_DPP__MAX];
378
379 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
380 double VUpdateWidthPix[DC__NUM_DPP__MAX];
381 double VReadyOffsetPix[DC__NUM_DPP__MAX];
382
383 unsigned int TotImmediateFlipBytes;
384 double TCalc;
385
386 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
387 unsigned int cache_num_pipes;
388 unsigned int pipe_plane[DC__NUM_DPP__MAX];
389
390
391
392 bool EmbeddedPanel[DC__NUM_DPP__MAX];
393 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
394 double MaxHSCLRatio;
395 double MaxVSCLRatio;
396 unsigned int MaxNumWriteback;
397 bool WritebackLumaAndChromaScalingSupported;
398 bool Cursor64BppSupport;
399 double DCFCLKPerState[DC__VOLTAGE_STATES + 1];
400 double DCFCLKState[DC__VOLTAGE_STATES + 1][2];
401 double FabricClockPerState[DC__VOLTAGE_STATES + 1];
402 double SOCCLKPerState[DC__VOLTAGE_STATES + 1];
403 double PHYCLKPerState[DC__VOLTAGE_STATES + 1];
404 double DTBCLKPerState[DC__VOLTAGE_STATES + 1];
405 double MaxDppclk[DC__VOLTAGE_STATES + 1];
406 double MaxDSCCLK[DC__VOLTAGE_STATES + 1];
407 double DRAMSpeedPerState[DC__VOLTAGE_STATES + 1];
408 double MaxDispclk[DC__VOLTAGE_STATES + 1];
409 int VoltageOverrideLevel;
410
411
412 bool ScaleRatioAndTapsSupport;
413 bool SourceFormatPixelAndScanSupport;
414 double TotalBandwidthConsumedGBytePerSecond;
415 bool DCCEnabledInAnyPlane;
416 bool WritebackLatencySupport;
417 bool WritebackModeSupport;
418 bool Writeback10bpc420Supported;
419 bool BandwidthSupport[DC__VOLTAGE_STATES + 1];
420 unsigned int TotalNumberOfActiveWriteback;
421 double CriticalPoint;
422 double ReturnBWToDCNPerState;
423 bool IsErrorResult[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
424 bool prefetch_vm_bw_valid;
425 bool prefetch_row_bw_valid;
426 bool NumberOfOTGSupport;
427 bool NonsupportedDSCInputBPC;
428 bool WritebackScaleRatioAndTapsSupport;
429 bool CursorSupport;
430 bool PitchSupport;
431 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES + 1];
432
433 double WritebackLineBufferLumaBufferSize;
434 double WritebackLineBufferChromaBufferSize;
435 double WritebackMinHSCLRatio;
436 double WritebackMinVSCLRatio;
437 double WritebackMaxHSCLRatio;
438 double WritebackMaxVSCLRatio;
439 double WritebackMaxHSCLTaps;
440 double WritebackMaxVSCLTaps;
441 unsigned int MaxNumDPP;
442 unsigned int MaxNumOTG;
443 double CursorBufferSize;
444 double CursorChunkSize;
445 unsigned int Mode;
446 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
447 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX];
448 double ImmediateFlipBW[DC__NUM_DPP__MAX];
449 double MaxMaxVStartup[DC__VOLTAGE_STATES + 1][2];
450
451 double WritebackLumaVExtra;
452 double WritebackChromaVExtra;
453 double WritebackRequiredDISPCLK;
454 double MaximumSwathWidthSupport;
455 double MaximumSwathWidthInDETBuffer;
456 double MaximumSwathWidthInLineBuffer;
457 double MaxDispclkRoundedDownToDFSGranularity;
458 double MaxDppclkRoundedDownToDFSGranularity;
459 double PlaneRequiredDISPCLKWithoutODMCombine;
460 double PlaneRequiredDISPCLKWithODMCombine;
461 double PlaneRequiredDISPCLK;
462 double TotalNumberOfActiveOTG;
463 double FECOverhead;
464 double EffectiveFECOverhead;
465 double Outbpp;
466 unsigned int OutbppDSC;
467 double TotalDSCUnitsRequired;
468 double bpp;
469 unsigned int slices;
470 double SwathWidthGranularityY;
471 double RoundedUpMaxSwathSizeBytesY;
472 double SwathWidthGranularityC;
473 double RoundedUpMaxSwathSizeBytesC;
474 double EffectiveDETLBLinesLuma;
475 double EffectiveDETLBLinesChroma;
476 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES + 1][2];
477 double PDEAndMetaPTEBytesPerFrameY;
478 double PDEAndMetaPTEBytesPerFrameC;
479 unsigned int MetaRowBytesY;
480 unsigned int MetaRowBytesC;
481 unsigned int DPTEBytesPerRowC;
482 unsigned int DPTEBytesPerRowY;
483 double ExtraLatency;
484 double TimeCalc;
485 double TWait;
486 double MaximumReadBandwidthWithPrefetch;
487 double MaximumReadBandwidthWithoutPrefetch;
488 double total_dcn_read_bw_with_flip;
489 double total_dcn_read_bw_with_flip_no_urgent_burst;
490 double FractionOfUrgentBandwidth;
491 double FractionOfUrgentBandwidthImmediateFlip;
492
493
494 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES + 1][2];
495 unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
496 int NoOfDPPThisState[DC__NUM_DPP__MAX];
497 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
498 double SwathWidthYThisState[DC__NUM_DPP__MAX];
499 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
500 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
501 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
502 double VRatioPreY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
503 double VRatioPreC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
504 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
505 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
506 double RequiredDPPCLK[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
507 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
508 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
509 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
510 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
511 bool PrefetchSupported[DC__VOLTAGE_STATES + 1][2];
512 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES + 1][2];
513 double RequiredDISPCLK[DC__VOLTAGE_STATES + 1][2];
514 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES + 1][2];
515 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES + 1][2];
516 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES + 1][2];
517 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES + 1][2];
518 bool ModeSupport[DC__VOLTAGE_STATES + 1][2];
519 double ReturnBWPerState[DC__VOLTAGE_STATES + 1][2];
520 bool DIOSupport[DC__VOLTAGE_STATES + 1];
521 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES + 1];
522 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
523 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES + 1];
524 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES + 1];
525 bool ROBSupport[DC__VOLTAGE_STATES + 1][2];
526 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES + 1][2];
527 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES + 1][2];
528 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES + 1][2];
529 double PrefetchBW[DC__NUM_DPP__MAX];
530 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
531 double MetaRowBytes[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
532 double DPTEBytesPerRow[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
533 double PrefetchLinesY[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
534 double PrefetchLinesC[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
535 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
536 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
537 double PrefillY[DC__NUM_DPP__MAX];
538 double PrefillC[DC__NUM_DPP__MAX];
539 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
540 double LinesForMetaPTE[DC__NUM_DPP__MAX];
541 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
542 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
543 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
544 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
545 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
546 bool RequiresDSC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
547 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
548 double RequiresFEC[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
549 double OutputBppPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
550 double DSCDelayPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
551 bool ViewportSizeSupport[DC__VOLTAGE_STATES + 1][2];
552 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
553 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
554 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
555 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
556 double MaxSwathHeightY[DC__NUM_DPP__MAX];
557 double MaxSwathHeightC[DC__NUM_DPP__MAX];
558 double MinSwathHeightY[DC__NUM_DPP__MAX];
559 double MinSwathHeightC[DC__NUM_DPP__MAX];
560 double ReadBandwidthLuma[DC__NUM_DPP__MAX];
561 double ReadBandwidthChroma[DC__NUM_DPP__MAX];
562 double ReadBandwidth[DC__NUM_DPP__MAX];
563 double WriteBandwidth[DC__NUM_DPP__MAX];
564 double PSCL_FACTOR[DC__NUM_DPP__MAX];
565 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
566 double MaximumVStartup[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
567 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
568 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
569 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
570 double AlignedYPitch[DC__NUM_DPP__MAX];
571 double AlignedCPitch[DC__NUM_DPP__MAX];
572 double MaximumSwathWidth[DC__NUM_DPP__MAX];
573 double cursor_bw[DC__NUM_DPP__MAX];
574 double cursor_bw_pre[DC__NUM_DPP__MAX];
575 double Tno_bw[DC__NUM_DPP__MAX];
576 double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
577 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
578 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
579 double final_flip_bw[DC__NUM_DPP__MAX];
580 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES + 1][2];
581 double WritebackDelay[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
582 unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
583 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
584 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
585 unsigned int meta_req_height[DC__NUM_DPP__MAX];
586 unsigned int meta_req_width[DC__NUM_DPP__MAX];
587 unsigned int meta_row_height[DC__NUM_DPP__MAX];
588 unsigned int meta_row_width[DC__NUM_DPP__MAX];
589 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
590 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
591 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
592 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
593 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
594 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
595 double meta_row_bw[DC__NUM_DPP__MAX];
596 double dpte_row_bw[DC__NUM_DPP__MAX];
597 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX];
598 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX];
599 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
600 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
601 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES + 1][2];
602 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
603 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
604 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
605 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
606 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
607 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
608
609
610 bool MPCCombine[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
611 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
612 double MaximumSwathWidthInLineBufferLuma;
613 double MaximumSwathWidthInLineBufferChroma;
614 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
615 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
616 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
617 double dummy1[DC__NUM_DPP__MAX];
618 double dummy2[DC__NUM_DPP__MAX];
619 double dummy3[DC__NUM_DPP__MAX];
620 double dummy4[DC__NUM_DPP__MAX];
621 double dummy5;
622 double dummy6;
623 double dummy7[DC__NUM_DPP__MAX];
624 double dummy8[DC__NUM_DPP__MAX];
625 unsigned int dummyinteger1ms[DC__NUM_DPP__MAX];
626 double dummyinteger2ms[DC__NUM_DPP__MAX];
627 unsigned int dummyinteger3[DC__NUM_DPP__MAX];
628 unsigned int dummyinteger4[DC__NUM_DPP__MAX];
629 unsigned int dummyinteger5;
630 unsigned int dummyinteger6;
631 unsigned int dummyinteger7;
632 unsigned int dummyinteger8;
633 unsigned int dummyinteger9;
634 unsigned int dummyinteger10;
635 unsigned int dummyinteger11;
636 unsigned int dummyinteger12;
637 unsigned int dummyintegerarr1[DC__NUM_DPP__MAX];
638 unsigned int dummyintegerarr2[DC__NUM_DPP__MAX];
639 unsigned int dummyintegerarr3[DC__NUM_DPP__MAX];
640 unsigned int dummyintegerarr4[DC__NUM_DPP__MAX];
641 bool dummysinglestring;
642 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
643 double PlaneRequiredDISPCLKWithODMCombine2To1;
644 double PlaneRequiredDISPCLKWithODMCombine4To1;
645 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES + 1][2];
646 bool LinkDSCEnable;
647 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES + 1];
648 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
649 double SwathWidthCThisState[DC__NUM_DPP__MAX];
650 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
651 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
652 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
653
654 unsigned int NotEnoughUrgentLatencyHiding;
655 unsigned int NotEnoughUrgentLatencyHidingPre;
656 int PTEBufferSizeInRequestsForLuma;
657 int PTEBufferSizeInRequestsForChroma;
658
659
660 int dpte_group_bytes_chroma;
661 unsigned int vm_group_bytes_chroma;
662 double dst_x_after_scaler;
663 double dst_y_after_scaler;
664 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
665
666
667 double PrefetchBandwidth[DC__NUM_DPP__MAX];
668 double VInitPreFillY[DC__NUM_DPP__MAX];
669 double VInitPreFillC[DC__NUM_DPP__MAX];
670 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
671 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
672 unsigned int VStartup[DC__NUM_DPP__MAX];
673 double DSTYAfterScaler[DC__NUM_DPP__MAX];
674 double DSTXAfterScaler[DC__NUM_DPP__MAX];
675 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
676 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
677 double VRatioPrefetchY[DC__NUM_DPP__MAX];
678 double VRatioPrefetchC[DC__NUM_DPP__MAX];
679 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
680 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
681 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
682 double MinTTUVBlank[DC__NUM_DPP__MAX];
683 double BytePerPixelDETY[DC__NUM_DPP__MAX];
684 double BytePerPixelDETC[DC__NUM_DPP__MAX];
685 double SwathWidthY[DC__NUM_DPP__MAX];
686 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
687 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
688 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
689 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
690 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
691 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
692 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
693 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
694 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
695 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
696 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
697 double MetaRowByte[DC__NUM_DPP__MAX];
698 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
699 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
700 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
701 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
702 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
703 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
704 double DSCCLK_calculated[DC__NUM_DPP__MAX];
705 unsigned int DSCDelay[DC__NUM_DPP__MAX];
706 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
707 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
708 double DPPCLK[DC__NUM_DPP__MAX];
709 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
710 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
711 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
712 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
713 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
714 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
715 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
716 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
717 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
718 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
719 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
720 double XFCTransferDelay[DC__NUM_DPP__MAX];
721 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
722 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
723 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
724 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
725 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
726 double FullDETBufferingTimeY[DC__NUM_DPP__MAX];
727 double FullDETBufferingTimeC[DC__NUM_DPP__MAX];
728 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
729 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
730 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
731 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
732 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
733 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
734 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
735 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
736 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
737 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
738 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
739 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
740 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
741 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
742 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
743 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
744 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
745 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
746 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
747 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
748 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
749 double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
750 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
751 double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
752 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
753 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
754 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
755 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
756 double LinesToFinishSwathTransferStutterCriticalPlane;
757 unsigned int BytePerPixelYCriticalPlane;
758 double SwathWidthYCriticalPlane;
759 double LinesInDETY[DC__NUM_DPP__MAX];
760 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
761
762 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
763 double SwathWidthC[DC__NUM_DPP__MAX];
764 unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
765 unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
766 unsigned int dummyinteger1;
767 unsigned int dummyinteger2;
768 double FinalDRAMClockChangeLatency;
769 double Tdmdl_vm[DC__NUM_DPP__MAX];
770 double Tdmdl[DC__NUM_DPP__MAX];
771 unsigned int ThisVStartup;
772 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
773 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
774 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
775 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
776 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
777 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
778 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
779 unsigned int DCCCIndependent64ByteBlock[DC__NUM_DPP__MAX];
780 double VStartupMargin;
781 bool NotEnoughTimeForDynamicMetadata;
782
783
784 unsigned int MaximumMaxVStartupLines;
785 double FabricAndDRAMBandwidth;
786 double LinesInDETLuma;
787 double LinesInDETChroma;
788 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
789 unsigned int LinesInDETC[DC__NUM_DPP__MAX];
790 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
791 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
792 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
793 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES + 1];
794 bool UrgentLatencySupport[DC__VOLTAGE_STATES + 1][2];
795 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
796 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
797 double qual_row_bw[DC__NUM_DPP__MAX];
798 double prefetch_row_bw[DC__NUM_DPP__MAX];
799 double prefetch_vm_bw[DC__NUM_DPP__MAX];
800
801 double PTEGroupSize;
802 unsigned int PDEProcessingBufIn64KBReqs;
803
804 double MaxTotalVActiveRDBandwidth;
805 bool DoUrgentLatencyAdjustment;
806 double UrgentLatencyAdjustmentFabricClockComponent;
807 double UrgentLatencyAdjustmentFabricClockReference;
808 double MinUrgentLatencySupportUs;
809 double MinFullDETBufferingTime;
810 double AverageReadBandwidthGBytePerSecond;
811 bool FirstMainPlane;
812
813 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
814 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
815 double HRatioChroma[DC__NUM_DPP__MAX];
816 double VRatioChroma[DC__NUM_DPP__MAX];
817 int WritebackSourceWidth[DC__NUM_DPP__MAX];
818
819 bool ModeIsSupported;
820 bool ODMCombine4To1Supported;
821
822 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
823 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
824 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
825 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
826 unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
827 unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
828 bool DSCEnable[DC__NUM_DPP__MAX];
829
830 double DRAMClockChangeLatencyOverride;
831
832 double GPUVMMinPageSize;
833 double HostVMMinPageSize;
834
835 bool MPCCombineEnable[DC__NUM_DPP__MAX];
836 unsigned int HostVMMaxNonCachedPageTableLevels;
837 bool DynamicMetadataVMEnabled;
838 double WritebackInterfaceBufferSize;
839 double WritebackLineBufferSize;
840
841 double DCCRateLuma[DC__NUM_DPP__MAX];
842 double DCCRateChroma[DC__NUM_DPP__MAX];
843
844 double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
845 int MinVoltageLevel;
846 int MaxVoltageLevel;
847
848 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
849 bool NumberOfHDMIFRLSupport;
850 unsigned int MaxNumHDMIFRLOutputs;
851 int AudioSampleRate[DC__NUM_DPP__MAX];
852 int AudioSampleLayout[DC__NUM_DPP__MAX];
853
854 int PercentMarginOverMinimumRequiredDCFCLK;
855 bool DynamicMetadataSupported[DC__VOLTAGE_STATES + 1][2];
856 enum immediate_flip_requirement ImmediateFlipRequirement;
857 double DETBufferSizeYThisState[DC__NUM_DPP__MAX];
858 double DETBufferSizeCThisState[DC__NUM_DPP__MAX];
859 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
860 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
861 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
862 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
863 double UrgLatency[DC__VOLTAGE_STATES + 1];
864 double VActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
865 double VActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
866 bool NoTimeForPrefetch[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
867 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
868 double dpte_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
869 double meta_row_bandwidth[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
870 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
871 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
872 int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
873 int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
874 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES + 1][2];
875 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
876 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
877 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
878 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES + 1][2][DC__NUM_DPP__MAX];
879 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES + 1][2];
880 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2];
881 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2];
882 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2];
883 bool UseMinimumRequiredDCFCLK;
884 double WritebackDelayTime[DC__NUM_DPP__MAX];
885 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
886 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
887 unsigned int dummyinteger15;
888 unsigned int dummyinteger16;
889 unsigned int dummyinteger17;
890 unsigned int dummyinteger18;
891 unsigned int dummyinteger19;
892 unsigned int dummyinteger20;
893 unsigned int dummyinteger21;
894 unsigned int dummyinteger22;
895 unsigned int dummyinteger23;
896 unsigned int dummyinteger24;
897 unsigned int dummyinteger25;
898 unsigned int dummyinteger26;
899 unsigned int dummyinteger27;
900 unsigned int dummyinteger28;
901 unsigned int dummyinteger29;
902 bool dummystring[DC__NUM_DPP__MAX];
903 double BPP;
904 enum odm_combine_policy ODMCombinePolicy;
905};
906
907bool CalculateMinAndMaxPrefetchMode(
908 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
909 unsigned int *MinPrefetchMode,
910 unsigned int *MaxPrefetchMode);
911
912double CalculateWriteBackDISPCLK(
913 enum source_format_class WritebackPixelFormat,
914 double PixelClock,
915 double WritebackHRatio,
916 double WritebackVRatio,
917 unsigned int WritebackLumaHTaps,
918 unsigned int WritebackLumaVTaps,
919 unsigned int WritebackChromaHTaps,
920 unsigned int WritebackChromaVTaps,
921 double WritebackDestinationWidth,
922 unsigned int HTotal,
923 unsigned int WritebackChromaLineBufferWidth);
924
925#endif
926
