LXR linux/drivers/gpu/drm/amd/display/dc/inc/dce

   1/*
   2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26/**
  27 * Bandwidth and Watermark calculations interface.
  28 * (Refer to "DCEx_mode_support.xlsm" from Perforce.)
  29 */
  30#ifndef __DCE_CALCS_H__
  31#define __DCE_CALCS_H__
  32
  33#include "bw_fixed.h"
  34
  35struct pipe_ctx;
  36struct dc;
  37struct dc_state;
  38struct dce_bw_output;
  39
  40enum bw_calcs_version {
  41        BW_CALCS_VERSION_INVALID,
  42        BW_CALCS_VERSION_CARRIZO,
  43        BW_CALCS_VERSION_POLARIS10,
  44        BW_CALCS_VERSION_POLARIS11,
  45        BW_CALCS_VERSION_POLARIS12,
  46        BW_CALCS_VERSION_VEGAM,
  47        BW_CALCS_VERSION_STONEY,
  48        BW_CALCS_VERSION_VEGA10
  49};
  50
  51/*******************************************************************************
  52 * There are three types of input into Calculations:
  53 * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP
  54 * 2. board-level values - these are generally coming from VBIOS parser
  55 * 3. mode/configuration values - depending Mode, Scaling number of Displays etc.
  56 ******************************************************************************/
  57
  58enum bw_defines {
  59        //Common
  60        bw_def_no = 0,
  61        bw_def_none = 0,
  62        bw_def_yes = 1,
  63        bw_def_ok = 1,
  64        bw_def_high = 2,
  65        bw_def_mid = 1,
  66        bw_def_low = 0,
  67
  68        //Internal
  69        bw_defs_start = 255,
  70        bw_def_underlay422,
  71        bw_def_underlay420_luma,
  72        bw_def_underlay420_chroma,
  73        bw_def_underlay444,
  74        bw_def_graphics,
  75        bw_def_display_write_back420_luma,
  76        bw_def_display_write_back420_chroma,
  77        bw_def_portrait,
  78        bw_def_hsr_mtn_4,
  79        bw_def_hsr_mtn_h_taps,
  80        bw_def_ceiling__h_taps_div_4___meq_hsr,
  81        bw_def_invalid_linear_or_stereo_mode,
  82        bw_def_invalid_rotation_or_bpp_or_stereo,
  83        bw_def_vsr_mtn_v_taps,
  84        bw_def_vsr_mtn_4,
  85        bw_def_auto,
  86        bw_def_manual,
  87        bw_def_exceeded_allowed_maximum_sclk,
  88        bw_def_exceeded_allowed_page_close_open,
  89        bw_def_exceeded_allowed_outstanding_pte_req_queue_size,
  90        bw_def_exceeded_allowed_maximum_bw,
  91        bw_def_landscape,
  92
  93        //Panning and bezel
  94        bw_def_any_lines,
  95
  96        //Underlay mode
  97        bw_def_underlay_only,
  98        bw_def_blended,
  99        bw_def_blend,
 100
 101        //Stereo mode
 102        bw_def_mono,
 103        bw_def_side_by_side,
 104        bw_def_top_bottom,
 105
 106        //Underlay surface type
 107        bw_def_420,
 108        bw_def_422,
 109        bw_def_444,
 110
 111        //Tiling mode
 112        bw_def_linear,
 113        bw_def_tiled,
 114        bw_def_array_linear_general,
 115        bw_def_array_linear_aligned,
 116        bw_def_rotated_micro_tiling,
 117        bw_def_display_micro_tiling,
 118
 119        //Memory type
 120        bw_def_gddr5,
 121        bw_def_hbm,
 122
 123        //Voltage
 124        bw_def_high_no_nbp_state_change,
 125        bw_def_0_72,
 126        bw_def_0_8,
 127        bw_def_0_9,
 128
 129        bw_def_notok = -1,
 130        bw_def_na = -1
 131};
 132
 133struct bw_calcs_dceip {
 134        enum bw_calcs_version version;
 135        uint32_t percent_of_ideal_port_bw_received_after_urgent_latency;
 136        uint32_t max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation;
 137        uint32_t max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation;
 138        bool large_cursor;
 139        uint32_t cursor_max_outstanding_group_num;
 140        bool dmif_pipe_en_fbc_chunk_tracker;
 141        struct bw_fixed dmif_request_buffer_size;
 142        uint32_t lines_interleaved_into_lb;
 143        uint32_t low_power_tiling_mode;
 144        uint32_t chunk_width;
 145        uint32_t number_of_graphics_pipes;
 146        uint32_t number_of_underlay_pipes;
 147        bool display_write_back_supported;
 148        bool argb_compression_support;
 149        struct bw_fixed underlay_vscaler_efficiency6_bit_per_component;
 150        struct bw_fixed underlay_vscaler_efficiency8_bit_per_component;
 151        struct bw_fixed underlay_vscaler_efficiency10_bit_per_component;
 152        struct bw_fixed underlay_vscaler_efficiency12_bit_per_component;
 153        struct bw_fixed graphics_vscaler_efficiency6_bit_per_component;
 154        struct bw_fixed graphics_vscaler_efficiency8_bit_per_component;
 155        struct bw_fixed graphics_vscaler_efficiency10_bit_per_component;
 156        struct bw_fixed graphics_vscaler_efficiency12_bit_per_component;
 157        struct bw_fixed alpha_vscaler_efficiency;
 158        uint32_t max_dmif_buffer_allocated;
 159        uint32_t graphics_dmif_size;
 160        uint32_t underlay_luma_dmif_size;
 161        uint32_t underlay_chroma_dmif_size;
 162        bool pre_downscaler_enabled;
 163        bool underlay_downscale_prefetch_enabled;
 164        struct bw_fixed lb_write_pixels_per_dispclk;
 165        struct bw_fixed lb_size_per_component444;
 166        bool graphics_lb_nodownscaling_multi_line_prefetching;
 167        struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor;
 168        struct bw_fixed underlay420_luma_lb_size_per_component;
 169        struct bw_fixed underlay420_chroma_lb_size_per_component;
 170        struct bw_fixed underlay422_lb_size_per_component;
 171        struct bw_fixed cursor_chunk_width;
 172        struct bw_fixed cursor_dcp_buffer_lines;
 173        struct bw_fixed underlay_maximum_width_efficient_for_tiling;
 174        struct bw_fixed underlay_maximum_height_efficient_for_tiling;
 175        struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display;
 176        struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation;
 177        struct bw_fixed minimum_outstanding_pte_request_limit;
 178        struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw;
 179        bool limit_excessive_outstanding_dmif_requests;
 180        struct bw_fixed linear_mode_line_request_alternation_slice;
 181        uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode;
 182        uint32_t display_write_back420_luma_mcifwr_buffer_size;
 183        uint32_t display_write_back420_chroma_mcifwr_buffer_size;
 184        struct bw_fixed request_efficiency;
 185        struct bw_fixed dispclk_per_request;
 186        struct bw_fixed dispclk_ramping_factor;
 187        struct bw_fixed display_pipe_throughput_factor;
 188        uint32_t scatter_gather_pte_request_rows_in_tiling_mode;
 189        struct bw_fixed mcifwr_all_surfaces_burst_time;
 190};
 191
 192struct bw_calcs_vbios {
 193        enum bw_defines memory_type;
 194        uint32_t dram_channel_width_in_bits;
 195        uint32_t number_of_dram_channels;
 196        uint32_t number_of_dram_banks;
 197        struct bw_fixed low_yclk; /*m_hz*/
 198        struct bw_fixed mid_yclk; /*m_hz*/
 199        struct bw_fixed high_yclk; /*m_hz*/
 200        struct bw_fixed low_sclk; /*m_hz*/
 201        struct bw_fixed mid1_sclk; /*m_hz*/
 202        struct bw_fixed mid2_sclk; /*m_hz*/
 203        struct bw_fixed mid3_sclk; /*m_hz*/
 204        struct bw_fixed mid4_sclk; /*m_hz*/
 205        struct bw_fixed mid5_sclk; /*m_hz*/
 206        struct bw_fixed mid6_sclk; /*m_hz*/
 207        struct bw_fixed high_sclk; /*m_hz*/
 208        struct bw_fixed low_voltage_max_dispclk; /*m_hz*/
 209        struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/
 210        struct bw_fixed high_voltage_max_dispclk; /*m_hz*/
 211        struct bw_fixed low_voltage_max_phyclk;
 212        struct bw_fixed mid_voltage_max_phyclk;
 213        struct bw_fixed high_voltage_max_phyclk;
 214        struct bw_fixed data_return_bus_width;
 215        struct bw_fixed trc;
 216        struct bw_fixed dmifmc_urgent_latency;
 217        struct bw_fixed stutter_self_refresh_exit_latency;
 218        struct bw_fixed stutter_self_refresh_entry_latency;
 219        struct bw_fixed nbp_state_change_latency;
 220        struct bw_fixed mcifwrmc_urgent_latency;
 221        bool scatter_gather_enable;
 222        struct bw_fixed down_spread_percentage;
 223        uint32_t cursor_width;
 224        uint32_t average_compression_rate;
 225        uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel;
 226        struct bw_fixed blackout_duration;
 227        struct bw_fixed maximum_blackout_recovery_time;
 228};
 229
 230/*******************************************************************************
 231 * Temporary data structure(s).
 232 ******************************************************************************/
 233#define maximum_number_of_surfaces 12
 234/*Units : MHz, us */
 235
 236struct bw_calcs_data {
 237        /* data for all displays */
 238        bool display_synchronization_enabled;
 239        uint32_t number_of_displays;
 240        enum bw_defines underlay_surface_type;
 241        enum bw_defines panning_and_bezel_adjustment;
 242        enum bw_defines graphics_tiling_mode;
 243        uint32_t graphics_lb_bpc;
 244        uint32_t underlay_lb_bpc;
 245        enum bw_defines underlay_tiling_mode;
 246        enum bw_defines d0_underlay_mode;
 247        bool d1_display_write_back_dwb_enable;
 248        enum bw_defines d1_underlay_mode;
 249
 250        bool increase_voltage_to_support_mclk_switch;
 251        bool cpup_state_change_enable;
 252        bool cpuc_state_change_enable;
 253        bool nbp_state_change_enable;
 254        bool stutter_mode_enable;
 255        uint32_t y_clk_level;
 256        uint32_t sclk_level;
 257        uint32_t number_of_underlay_surfaces;
 258        uint32_t number_of_dram_wrchannels;
 259        uint32_t chunk_request_delay;
 260        uint32_t number_of_dram_channels;
 261        enum bw_defines underlay_micro_tile_mode;
 262        enum bw_defines graphics_micro_tile_mode;
 263        struct bw_fixed max_phyclk;
 264        struct bw_fixed dram_efficiency;
 265        struct bw_fixed src_width_after_surface_type;
 266        struct bw_fixed src_height_after_surface_type;
 267        struct bw_fixed hsr_after_surface_type;
 268        struct bw_fixed vsr_after_surface_type;
 269        struct bw_fixed src_width_after_rotation;
 270        struct bw_fixed src_height_after_rotation;
 271        struct bw_fixed hsr_after_rotation;
 272        struct bw_fixed vsr_after_rotation;
 273        struct bw_fixed source_height_pixels;
 274        struct bw_fixed hsr_after_stereo;
 275        struct bw_fixed vsr_after_stereo;
 276        struct bw_fixed source_width_in_lb;
 277        struct bw_fixed lb_line_pitch;
 278        struct bw_fixed underlay_maximum_source_efficient_for_tiling;
 279        struct bw_fixed num_lines_at_frame_start;
 280        struct bw_fixed min_dmif_size_in_time;
 281        struct bw_fixed min_mcifwr_size_in_time;
 282        struct bw_fixed total_requests_for_dmif_size;
 283        struct bw_fixed peak_pte_request_to_eviction_ratio_limiting;
 284        struct bw_fixed useful_pte_per_pte_request;
 285        struct bw_fixed scatter_gather_pte_request_rows;
 286        struct bw_fixed scatter_gather_row_height;
 287        struct bw_fixed scatter_gather_pte_requests_in_vblank;
 288        struct bw_fixed inefficient_linear_pitch_in_bytes;
 289        struct bw_fixed cursor_total_data;
 290        struct bw_fixed cursor_total_request_groups;
 291        struct bw_fixed scatter_gather_total_pte_requests;
 292        struct bw_fixed scatter_gather_total_pte_request_groups;
 293        struct bw_fixed tile_width_in_pixels;
 294        struct bw_fixed dmif_total_number_of_data_request_page_close_open;
 295        struct bw_fixed mcifwr_total_number_of_data_request_page_close_open;
 296        struct bw_fixed bytes_per_page_close_open;
 297        struct bw_fixed mcifwr_total_page_close_open_time;
 298        struct bw_fixed total_requests_for_adjusted_dmif_size;
 299        struct bw_fixed total_dmifmc_urgent_trips;
 300        struct bw_fixed total_dmifmc_urgent_latency;
 301        struct bw_fixed total_display_reads_required_data;
 302        struct bw_fixed total_display_reads_required_dram_access_data;
 303        struct bw_fixed total_display_writes_required_data;
 304        struct bw_fixed total_display_writes_required_dram_access_data;
 305        struct bw_fixed display_reads_required_data;
 306        struct bw_fixed display_reads_required_dram_access_data;
 307        struct bw_fixed dmif_total_page_close_open_time;
 308        struct bw_fixed min_cursor_memory_interface_buffer_size_in_time;
 309        struct bw_fixed min_read_buffer_size_in_time;
 310        struct bw_fixed display_reads_time_for_data_transfer;
 311        struct bw_fixed display_writes_time_for_data_transfer;
 312        struct bw_fixed dmif_required_dram_bandwidth;
 313        struct bw_fixed mcifwr_required_dram_bandwidth;
 314        struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open;
 315        struct bw_fixed required_mcifmcwr_urgent_latency;
 316        struct bw_fixed required_dram_bandwidth_gbyte_per_second;
 317        struct bw_fixed dram_bandwidth;
 318        struct bw_fixed dmif_required_sclk;
 319        struct bw_fixed mcifwr_required_sclk;
 320        struct bw_fixed required_sclk;
 321        struct bw_fixed downspread_factor;
 322        struct bw_fixed v_scaler_efficiency;
 323        struct bw_fixed scaler_limits_factor;
 324        struct bw_fixed display_pipe_pixel_throughput;
 325        struct bw_fixed total_dispclk_required_with_ramping;
 326        struct bw_fixed total_dispclk_required_without_ramping;
 327        struct bw_fixed total_read_request_bandwidth;
 328        struct bw_fixed total_write_request_bandwidth;
 329        struct bw_fixed dispclk_required_for_total_read_request_bandwidth;
 330        struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth;
 331        struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth;
 332        struct bw_fixed dispclk;
 333        struct bw_fixed blackout_recovery_time;
 334        struct bw_fixed min_pixels_per_data_fifo_entry;
 335        struct bw_fixed sclk_deep_sleep;
 336        struct bw_fixed chunk_request_time;
 337        struct bw_fixed cursor_request_time;
 338        struct bw_fixed line_source_pixels_transfer_time;
 339        struct bw_fixed dmifdram_access_efficiency;
 340        struct bw_fixed mcifwrdram_access_efficiency;
 341        struct bw_fixed total_average_bandwidth_no_compression;
 342        struct bw_fixed total_average_bandwidth;
 343        struct bw_fixed total_stutter_cycle_duration;
 344        struct bw_fixed stutter_burst_time;
 345        struct bw_fixed time_in_self_refresh;
 346        struct bw_fixed stutter_efficiency;
 347        struct bw_fixed worst_number_of_trips_to_memory;
 348        struct bw_fixed immediate_flip_time;
 349        struct bw_fixed latency_for_non_dmif_clients;
 350        struct bw_fixed latency_for_non_mcifwr_clients;
 351        struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk;
 352        struct bw_fixed nbp_state_dram_speed_change_margin;
 353        struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency;
 354        struct bw_fixed dram_speed_change_margin;
 355        struct bw_fixed min_vblank_dram_speed_change_margin;
 356        struct bw_fixed min_stutter_refresh_duration;
 357        uint32_t total_stutter_dmif_buffer_size;
 358        uint32_t total_bytes_requested;
 359        uint32_t min_stutter_dmif_buffer_size;
 360        uint32_t num_stutter_bursts;
 361        struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported;
 362        struct bw_fixed nbp_state_dram_speed_change_latency_supported;
 363        bool fbc_en[maximum_number_of_surfaces];
 364        bool lpt_en[maximum_number_of_surfaces];
 365        bool displays_match_flag[maximum_number_of_surfaces];
 366        bool use_alpha[maximum_number_of_surfaces];
 367        bool orthogonal_rotation[maximum_number_of_surfaces];
 368        bool enable[maximum_number_of_surfaces];
 369        bool access_one_channel_only[maximum_number_of_surfaces];
 370        bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces];
 371        bool interlace_mode[maximum_number_of_surfaces];
 372        bool display_pstate_change_enable[maximum_number_of_surfaces];
 373        bool line_buffer_prefetch[maximum_number_of_surfaces];
 374        uint32_t bytes_per_pixel[maximum_number_of_surfaces];
 375        uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces];
 376        uint32_t lb_bpc[maximum_number_of_surfaces];
 377        uint32_t output_bpphdmi[maximum_number_of_surfaces];
 378        uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces];
 379        uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces];
 380        uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces];
 381        enum bw_defines stereo_mode[maximum_number_of_surfaces];
 382        struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces];
 383        struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces];
 384        struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces];
 385        struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces];
 386        struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces];
 387        struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces];
 388        struct bw_fixed h_total[maximum_number_of_surfaces];
 389        struct bw_fixed v_total[maximum_number_of_surfaces];
 390        struct bw_fixed pixel_rate[maximum_number_of_surfaces];
 391        struct bw_fixed src_width[maximum_number_of_surfaces];
 392        struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces];
 393        struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces];
 394        struct bw_fixed src_height[maximum_number_of_surfaces];
 395        struct bw_fixed scale_ratio[maximum_number_of_surfaces];
 396        struct bw_fixed h_taps[maximum_number_of_surfaces];
 397        struct bw_fixed v_taps[maximum_number_of_surfaces];
 398        struct bw_fixed h_scale_ratio[maximum_number_of_surfaces];
 399        struct bw_fixed v_scale_ratio[maximum_number_of_surfaces];
 400        struct bw_fixed rotation_angle[maximum_number_of_surfaces];
 401        struct bw_fixed compression_rate[maximum_number_of_surfaces];
 402        struct bw_fixed hsr[maximum_number_of_surfaces];
 403        struct bw_fixed vsr[maximum_number_of_surfaces];
 404        struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces];
 405        struct bw_fixed source_width_pixels[maximum_number_of_surfaces];
 406        struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces];
 407        struct bw_fixed display_bandwidth[maximum_number_of_surfaces];
 408        struct bw_fixed request_bandwidth[maximum_number_of_surfaces];
 409        struct bw_fixed bytes_per_request[maximum_number_of_surfaces];
 410        struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces];
 411        struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces];
 412        struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces];
 413        struct bw_fixed lb_partitions[maximum_number_of_surfaces];
 414        struct bw_fixed lb_partitions_max[maximum_number_of_surfaces];
 415        struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces];
 416        struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces];
 417        struct bw_fixed data_buffer_size[maximum_number_of_surfaces];
 418        struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces];
 419        struct bw_fixed urgent_watermark[maximum_number_of_surfaces];
 420        struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces];
 421        struct bw_fixed v_filter_init[maximum_number_of_surfaces];
 422        struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces];
 423        struct bw_fixed average_bandwidth[maximum_number_of_surfaces];
 424        struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces];
 425        struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces];
 426        struct bw_fixed lb_size_per_component[maximum_number_of_surfaces];
 427        struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces];
 428        struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces];
 429        struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces];
 430        struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces];
 431        struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces];
 432        struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces];
 433        struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces];
 434        struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces];
 435        struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces];
 436        struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces];
 437        struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces];
 438        struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces];
 439        struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces];
 440        struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces];
 441        struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces];
 442        struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces];
 443        struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces];
 444        struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces];
 445        struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces];
 446        struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces];
 447        struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces];
 448        struct bw_fixed active_time[maximum_number_of_surfaces];
 449        struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces];
 450        struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces];
 451        struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces];
 452        uint32_t num_displays_with_margin[3][8];
 453        struct bw_fixed dmif_burst_time[3][8];
 454        struct bw_fixed mcifwr_burst_time[3][8];
 455        struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8];
 456        struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8];
 457        struct bw_fixed min_dram_speed_change_margin[3][8];
 458        struct bw_fixed dispclk_required_for_dram_speed_change[3][8];
 459        struct bw_fixed dispclk_required_for_dram_speed_change_pipe[3][8];
 460        struct bw_fixed blackout_duration_margin[3][8];
 461        struct bw_fixed dispclk_required_for_blackout_duration[3][8];
 462        struct bw_fixed dispclk_required_for_blackout_recovery[3][8];
 463        struct bw_fixed dmif_required_sclk_for_urgent_latency[6];
 464};
 465
 466/**
 467 * Initialize structures with data which will NOT change at runtime.
 468 */
 469void bw_calcs_init(
 470        struct bw_calcs_dceip *bw_dceip,
 471        struct bw_calcs_vbios *bw_vbios,
 472        struct hw_asic_id asic_id);
 473
 474/**
 475 * Return:
 476 *      true -  Display(s) configuration supported.
 477 *              In this case 'calcs_output' contains data for HW programming
 478 *      false - Display(s) configuration not supported (not enough bandwidth).
 479 */
 480bool bw_calcs(
 481        struct dc_context *ctx,
 482        const struct bw_calcs_dceip *dceip,
 483        const struct bw_calcs_vbios *vbios,
 484        const struct pipe_ctx *pipe,
 485        int pipe_count,
 486        struct dce_bw_output *calcs_output);
 487
 488#endif /* __BANDWIDTH_CALCS_H__ */
 489
 490