LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DAL_CLK_MGR_INTERNAL_H__
  27#define __DAL_CLK_MGR_INTERNAL_H__
  28
  29#include "clk_mgr.h"
  30#include "dc.h"
  31
  32/*
  33 * only thing needed from here is MEMORY_TYPE_MULTIPLIER_CZ, which is also
  34 * used in resource, perhaps this should be defined somewhere more common.
  35 */
  36#include "resource.h"
  37
  38
  39/* Starting DID for each range */
  40enum dentist_base_divider_id {
  41        DENTIST_BASE_DID_1 = 0x08,
  42        DENTIST_BASE_DID_2 = 0x40,
  43        DENTIST_BASE_DID_3 = 0x60,
  44        DENTIST_BASE_DID_4 = 0x7e,
  45        DENTIST_MAX_DID = 0x7f
  46};
  47
  48/* Starting point and step size for each divider range.*/
  49enum dentist_divider_range {
  50        DENTIST_DIVIDER_RANGE_1_START = 8,   /* 2.00  */
  51        DENTIST_DIVIDER_RANGE_1_STEP  = 1,   /* 0.25  */
  52        DENTIST_DIVIDER_RANGE_2_START = 64,  /* 16.00 */
  53        DENTIST_DIVIDER_RANGE_2_STEP  = 2,   /* 0.50  */
  54        DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
  55        DENTIST_DIVIDER_RANGE_3_STEP  = 4,   /* 1.00  */
  56        DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
  57        DENTIST_DIVIDER_RANGE_4_STEP  = 264, /* 66.00 */
  58        DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
  59};
  60
  61/*
  62 ***************************************************************************************
  63 ****************** Clock Manager Private Macros and Defines ***************************
  64 ***************************************************************************************
  65 */
  66
  67/* Macros */
  68
  69#define TO_CLK_MGR_INTERNAL(clk_mgr)\
  70        container_of(clk_mgr, struct clk_mgr_internal, base)
  71
  72#define CTX \
  73        clk_mgr->base.ctx
  74#define DC_LOGGER \
  75        clk_mgr->ctx->logger
  76
  77
  78
  79
  80#define CLK_BASE(inst) \
  81        CLK_BASE_INNER(inst)
  82
  83#define CLK_SRI(reg_name, block, inst)\
  84        .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
  85                                        mm ## block ## _ ## inst ## _ ## reg_name
  86
  87#define CLK_COMMON_REG_LIST_DCE_BASE() \
  88        .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \
  89        .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL
  90
  91#define CLK_COMMON_REG_LIST_DCN_BASE() \
  92        SR(DENTIST_DISPCLK_CNTL)
  93
  94#define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \
  95        .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \
  96        .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \
  97        .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67
  98
  99#define CLK_REG_LIST_NV10() \
 100        SR(DENTIST_DISPCLK_CNTL), \
 101        CLK_SRI(CLK3_CLK_PLL_REQ, CLK3, 0), \
 102        CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0)
 103
 104#define CLK_SF(reg_name, field_name, post_fix)\
 105        .field_name = reg_name ## __ ## field_name ## post_fix
 106
 107#define CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
 108        CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \
 109        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh)
 110
 111#define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
 112        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\
 113        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
 114
 115#define CLK_MASK_SH_LIST_RV1(mask_sh) \
 116        CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
 117        CLK_SF(MP1_SMN_C2PMSG_67, CONTENT, mask_sh),\
 118        CLK_SF(MP1_SMN_C2PMSG_83, CONTENT, mask_sh),\
 119        CLK_SF(MP1_SMN_C2PMSG_91, CONTENT, mask_sh),
 120
 121#define CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh) \
 122        CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
 123        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, mask_sh),\
 124        CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_CHG_DONE, mask_sh)
 125
 126#define CLK_MASK_SH_LIST_NV10(mask_sh) \
 127        CLK_COMMON_MASK_SH_LIST_DCN20_BASE(mask_sh),\
 128        CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_int, mask_sh),\
 129        CLK_SF(CLK3_0_CLK3_CLK_PLL_REQ, FbMult_frac, mask_sh)
 130
 131#define CLK_REG_FIELD_LIST(type) \
 132        type DPREFCLK_SRC_SEL; \
 133        type DENTIST_DPREFCLK_WDIVIDER; \
 134        type DENTIST_DISPCLK_WDIVIDER; \
 135        type DENTIST_DISPCLK_CHG_DONE;
 136
 137/*
 138 ***************************************************************************************
 139 ****************** Clock Manager Private Structures ***********************************
 140 ***************************************************************************************
 141 */
 142#define CLK20_REG_FIELD_LIST(type) \
 143        type DENTIST_DPPCLK_WDIVIDER; \
 144        type DENTIST_DPPCLK_CHG_DONE; \
 145        type FbMult_int; \
 146        type FbMult_frac;
 147
 148#define VBIOS_SMU_REG_FIELD_LIST(type) \
 149        type CONTENT;
 150
 151struct clk_mgr_shift {
 152        CLK_REG_FIELD_LIST(uint8_t)
 153        CLK20_REG_FIELD_LIST(uint8_t)
 154        VBIOS_SMU_REG_FIELD_LIST(uint32_t)
 155};
 156
 157struct clk_mgr_mask {
 158        CLK_REG_FIELD_LIST(uint32_t)
 159        CLK20_REG_FIELD_LIST(uint32_t)
 160        VBIOS_SMU_REG_FIELD_LIST(uint32_t)
 161};
 162
 163struct clk_mgr_registers {
 164        uint32_t DPREFCLK_CNTL;
 165        uint32_t DENTIST_DISPCLK_CNTL;
 166
 167        uint32_t CLK3_CLK2_DFS_CNTL;
 168        uint32_t CLK3_CLK_PLL_REQ;
 169
 170        uint32_t MP1_SMN_C2PMSG_67;
 171        uint32_t MP1_SMN_C2PMSG_83;
 172        uint32_t MP1_SMN_C2PMSG_91;
 173};
 174
 175enum clock_type {
 176        clock_type_dispclk = 1,
 177        clock_type_dcfclk,
 178        clock_type_socclk,
 179        clock_type_pixelclk,
 180        clock_type_phyclk,
 181        clock_type_dppclk,
 182        clock_type_fclk,
 183        clock_type_dcfdsclk,
 184        clock_type_dscclk,
 185        clock_type_uclk,
 186        clock_type_dramclk,
 187};
 188
 189
 190struct state_dependent_clocks {
 191        int display_clk_khz;
 192        int pixel_clk_khz;
 193};
 194
 195struct clk_mgr_internal {
 196        struct clk_mgr base;
 197        int smu_ver;
 198        struct pp_smu_funcs *pp_smu;
 199        struct clk_mgr_internal_funcs *funcs;
 200
 201        struct dccg *dccg;
 202
 203        /*
 204         * For backwards compatbility with previous implementation
 205         * TODO: remove these after everything transitions to new pattern
 206         * Rationale is that clk registers change a lot across DCE versions
 207         * and a shared data structure doesn't really make sense.
 208         */
 209        const struct clk_mgr_registers *regs;
 210        const struct clk_mgr_shift *clk_mgr_shift;
 211        const struct clk_mgr_mask *clk_mgr_mask;
 212
 213        struct state_dependent_clocks max_clks_by_state[DM_PP_CLOCKS_MAX_STATES];
 214
 215        /*TODO: figure out which of the below fields should be here vs in asic specific portion */
 216        /* Cache the status of DFS-bypass feature*/
 217        bool dfs_bypass_enabled;
 218        /* True if the DFS-bypass feature is enabled and active. */
 219        bool dfs_bypass_active;
 220
 221        uint32_t dfs_ref_freq_khz;
 222        /*
 223         * Cache the display clock returned by VBIOS if DFS-bypass is enabled.
 224         * This is basically "Crystal Frequency In KHz" (XTALIN) frequency
 225         */
 226        int dfs_bypass_disp_clk;
 227
 228        /**
 229         * @ss_on_dprefclk:
 230         *
 231         * True if spread spectrum is enabled on the DP ref clock.
 232         */
 233        bool ss_on_dprefclk;
 234
 235        /**
 236         * @xgmi_enabled:
 237         *
 238         * True if xGMI is enabled. On VG20, both audio and display clocks need
 239         * to be adjusted with the WAFL link's SS info if xGMI is enabled.
 240         */
 241        bool xgmi_enabled;
 242
 243        /**
 244         * @dprefclk_ss_percentage:
 245         *
 246         * DPREFCLK SS percentage (if down-spread enabled).
 247         *
 248         * Note that if XGMI is enabled, the SS info (percentage and divider)
 249         * from the WAFL link is used instead. This is decided during
 250         * dce_clk_mgr initialization.
 251         */
 252        int dprefclk_ss_percentage;
 253
 254        /**
 255         * @dprefclk_ss_divider:
 256         *
 257         * DPREFCLK SS percentage Divider (100 or 1000).
 258         */
 259        int dprefclk_ss_divider;
 260
 261        enum dm_pp_clocks_state max_clks_state;
 262        enum dm_pp_clocks_state cur_min_clks_state;
 263};
 264
 265struct clk_mgr_internal_funcs {
 266        int (*set_dispclk)(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
 267        int (*set_dprefclk)(struct clk_mgr_internal *clk_mgr);
 268};
 269
 270
 271/*
 272 ***************************************************************************************
 273 ****************** Clock Manager Level Helper functions *******************************
 274 ***************************************************************************************
 275 */
 276
 277
 278static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk)
 279{
 280        return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk);
 281}
 282
 283static inline bool should_update_pstate_support(bool safe_to_lower, bool calc_support, bool cur_support)
 284{
 285        if (cur_support != calc_support) {
 286                if (calc_support == true && safe_to_lower)
 287                        return true;
 288                else if (calc_support == false && !safe_to_lower)
 289                        return true;
 290        }
 291
 292        return false;
 293}
 294
 295int clk_mgr_helper_get_active_display_cnt(
 296                struct dc *dc,
 297                struct dc_state *context);
 298
 299
 300
 301#endif //__DAL_CLK_MGR_INTERNAL_H__
 302