LXR linux/drivers/gpu/drm/amd/powerplay/smumgr/vega10

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/pci.h>
  25
  26#include "smumgr.h"
  27#include "vega10_inc.h"
  28#include "soc15_common.h"
  29#include "vega10_smumgr.h"
  30#include "vega10_hwmgr.h"
  31#include "vega10_ppsmc.h"
  32#include "smu9_driver_if.h"
  33#include "smu9_smumgr.h"
  34#include "ppatomctrl.h"
  35#include "pp_debug.h"
  36
  37
  38static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
  39                uint8_t *table, int16_t table_id)
  40{
  41        struct vega10_smumgr *priv = hwmgr->smu_backend;
  42        struct amdgpu_device *adev = hwmgr->adev;
  43
  44        PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
  45                        "Invalid SMU Table ID!", return -EINVAL);
  46        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
  47                        "Invalid SMU Table version!", return -EINVAL);
  48        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
  49                        "Invalid SMU Table Length!", return -EINVAL);
  50        smu9_send_msg_to_smc_with_parameter(hwmgr,
  51                        PPSMC_MSG_SetDriverDramAddrHigh,
  52                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
  53        smu9_send_msg_to_smc_with_parameter(hwmgr,
  54                        PPSMC_MSG_SetDriverDramAddrLow,
  55                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
  56        smu9_send_msg_to_smc_with_parameter(hwmgr,
  57                        PPSMC_MSG_TransferTableSmu2Dram,
  58                        priv->smu_tables.entry[table_id].table_id);
  59
  60        /* flush hdp cache */
  61        amdgpu_asic_flush_hdp(adev, NULL);
  62
  63        memcpy(table, priv->smu_tables.entry[table_id].table,
  64                        priv->smu_tables.entry[table_id].size);
  65
  66        return 0;
  67}
  68
  69static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
  70                uint8_t *table, int16_t table_id)
  71{
  72        struct vega10_smumgr *priv = hwmgr->smu_backend;
  73        struct amdgpu_device *adev = hwmgr->adev;
  74
  75        /* under sriov, vbios or hypervisor driver
  76         * has already copy table to smc so here only skip it
  77         */
  78        if (!hwmgr->not_vf)
  79                return 0;
  80
  81        PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
  82                        "Invalid SMU Table ID!", return -EINVAL);
  83        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
  84                        "Invalid SMU Table version!", return -EINVAL);
  85        PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
  86                        "Invalid SMU Table Length!", return -EINVAL);
  87
  88        memcpy(priv->smu_tables.entry[table_id].table, table,
  89                        priv->smu_tables.entry[table_id].size);
  90
  91        amdgpu_asic_flush_hdp(adev, NULL);
  92
  93        smu9_send_msg_to_smc_with_parameter(hwmgr,
  94                        PPSMC_MSG_SetDriverDramAddrHigh,
  95                        upper_32_bits(priv->smu_tables.entry[table_id].mc_addr));
  96        smu9_send_msg_to_smc_with_parameter(hwmgr,
  97                        PPSMC_MSG_SetDriverDramAddrLow,
  98                        lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));
  99        smu9_send_msg_to_smc_with_parameter(hwmgr,
 100                        PPSMC_MSG_TransferTableDram2Smu,
 101                        priv->smu_tables.entry[table_id].table_id);
 102
 103        return 0;
 104}
 105
 106int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
 107                               bool enable, uint32_t feature_mask)
 108{
 109        int msg = enable ? PPSMC_MSG_EnableSmuFeatures :
 110                        PPSMC_MSG_DisableSmuFeatures;
 111
 112        /* VF has no permission to change smu feature due
 113         * to security concern even under pp one vf mode
 114         * it still can't do it. For vega10, the smu in
 115         * vbios will enable the appropriate features.
 116         * */
 117        if (!hwmgr->not_vf)
 118                return 0;
 119
 120        return smum_send_msg_to_smc_with_parameter(hwmgr,
 121                        msg, feature_mask);
 122}
 123
 124int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
 125                            uint64_t *features_enabled)
 126{
 127        if (features_enabled == NULL)
 128                return -EINVAL;
 129
 130        smu9_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures);
 131        *features_enabled = smu9_get_argument(hwmgr);
 132
 133        return 0;
 134}
 135
 136static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
 137{
 138        uint64_t features_enabled = 0;
 139
 140        vega10_get_enabled_smc_features(hwmgr, &features_enabled);
 141
 142        if (features_enabled & SMC_DPM_FEATURES)
 143                return true;
 144        else
 145                return false;
 146}
 147
 148static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
 149{
 150        struct vega10_smumgr *priv = hwmgr->smu_backend;
 151
 152        if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) {
 153                smu9_send_msg_to_smc_with_parameter(hwmgr,
 154                                PPSMC_MSG_SetToolsDramAddrHigh,
 155                                upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
 156                smu9_send_msg_to_smc_with_parameter(hwmgr,
 157                                PPSMC_MSG_SetToolsDramAddrLow,
 158                                lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));
 159        }
 160        return 0;
 161}
 162
 163static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
 164{
 165        uint32_t smc_driver_if_version;
 166        struct amdgpu_device *adev = hwmgr->adev;
 167        uint32_t dev_id;
 168        uint32_t rev_id;
 169
 170        PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr,
 171                        PPSMC_MSG_GetDriverIfVersion),
 172                        "Attempt to get SMC IF Version Number Failed!",
 173                        return -EINVAL);
 174        smc_driver_if_version = smu9_get_argument(hwmgr);
 175
 176        dev_id = adev->pdev->device;
 177        rev_id = adev->pdev->revision;
 178
 179        if (!((dev_id == 0x687f) &&
 180                ((rev_id == 0xc0) ||
 181                (rev_id == 0xc1) ||
 182                (rev_id == 0xc3)))) {
 183                if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
 184                        pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
 185                               smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
 186                        return -EINVAL;
 187                }
 188        }
 189
 190        return 0;
 191}
 192
 193static int vega10_smu_init(struct pp_hwmgr *hwmgr)
 194{
 195        struct vega10_smumgr *priv;
 196        unsigned long tools_size;
 197        int ret;
 198        struct cgs_firmware_info info = {0};
 199
 200        ret = cgs_get_firmware_info(hwmgr->device,
 201                                    CGS_UCODE_ID_SMU,
 202                                    &info);
 203        if (ret || !info.kptr)
 204                return -EINVAL;
 205
 206        priv = kzalloc(sizeof(struct vega10_smumgr), GFP_KERNEL);
 207
 208        if (!priv)
 209                return -ENOMEM;
 210
 211        hwmgr->smu_backend = priv;
 212
 213        /* allocate space for pptable */
 214        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 215                        sizeof(PPTable_t),
 216                        PAGE_SIZE,
 217                        AMDGPU_GEM_DOMAIN_VRAM,
 218                        &priv->smu_tables.entry[PPTABLE].handle,
 219                        &priv->smu_tables.entry[PPTABLE].mc_addr,
 220                        &priv->smu_tables.entry[PPTABLE].table);
 221        if (ret)
 222                goto free_backend;
 223
 224        priv->smu_tables.entry[PPTABLE].version = 0x01;
 225        priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
 226        priv->smu_tables.entry[PPTABLE].table_id = TABLE_PPTABLE;
 227
 228        /* allocate space for watermarks table */
 229        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 230                        sizeof(Watermarks_t),
 231                        PAGE_SIZE,
 232                        AMDGPU_GEM_DOMAIN_VRAM,
 233                        &priv->smu_tables.entry[WMTABLE].handle,
 234                        &priv->smu_tables.entry[WMTABLE].mc_addr,
 235                        &priv->smu_tables.entry[WMTABLE].table);
 236
 237        if (ret)
 238                goto err0;
 239
 240        priv->smu_tables.entry[WMTABLE].version = 0x01;
 241        priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
 242        priv->smu_tables.entry[WMTABLE].table_id = TABLE_WATERMARKS;
 243
 244        /* allocate space for AVFS table */
 245        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 246                        sizeof(AvfsTable_t),
 247                        PAGE_SIZE,
 248                        AMDGPU_GEM_DOMAIN_VRAM,
 249                        &priv->smu_tables.entry[AVFSTABLE].handle,
 250                        &priv->smu_tables.entry[AVFSTABLE].mc_addr,
 251                        &priv->smu_tables.entry[AVFSTABLE].table);
 252
 253        if (ret)
 254                goto err1;
 255
 256        priv->smu_tables.entry[AVFSTABLE].version = 0x01;
 257        priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t);
 258        priv->smu_tables.entry[AVFSTABLE].table_id = TABLE_AVFS;
 259
 260        tools_size = 0x19000;
 261        if (tools_size) {
 262                ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 263                                tools_size,
 264                                PAGE_SIZE,
 265                                AMDGPU_GEM_DOMAIN_VRAM,
 266                                &priv->smu_tables.entry[TOOLSTABLE].handle,
 267                                &priv->smu_tables.entry[TOOLSTABLE].mc_addr,
 268                                &priv->smu_tables.entry[TOOLSTABLE].table);
 269                if (ret)
 270                        goto err2;
 271                priv->smu_tables.entry[TOOLSTABLE].version = 0x01;
 272                priv->smu_tables.entry[TOOLSTABLE].size = tools_size;
 273                priv->smu_tables.entry[TOOLSTABLE].table_id = TABLE_PMSTATUSLOG;
 274        }
 275
 276        /* allocate space for AVFS Fuse table */
 277        ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 278                        sizeof(AvfsFuseOverride_t),
 279                        PAGE_SIZE,
 280                        AMDGPU_GEM_DOMAIN_VRAM,
 281                        &priv->smu_tables.entry[AVFSFUSETABLE].handle,
 282                        &priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,
 283                        &priv->smu_tables.entry[AVFSFUSETABLE].table);
 284        if (ret)
 285                goto err3;
 286
 287        priv->smu_tables.entry[AVFSFUSETABLE].version = 0x01;
 288        priv->smu_tables.entry[AVFSFUSETABLE].size = sizeof(AvfsFuseOverride_t);
 289        priv->smu_tables.entry[AVFSFUSETABLE].table_id = TABLE_AVFS_FUSE_OVERRIDE;
 290
 291
 292        return 0;
 293
 294err3:
 295        if (priv->smu_tables.entry[TOOLSTABLE].table)
 296                amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle,
 297                                &priv->smu_tables.entry[TOOLSTABLE].mc_addr,
 298                                &priv->smu_tables.entry[TOOLSTABLE].table);
 299err2:
 300        amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle,
 301                                &priv->smu_tables.entry[AVFSTABLE].mc_addr,
 302                                &priv->smu_tables.entry[AVFSTABLE].table);
 303err1:
 304        amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
 305                                &priv->smu_tables.entry[WMTABLE].mc_addr,
 306                                &priv->smu_tables.entry[WMTABLE].table);
 307err0:
 308        amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,
 309                        &priv->smu_tables.entry[PPTABLE].mc_addr,
 310                        &priv->smu_tables.entry[PPTABLE].table);
 311free_backend:
 312        kfree(hwmgr->smu_backend);
 313
 314        return -EINVAL;
 315}
 316
 317static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
 318{
 319        struct vega10_smumgr *priv = hwmgr->smu_backend;
 320
 321        if (priv) {
 322                amdgpu_bo_free_kernel(&priv->smu_tables.entry[PPTABLE].handle,
 323                                &priv->smu_tables.entry[PPTABLE].mc_addr,
 324                                &priv->smu_tables.entry[PPTABLE].table);
 325                amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
 326                                        &priv->smu_tables.entry[WMTABLE].mc_addr,
 327                                        &priv->smu_tables.entry[WMTABLE].table);
 328                amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSTABLE].handle,
 329                                        &priv->smu_tables.entry[AVFSTABLE].mc_addr,
 330                                        &priv->smu_tables.entry[AVFSTABLE].table);
 331                if (priv->smu_tables.entry[TOOLSTABLE].table)
 332                        amdgpu_bo_free_kernel(&priv->smu_tables.entry[TOOLSTABLE].handle,
 333                                        &priv->smu_tables.entry[TOOLSTABLE].mc_addr,
 334                                        &priv->smu_tables.entry[TOOLSTABLE].table);
 335                amdgpu_bo_free_kernel(&priv->smu_tables.entry[AVFSFUSETABLE].handle,
 336                                        &priv->smu_tables.entry[AVFSFUSETABLE].mc_addr,
 337                                        &priv->smu_tables.entry[AVFSFUSETABLE].table);
 338                kfree(hwmgr->smu_backend);
 339                hwmgr->smu_backend = NULL;
 340        }
 341        return 0;
 342}
 343
 344static int vega10_start_smu(struct pp_hwmgr *hwmgr)
 345{
 346        if (!smu9_is_smc_ram_running(hwmgr))
 347                return -EINVAL;
 348
 349        PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
 350                        "Failed to verify SMC interface!",
 351                        return -EINVAL);
 352
 353        vega10_set_tools_address(hwmgr);
 354
 355        return 0;
 356}
 357
 358static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
 359                                    uint16_t table_id, bool rw)
 360{
 361        int ret;
 362
 363        if (rw)
 364                ret = vega10_copy_table_from_smc(hwmgr, table, table_id);
 365        else
 366                ret = vega10_copy_table_to_smc(hwmgr, table, table_id);
 367
 368        return ret;
 369}
 370
 371const struct pp_smumgr_func vega10_smu_funcs = {
 372        .name = "vega10_smu",
 373        .smu_init = &vega10_smu_init,
 374        .smu_fini = &vega10_smu_fini,
 375        .start_smu = &vega10_start_smu,
 376        .request_smu_load_specific_fw = NULL,
 377        .send_msg_to_smc = &smu9_send_msg_to_smc,
 378        .send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter,
 379        .download_pptable_settings = NULL,
 380        .upload_pptable_settings = NULL,
 381        .is_dpm_running = vega10_is_dpm_running,
 382        .get_argument = smu9_get_argument,
 383        .smc_table_manager = vega10_smc_table_manager,
 384};
 385