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9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/err.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/phy/phy.h>
19#include <linux/platform_device.h>
20
21#include <drm/bridge/analogix_dp.h>
22#include <drm/drm_atomic.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_bridge.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_device.h>
27#include <drm/drm_panel.h>
28#include <drm/drm_print.h>
29#include <drm/drm_probe_helper.h>
30
31#include "analogix_dp_core.h"
32#include "analogix_dp_reg.h"
33
34#define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
35
36static const bool verify_fast_training;
37
38struct bridge_init {
39 struct i2c_client *client;
40 struct device_node *node;
41};
42
43static int analogix_dp_init_dp(struct analogix_dp_device *dp)
44{
45 int ret;
46
47 analogix_dp_reset(dp);
48
49 analogix_dp_swreset(dp);
50
51 analogix_dp_init_analog_param(dp);
52 analogix_dp_init_interrupt(dp);
53
54
55 analogix_dp_enable_sw_function(dp);
56
57 analogix_dp_config_interrupt(dp);
58 ret = analogix_dp_init_analog_func(dp);
59 if (ret)
60 return ret;
61
62 analogix_dp_init_hpd(dp);
63 analogix_dp_init_aux(dp);
64 return 0;
65}
66
67static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
68{
69 int timeout_loop = 0;
70
71 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
72 if (analogix_dp_get_plug_in_status(dp) == 0)
73 return 0;
74
75 timeout_loop++;
76 usleep_range(1000, 1100);
77 }
78
79
80
81
82
83
84 if (!dp->force_hpd)
85 return -ETIMEDOUT;
86
87
88
89
90
91
92 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
93
94 analogix_dp_force_hpd(dp);
95
96 if (analogix_dp_get_plug_in_status(dp) != 0) {
97 dev_err(dp->dev, "failed to get hpd plug in status\n");
98 return -EINVAL;
99 }
100
101 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
102
103 return 0;
104}
105
106static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
107{
108 unsigned char psr_version;
109 int ret;
110
111 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
112 if (ret != 1) {
113 dev_err(dp->dev, "failed to get PSR version, disable it\n");
114 return false;
115 }
116
117 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
118 return psr_version & DP_PSR_IS_SUPPORTED;
119}
120
121static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
122{
123 unsigned char psr_en;
124 int ret;
125
126
127 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
128 if (ret != 1) {
129 dev_err(dp->dev, "failed to get psr config\n");
130 goto end;
131 }
132
133 psr_en &= ~DP_PSR_ENABLE;
134 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
135 if (ret != 1) {
136 dev_err(dp->dev, "failed to disable panel psr\n");
137 goto end;
138 }
139
140
141 psr_en = DP_PSR_CRC_VERIFICATION;
142 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
143 if (ret != 1) {
144 dev_err(dp->dev, "failed to set panel psr\n");
145 goto end;
146 }
147
148
149 psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
150 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
151 if (ret != 1) {
152 dev_err(dp->dev, "failed to set panel psr\n");
153 goto end;
154 }
155
156 analogix_dp_enable_psr_crc(dp);
157
158 dp->psr_supported = true;
159
160 return 0;
161end:
162 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
163
164 return ret;
165}
166
167static int
168analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
169 bool enable)
170{
171 u8 data;
172 int ret;
173
174 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
175 if (ret != 1)
176 return ret;
177
178 if (enable)
179 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
180 DP_LANE_COUNT_ENHANCED_FRAME_EN |
181 DPCD_LANE_COUNT_SET(data));
182 else
183 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
184 DPCD_LANE_COUNT_SET(data));
185
186 return ret < 0 ? ret : 0;
187}
188
189static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
190 u8 *enhanced_mode_support)
191{
192 u8 data;
193 int ret;
194
195 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
196 if (ret != 1) {
197 *enhanced_mode_support = 0;
198 return ret;
199 }
200
201 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
202
203 return 0;
204}
205
206static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
207{
208 u8 data;
209 int ret;
210
211 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
212 if (ret < 0)
213 return ret;
214
215 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
216 if (ret < 0)
217 return ret;
218
219 analogix_dp_enable_enhanced_mode(dp, data);
220
221 return 0;
222}
223
224static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
225{
226 int ret;
227
228 analogix_dp_set_training_pattern(dp, DP_NONE);
229
230 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
231 DP_TRAINING_PATTERN_DISABLE);
232
233 return ret < 0 ? ret : 0;
234}
235
236static void
237analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
238 int pre_emphasis, int lane)
239{
240 switch (lane) {
241 case 0:
242 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
243 break;
244 case 1:
245 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
246 break;
247
248 case 2:
249 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
250 break;
251
252 case 3:
253 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
254 break;
255 }
256}
257
258static int analogix_dp_link_start(struct analogix_dp_device *dp)
259{
260 u8 buf[4];
261 int lane, lane_count, pll_tries, retval;
262
263 lane_count = dp->link_train.lane_count;
264
265 dp->link_train.lt_state = CLOCK_RECOVERY;
266 dp->link_train.eq_loop = 0;
267
268 for (lane = 0; lane < lane_count; lane++)
269 dp->link_train.cr_loop[lane] = 0;
270
271
272 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
273 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
274
275
276 buf[0] = dp->link_train.link_rate;
277 buf[1] = dp->link_train.lane_count;
278 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
279 if (retval < 0)
280 return retval;
281
282 retval = analogix_dp_set_enhanced_mode(dp);
283 if (retval < 0) {
284 dev_err(dp->dev, "failed to set enhance mode\n");
285 return retval;
286 }
287
288
289 for (lane = 0; lane < lane_count; lane++)
290 analogix_dp_set_lane_lane_pre_emphasis(dp,
291 PRE_EMPHASIS_LEVEL_0, lane);
292
293
294 pll_tries = 0;
295 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
296 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
297 dev_err(dp->dev, "Wait for PLL lock timed out\n");
298 return -ETIMEDOUT;
299 }
300
301 pll_tries++;
302 usleep_range(90, 120);
303 }
304
305
306 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
307
308
309 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
310 DP_LINK_SCRAMBLING_DISABLE |
311 DP_TRAINING_PATTERN_1);
312 if (retval < 0)
313 return retval;
314
315 for (lane = 0; lane < lane_count; lane++)
316 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
317 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
318
319 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
320 lane_count);
321 if (retval < 0)
322 return retval;
323
324 return 0;
325}
326
327static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
328{
329 int shift = (lane & 1) * 4;
330 u8 link_value = link_status[lane >> 1];
331
332 return (link_value >> shift) & 0xf;
333}
334
335static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
336{
337 int lane;
338 u8 lane_status;
339
340 for (lane = 0; lane < lane_count; lane++) {
341 lane_status = analogix_dp_get_lane_status(link_status, lane);
342 if ((lane_status & DP_LANE_CR_DONE) == 0)
343 return -EINVAL;
344 }
345 return 0;
346}
347
348static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
349 int lane_count)
350{
351 int lane;
352 u8 lane_status;
353
354 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
355 return -EINVAL;
356
357 for (lane = 0; lane < lane_count; lane++) {
358 lane_status = analogix_dp_get_lane_status(link_status, lane);
359 lane_status &= DP_CHANNEL_EQ_BITS;
360 if (lane_status != DP_CHANNEL_EQ_BITS)
361 return -EINVAL;
362 }
363
364 return 0;
365}
366
367static unsigned char
368analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
369{
370 int shift = (lane & 1) * 4;
371 u8 link_value = adjust_request[lane >> 1];
372
373 return (link_value >> shift) & 0x3;
374}
375
376static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
377 u8 adjust_request[2],
378 int lane)
379{
380 int shift = (lane & 1) * 4;
381 u8 link_value = adjust_request[lane >> 1];
382
383 return ((link_value >> shift) & 0xc) >> 2;
384}
385
386static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
387 u8 training_lane_set, int lane)
388{
389 switch (lane) {
390 case 0:
391 analogix_dp_set_lane0_link_training(dp, training_lane_set);
392 break;
393 case 1:
394 analogix_dp_set_lane1_link_training(dp, training_lane_set);
395 break;
396
397 case 2:
398 analogix_dp_set_lane2_link_training(dp, training_lane_set);
399 break;
400
401 case 3:
402 analogix_dp_set_lane3_link_training(dp, training_lane_set);
403 break;
404 }
405}
406
407static unsigned int
408analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
409 int lane)
410{
411 u32 reg;
412
413 switch (lane) {
414 case 0:
415 reg = analogix_dp_get_lane0_link_training(dp);
416 break;
417 case 1:
418 reg = analogix_dp_get_lane1_link_training(dp);
419 break;
420 case 2:
421 reg = analogix_dp_get_lane2_link_training(dp);
422 break;
423 case 3:
424 reg = analogix_dp_get_lane3_link_training(dp);
425 break;
426 default:
427 WARN_ON(1);
428 return 0;
429 }
430
431 return reg;
432}
433
434static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
435{
436 analogix_dp_training_pattern_dis(dp);
437 analogix_dp_set_enhanced_mode(dp);
438
439 dp->link_train.lt_state = FAILED;
440}
441
442static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
443 u8 adjust_request[2])
444{
445 int lane, lane_count;
446 u8 voltage_swing, pre_emphasis, training_lane;
447
448 lane_count = dp->link_train.lane_count;
449 for (lane = 0; lane < lane_count; lane++) {
450 voltage_swing = analogix_dp_get_adjust_request_voltage(
451 adjust_request, lane);
452 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
453 adjust_request, lane);
454 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
455 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
456
457 if (voltage_swing == VOLTAGE_LEVEL_3)
458 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
459 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
460 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
461
462 dp->link_train.training_lane[lane] = training_lane;
463 }
464}
465
466static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
467{
468 int lane, lane_count, retval;
469 u8 voltage_swing, pre_emphasis, training_lane;
470 u8 link_status[2], adjust_request[2];
471
472 usleep_range(100, 101);
473
474 lane_count = dp->link_train.lane_count;
475
476 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
477 if (retval < 0)
478 return retval;
479
480 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
481 adjust_request, 2);
482 if (retval < 0)
483 return retval;
484
485 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
486
487 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
488
489 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
490 DP_LINK_SCRAMBLING_DISABLE |
491 DP_TRAINING_PATTERN_2);
492 if (retval < 0)
493 return retval;
494
495 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
496 dp->link_train.lt_state = EQUALIZER_TRAINING;
497 } else {
498 for (lane = 0; lane < lane_count; lane++) {
499 training_lane = analogix_dp_get_lane_link_training(
500 dp, lane);
501 voltage_swing = analogix_dp_get_adjust_request_voltage(
502 adjust_request, lane);
503 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
504 adjust_request, lane);
505
506 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
507 voltage_swing &&
508 DPCD_PRE_EMPHASIS_GET(training_lane) ==
509 pre_emphasis)
510 dp->link_train.cr_loop[lane]++;
511
512 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
513 voltage_swing == VOLTAGE_LEVEL_3 ||
514 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
515 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
516 dp->link_train.cr_loop[lane],
517 voltage_swing, pre_emphasis);
518 analogix_dp_reduce_link_rate(dp);
519 return -EIO;
520 }
521 }
522 }
523
524 analogix_dp_get_adjust_training_lane(dp, adjust_request);
525
526 for (lane = 0; lane < lane_count; lane++)
527 analogix_dp_set_lane_link_training(dp,
528 dp->link_train.training_lane[lane], lane);
529
530 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
531 dp->link_train.training_lane, lane_count);
532 if (retval < 0)
533 return retval;
534
535 return 0;
536}
537
538static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
539{
540 int lane, lane_count, retval;
541 u32 reg;
542 u8 link_align, link_status[2], adjust_request[2];
543
544 usleep_range(400, 401);
545
546 lane_count = dp->link_train.lane_count;
547
548 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
549 if (retval < 0)
550 return retval;
551
552 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
553 analogix_dp_reduce_link_rate(dp);
554 return -EIO;
555 }
556
557 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
558 adjust_request, 2);
559 if (retval < 0)
560 return retval;
561
562 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
563 &link_align);
564 if (retval < 0)
565 return retval;
566
567 analogix_dp_get_adjust_training_lane(dp, adjust_request);
568
569 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
570
571 retval = analogix_dp_training_pattern_dis(dp);
572 if (retval < 0)
573 return retval;
574
575 dev_dbg(dp->dev, "Link Training success!\n");
576 analogix_dp_get_link_bandwidth(dp, ®);
577 dp->link_train.link_rate = reg;
578 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
579 dp->link_train.link_rate);
580
581 analogix_dp_get_lane_count(dp, ®);
582 dp->link_train.lane_count = reg;
583 dev_dbg(dp->dev, "final lane count = %.2x\n",
584 dp->link_train.lane_count);
585
586 dp->link_train.lt_state = FINISHED;
587
588 return 0;
589 }
590
591
592 dp->link_train.eq_loop++;
593
594 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
595 dev_err(dp->dev, "EQ Max loop\n");
596 analogix_dp_reduce_link_rate(dp);
597 return -EIO;
598 }
599
600 for (lane = 0; lane < lane_count; lane++)
601 analogix_dp_set_lane_link_training(dp,
602 dp->link_train.training_lane[lane], lane);
603
604 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
605 dp->link_train.training_lane, lane_count);
606 if (retval < 0)
607 return retval;
608
609 return 0;
610}
611
612static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
613 u8 *bandwidth)
614{
615 u8 data;
616
617
618
619
620
621
622
623 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
624 *bandwidth = data;
625}
626
627static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
628 u8 *lane_count)
629{
630 u8 data;
631
632
633
634
635
636 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
637 *lane_count = DPCD_MAX_LANE_COUNT(data);
638}
639
640static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
641 u32 max_lanes, u32 max_rate)
642{
643 int retval = 0;
644 bool training_finished = false;
645
646
647
648
649
650 analogix_dp_reset_macro(dp);
651
652
653 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
654 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
655
656 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
657 (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
658 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
659 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
660 dp->link_train.link_rate);
661 dp->link_train.link_rate = DP_LINK_BW_1_62;
662 }
663
664 if (dp->link_train.lane_count == 0) {
665 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
666 dp->link_train.lane_count);
667 dp->link_train.lane_count = (u8)LANE_COUNT1;
668 }
669
670
671 if (dp->link_train.lane_count > max_lanes)
672 dp->link_train.lane_count = max_lanes;
673 if (dp->link_train.link_rate > max_rate)
674 dp->link_train.link_rate = max_rate;
675
676
677 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
678
679 dp->link_train.lt_state = START;
680
681
682 while (!retval && !training_finished) {
683 switch (dp->link_train.lt_state) {
684 case START:
685 retval = analogix_dp_link_start(dp);
686 if (retval)
687 dev_err(dp->dev, "LT link start failed!\n");
688 break;
689 case CLOCK_RECOVERY:
690 retval = analogix_dp_process_clock_recovery(dp);
691 if (retval)
692 dev_err(dp->dev, "LT CR failed!\n");
693 break;
694 case EQUALIZER_TRAINING:
695 retval = analogix_dp_process_equalizer_training(dp);
696 if (retval)
697 dev_err(dp->dev, "LT EQ failed!\n");
698 break;
699 case FINISHED:
700 training_finished = 1;
701 break;
702 case FAILED:
703 return -EREMOTEIO;
704 }
705 }
706 if (retval)
707 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
708
709 return retval;
710}
711
712static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
713{
714 int i, ret;
715 u8 link_align, link_status[2];
716 enum pll_status status;
717
718 analogix_dp_reset_macro(dp);
719
720 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
721 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
722
723 for (i = 0; i < dp->link_train.lane_count; i++) {
724 analogix_dp_set_lane_link_training(dp,
725 dp->link_train.training_lane[i], i);
726 }
727
728 ret = readx_poll_timeout(analogix_dp_get_pll_lock_status, dp, status,
729 status != PLL_UNLOCKED, 120,
730 120 * DP_TIMEOUT_LOOP_COUNT);
731 if (ret) {
732 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
733 return ret;
734 }
735
736
737 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
738
739 usleep_range(500, 600);
740
741 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
742
743 usleep_range(500, 600);
744
745
746 analogix_dp_set_training_pattern(dp, DP_NONE);
747
748
749
750
751
752 if (verify_fast_training) {
753 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
754 &link_align);
755 if (ret < 0) {
756 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
757 ret);
758 return ret;
759 }
760
761 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
762 2);
763 if (ret < 0) {
764 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
765 ret);
766 return ret;
767 }
768
769 if (analogix_dp_clock_recovery_ok(link_status,
770 dp->link_train.lane_count)) {
771 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
772 analogix_dp_reduce_link_rate(dp);
773 return -EIO;
774 }
775
776 if (analogix_dp_channel_eq_ok(link_status, link_align,
777 dp->link_train.lane_count)) {
778 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
779 analogix_dp_reduce_link_rate(dp);
780 return -EIO;
781 }
782 }
783
784 return 0;
785}
786
787static int analogix_dp_train_link(struct analogix_dp_device *dp)
788{
789 if (dp->fast_train_enable)
790 return analogix_dp_fast_link_train(dp);
791
792 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
793 dp->video_info.max_link_rate);
794}
795
796static int analogix_dp_config_video(struct analogix_dp_device *dp)
797{
798 int timeout_loop = 0;
799 int done_count = 0;
800
801 analogix_dp_config_video_slave_mode(dp);
802
803 analogix_dp_set_video_color_format(dp);
804
805 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
806 dev_err(dp->dev, "PLL is not locked yet.\n");
807 return -EINVAL;
808 }
809
810 for (;;) {
811 timeout_loop++;
812 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
813 break;
814 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
815 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
816 return -ETIMEDOUT;
817 }
818 usleep_range(1000, 1001);
819 }
820
821
822 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
823
824
825 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
826
827
828 analogix_dp_enable_video_mute(dp, 0);
829
830
831 analogix_dp_enable_video_master(dp, 0);
832
833
834 analogix_dp_start_video(dp);
835
836 timeout_loop = 0;
837
838 for (;;) {
839 timeout_loop++;
840 if (analogix_dp_is_video_stream_on(dp) == 0) {
841 done_count++;
842 if (done_count > 10)
843 break;
844 } else if (done_count) {
845 done_count = 0;
846 }
847 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
848 dev_warn(dp->dev,
849 "Ignoring timeout of video streamclk ok\n");
850 break;
851 }
852
853 usleep_range(1000, 1001);
854 }
855
856 return 0;
857}
858
859static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
860 bool enable)
861{
862 u8 data;
863 int ret;
864
865 if (enable) {
866 analogix_dp_enable_scrambling(dp);
867
868 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
869 &data);
870 if (ret != 1)
871 return ret;
872 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
873 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
874 } else {
875 analogix_dp_disable_scrambling(dp);
876
877 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
878 &data);
879 if (ret != 1)
880 return ret;
881 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
882 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
883 }
884 return ret < 0 ? ret : 0;
885}
886
887static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
888{
889 struct analogix_dp_device *dp = arg;
890 irqreturn_t ret = IRQ_NONE;
891 enum dp_irq_type irq_type;
892
893 irq_type = analogix_dp_get_irq_type(dp);
894 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
895 analogix_dp_mute_hpd_interrupt(dp);
896 ret = IRQ_WAKE_THREAD;
897 }
898
899 return ret;
900}
901
902static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
903{
904 struct analogix_dp_device *dp = arg;
905 enum dp_irq_type irq_type;
906
907 irq_type = analogix_dp_get_irq_type(dp);
908 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
909 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
910 dev_dbg(dp->dev, "Detected cable status changed!\n");
911 if (dp->drm_dev)
912 drm_helper_hpd_irq_event(dp->drm_dev);
913 }
914
915 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
916 analogix_dp_clear_hotplug_interrupts(dp);
917 analogix_dp_unmute_hpd_interrupt(dp);
918 }
919
920 return IRQ_HANDLED;
921}
922
923static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
924{
925 int ret;
926 u8 spread;
927
928 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
929 if (ret != 1) {
930 dev_err(dp->dev, "failed to read downspread %d\n", ret);
931 return ret;
932 }
933 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
934 dev_dbg(dp->dev, "fast link training %s\n",
935 dp->fast_train_enable ? "supported" : "unsupported");
936 return 0;
937}
938
939static int analogix_dp_commit(struct analogix_dp_device *dp)
940{
941 int ret;
942
943
944 if (dp->plat_data->panel) {
945 if (drm_panel_disable(dp->plat_data->panel))
946 DRM_ERROR("failed to disable the panel\n");
947 }
948
949 ret = analogix_dp_train_link(dp);
950 if (ret) {
951 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
952 return ret;
953 }
954
955 ret = analogix_dp_enable_scramble(dp, 1);
956 if (ret < 0) {
957 dev_err(dp->dev, "can not enable scramble\n");
958 return ret;
959 }
960
961 analogix_dp_init_video(dp);
962 ret = analogix_dp_config_video(dp);
963 if (ret) {
964 dev_err(dp->dev, "unable to config video\n");
965 return ret;
966 }
967
968
969 if (dp->plat_data->panel) {
970 ret = drm_panel_enable(dp->plat_data->panel);
971 if (ret) {
972 DRM_ERROR("failed to enable the panel\n");
973 return ret;
974 }
975 }
976
977
978 ret = analogix_dp_fast_link_train_detection(dp);
979 if (ret)
980 return ret;
981
982 if (analogix_dp_detect_sink_psr(dp)) {
983 ret = analogix_dp_enable_sink_psr(dp);
984 if (ret)
985 return ret;
986 }
987
988 return ret;
989}
990
991static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
992{
993 struct dp_sdp psr_vsc;
994 int ret;
995 u8 sink;
996
997 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
998 if (ret != 1)
999 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1000 else if (sink == DP_PSR_SINK_ACTIVE_RFB)
1001 return 0;
1002
1003
1004 memset(&psr_vsc, 0, sizeof(psr_vsc));
1005 psr_vsc.sdp_header.HB0 = 0;
1006 psr_vsc.sdp_header.HB1 = 0x7;
1007 psr_vsc.sdp_header.HB2 = 0x2;
1008 psr_vsc.sdp_header.HB3 = 0x8;
1009 psr_vsc.db[0] = 0;
1010 psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
1011
1012 ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1013 if (!ret)
1014 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
1015
1016 return ret;
1017}
1018
1019static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
1020{
1021 struct dp_sdp psr_vsc;
1022 int ret;
1023 u8 sink;
1024
1025 analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
1026
1027 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
1028 if (ret != 1) {
1029 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
1030 return ret;
1031 }
1032
1033 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
1034 if (ret != 1) {
1035 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
1036 return ret;
1037 } else if (sink == DP_PSR_SINK_INACTIVE) {
1038 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
1039 return 0;
1040 }
1041
1042 ret = analogix_dp_train_link(dp);
1043 if (ret) {
1044 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
1045 return ret;
1046 }
1047
1048
1049 memset(&psr_vsc, 0, sizeof(psr_vsc));
1050 psr_vsc.sdp_header.HB0 = 0;
1051 psr_vsc.sdp_header.HB1 = 0x7;
1052 psr_vsc.sdp_header.HB2 = 0x2;
1053 psr_vsc.sdp_header.HB3 = 0x8;
1054
1055 psr_vsc.db[0] = 0;
1056 psr_vsc.db[1] = 0;
1057
1058 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
1059}
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
1075 bool prepare, bool is_modeset_prepare)
1076{
1077 int ret = 0;
1078
1079 if (!dp->plat_data->panel)
1080 return 0;
1081
1082 mutex_lock(&dp->panel_lock);
1083
1084
1085
1086
1087
1088 if (dp->panel_is_modeset && !is_modeset_prepare)
1089 goto out;
1090
1091 if (prepare)
1092 ret = drm_panel_prepare(dp->plat_data->panel);
1093 else
1094 ret = drm_panel_unprepare(dp->plat_data->panel);
1095
1096 if (ret)
1097 goto out;
1098
1099 if (is_modeset_prepare)
1100 dp->panel_is_modeset = prepare;
1101
1102out:
1103 mutex_unlock(&dp->panel_lock);
1104 return ret;
1105}
1106
1107static int analogix_dp_get_modes(struct drm_connector *connector)
1108{
1109 struct analogix_dp_device *dp = to_dp(connector);
1110 struct edid *edid;
1111 int ret, num_modes = 0;
1112
1113 if (dp->plat_data->panel) {
1114 num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
1115 } else {
1116 ret = analogix_dp_prepare_panel(dp, true, false);
1117 if (ret) {
1118 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1119 return 0;
1120 }
1121
1122 pm_runtime_get_sync(dp->dev);
1123 edid = drm_get_edid(connector, &dp->aux.ddc);
1124 pm_runtime_put(dp->dev);
1125 if (edid) {
1126 drm_connector_update_edid_property(&dp->connector,
1127 edid);
1128 num_modes += drm_add_edid_modes(&dp->connector, edid);
1129 kfree(edid);
1130 }
1131
1132 ret = analogix_dp_prepare_panel(dp, false, false);
1133 if (ret)
1134 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1135 }
1136
1137 if (dp->plat_data->get_modes)
1138 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
1139
1140 return num_modes;
1141}
1142
1143static struct drm_encoder *
1144analogix_dp_best_encoder(struct drm_connector *connector)
1145{
1146 struct analogix_dp_device *dp = to_dp(connector);
1147
1148 return dp->encoder;
1149}
1150
1151
1152static int analogix_dp_atomic_check(struct drm_connector *connector,
1153 struct drm_atomic_state *state)
1154{
1155 struct analogix_dp_device *dp = to_dp(connector);
1156 struct drm_connector_state *conn_state;
1157 struct drm_crtc_state *crtc_state;
1158
1159 conn_state = drm_atomic_get_new_connector_state(state, connector);
1160 if (WARN_ON(!conn_state))
1161 return -ENODEV;
1162
1163 conn_state->self_refresh_aware = true;
1164
1165 if (!conn_state->crtc)
1166 return 0;
1167
1168 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1169 if (!crtc_state)
1170 return 0;
1171
1172 if (crtc_state->self_refresh_active && !dp->psr_supported)
1173 return -EINVAL;
1174
1175 return 0;
1176}
1177
1178static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1179 .get_modes = analogix_dp_get_modes,
1180 .best_encoder = analogix_dp_best_encoder,
1181 .atomic_check = analogix_dp_atomic_check,
1182};
1183
1184static enum drm_connector_status
1185analogix_dp_detect(struct drm_connector *connector, bool force)
1186{
1187 struct analogix_dp_device *dp = to_dp(connector);
1188 enum drm_connector_status status = connector_status_disconnected;
1189 int ret;
1190
1191 if (dp->plat_data->panel)
1192 return connector_status_connected;
1193
1194 ret = analogix_dp_prepare_panel(dp, true, false);
1195 if (ret) {
1196 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
1197 return connector_status_disconnected;
1198 }
1199
1200 if (!analogix_dp_detect_hpd(dp))
1201 status = connector_status_connected;
1202
1203 ret = analogix_dp_prepare_panel(dp, false, false);
1204 if (ret)
1205 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
1206
1207 return status;
1208}
1209
1210static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1211 .fill_modes = drm_helper_probe_single_connector_modes,
1212 .detect = analogix_dp_detect,
1213 .destroy = drm_connector_cleanup,
1214 .reset = drm_atomic_helper_connector_reset,
1215 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1216 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1217};
1218
1219static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1220{
1221 struct analogix_dp_device *dp = bridge->driver_private;
1222 struct drm_encoder *encoder = dp->encoder;
1223 struct drm_connector *connector = NULL;
1224 int ret = 0;
1225
1226 if (!bridge->encoder) {
1227 DRM_ERROR("Parent encoder object not found");
1228 return -ENODEV;
1229 }
1230
1231 if (!dp->plat_data->skip_connector) {
1232 connector = &dp->connector;
1233 connector->polled = DRM_CONNECTOR_POLL_HPD;
1234
1235 ret = drm_connector_init(dp->drm_dev, connector,
1236 &analogix_dp_connector_funcs,
1237 DRM_MODE_CONNECTOR_eDP);
1238 if (ret) {
1239 DRM_ERROR("Failed to initialize connector with drm\n");
1240 return ret;
1241 }
1242
1243 drm_connector_helper_add(connector,
1244 &analogix_dp_connector_helper_funcs);
1245 drm_connector_attach_encoder(connector, encoder);
1246 }
1247
1248
1249
1250
1251
1252
1253
1254 if (dp->plat_data->attach) {
1255 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1256 if (ret) {
1257 DRM_ERROR("Failed at platform attach func\n");
1258 return ret;
1259 }
1260 }
1261
1262 if (dp->plat_data->panel) {
1263 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1264 if (ret) {
1265 DRM_ERROR("Failed to attach panel\n");
1266 return ret;
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273static
1274struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1275 struct drm_atomic_state *state)
1276{
1277 struct drm_encoder *encoder = dp->encoder;
1278 struct drm_connector *connector;
1279 struct drm_connector_state *conn_state;
1280
1281 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1282 if (!connector)
1283 return NULL;
1284
1285 conn_state = drm_atomic_get_new_connector_state(state, connector);
1286 if (!conn_state)
1287 return NULL;
1288
1289 return conn_state->crtc;
1290}
1291
1292static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1293 struct drm_atomic_state *state)
1294{
1295 struct analogix_dp_device *dp = bridge->driver_private;
1296 struct drm_crtc *crtc;
1297 struct drm_crtc_state *old_crtc_state;
1298 int ret;
1299
1300 crtc = analogix_dp_get_new_crtc(dp, state);
1301 if (!crtc)
1302 return;
1303
1304 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1305
1306 if (old_crtc_state && old_crtc_state->self_refresh_active)
1307 return;
1308
1309 ret = analogix_dp_prepare_panel(dp, true, true);
1310 if (ret)
1311 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1312}
1313
1314static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1315{
1316 int ret;
1317
1318 pm_runtime_get_sync(dp->dev);
1319
1320 ret = clk_prepare_enable(dp->clock);
1321 if (ret < 0) {
1322 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1323 goto out_dp_clk_pre;
1324 }
1325
1326 if (dp->plat_data->power_on_start)
1327 dp->plat_data->power_on_start(dp->plat_data);
1328
1329 phy_power_on(dp->phy);
1330
1331 ret = analogix_dp_init_dp(dp);
1332 if (ret)
1333 goto out_dp_init;
1334
1335
1336
1337
1338
1339
1340 ret = analogix_dp_detect_hpd(dp);
1341 if (ret) {
1342 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1343 goto out_dp_init;
1344 }
1345
1346 ret = analogix_dp_commit(dp);
1347 if (ret) {
1348 DRM_ERROR("dp commit error, ret = %d\n", ret);
1349 goto out_dp_init;
1350 }
1351
1352 if (dp->plat_data->power_on_end)
1353 dp->plat_data->power_on_end(dp->plat_data);
1354
1355 enable_irq(dp->irq);
1356 return 0;
1357
1358out_dp_init:
1359 phy_power_off(dp->phy);
1360 if (dp->plat_data->power_off)
1361 dp->plat_data->power_off(dp->plat_data);
1362 clk_disable_unprepare(dp->clock);
1363out_dp_clk_pre:
1364 pm_runtime_put_sync(dp->dev);
1365
1366 return ret;
1367}
1368
1369static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1370 struct drm_atomic_state *state)
1371{
1372 struct analogix_dp_device *dp = bridge->driver_private;
1373 struct drm_crtc *crtc;
1374 struct drm_crtc_state *old_crtc_state;
1375 int timeout_loop = 0;
1376 int ret;
1377
1378 crtc = analogix_dp_get_new_crtc(dp, state);
1379 if (!crtc)
1380 return;
1381
1382 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1383
1384 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1385 ret = analogix_dp_disable_psr(dp);
1386 if (ret)
1387 DRM_ERROR("Failed to disable psr %d\n", ret);
1388 return;
1389 }
1390
1391 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1392 return;
1393
1394 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1395 if (analogix_dp_set_bridge(dp) == 0) {
1396 dp->dpms_mode = DRM_MODE_DPMS_ON;
1397 return;
1398 }
1399 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1400 timeout_loop);
1401 timeout_loop++;
1402 usleep_range(10, 11);
1403 }
1404 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1405}
1406
1407static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1408{
1409 struct analogix_dp_device *dp = bridge->driver_private;
1410 int ret;
1411
1412 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1413 return;
1414
1415 if (dp->plat_data->panel) {
1416 if (drm_panel_disable(dp->plat_data->panel)) {
1417 DRM_ERROR("failed to disable the panel\n");
1418 return;
1419 }
1420 }
1421
1422 disable_irq(dp->irq);
1423
1424 if (dp->plat_data->power_off)
1425 dp->plat_data->power_off(dp->plat_data);
1426
1427 analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1428 phy_power_off(dp->phy);
1429
1430 clk_disable_unprepare(dp->clock);
1431
1432 pm_runtime_put_sync(dp->dev);
1433
1434 ret = analogix_dp_prepare_panel(dp, false, true);
1435 if (ret)
1436 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1437
1438 dp->fast_train_enable = false;
1439 dp->psr_supported = false;
1440 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1441}
1442
1443static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1444 struct drm_atomic_state *state)
1445{
1446 struct analogix_dp_device *dp = bridge->driver_private;
1447 struct drm_crtc *crtc;
1448 struct drm_crtc_state *new_crtc_state = NULL;
1449
1450 crtc = analogix_dp_get_new_crtc(dp, state);
1451 if (!crtc)
1452 goto out;
1453
1454 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1455 if (!new_crtc_state)
1456 goto out;
1457
1458
1459 if (new_crtc_state->self_refresh_active)
1460 return;
1461
1462out:
1463 analogix_dp_bridge_disable(bridge);
1464}
1465
1466static
1467void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1468 struct drm_atomic_state *state)
1469{
1470 struct analogix_dp_device *dp = bridge->driver_private;
1471 struct drm_crtc *crtc;
1472 struct drm_crtc_state *new_crtc_state;
1473 int ret;
1474
1475 crtc = analogix_dp_get_new_crtc(dp, state);
1476 if (!crtc)
1477 return;
1478
1479 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1480 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1481 return;
1482
1483 ret = analogix_dp_enable_psr(dp);
1484 if (ret)
1485 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1486}
1487
1488static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1489 const struct drm_display_mode *orig_mode,
1490 const struct drm_display_mode *mode)
1491{
1492 struct analogix_dp_device *dp = bridge->driver_private;
1493 struct drm_display_info *display_info = &dp->connector.display_info;
1494 struct video_info *video = &dp->video_info;
1495 struct device_node *dp_node = dp->dev->of_node;
1496 int vic;
1497
1498
1499 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1500 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1501 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1502
1503
1504 vic = drm_match_cea_mode(mode);
1505 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1506 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1507 video->dynamic_range = CEA;
1508 video->ycbcr_coeff = COLOR_YCBCR601;
1509 } else if (vic) {
1510 video->dynamic_range = CEA;
1511 video->ycbcr_coeff = COLOR_YCBCR709;
1512 } else {
1513 video->dynamic_range = VESA;
1514 video->ycbcr_coeff = COLOR_YCBCR709;
1515 }
1516
1517
1518 switch (display_info->bpc) {
1519 case 12:
1520 video->color_depth = COLOR_12;
1521 break;
1522 case 10:
1523 video->color_depth = COLOR_10;
1524 break;
1525 case 8:
1526 video->color_depth = COLOR_8;
1527 break;
1528 case 6:
1529 video->color_depth = COLOR_6;
1530 break;
1531 default:
1532 video->color_depth = COLOR_8;
1533 break;
1534 }
1535 if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1536 video->color_space = COLOR_YCBCR444;
1537 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1538 video->color_space = COLOR_YCBCR422;
1539 else
1540 video->color_space = COLOR_RGB;
1541
1542
1543
1544
1545
1546
1547
1548
1549 of_property_read_u32(dp_node, "samsung,color-space",
1550 &video->color_space);
1551 of_property_read_u32(dp_node, "samsung,dynamic-range",
1552 &video->dynamic_range);
1553 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1554 &video->ycbcr_coeff);
1555 of_property_read_u32(dp_node, "samsung,color-depth",
1556 &video->color_depth);
1557 if (of_property_read_bool(dp_node, "hsync-active-high"))
1558 video->h_sync_polarity = true;
1559 if (of_property_read_bool(dp_node, "vsync-active-high"))
1560 video->v_sync_polarity = true;
1561 if (of_property_read_bool(dp_node, "interlaced"))
1562 video->interlaced = true;
1563}
1564
1565static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1566 .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1567 .atomic_enable = analogix_dp_bridge_atomic_enable,
1568 .atomic_disable = analogix_dp_bridge_atomic_disable,
1569 .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1570 .mode_set = analogix_dp_bridge_mode_set,
1571 .attach = analogix_dp_bridge_attach,
1572};
1573
1574static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1575 struct analogix_dp_device *dp)
1576{
1577 struct drm_bridge *bridge;
1578 int ret;
1579
1580 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1581 if (!bridge) {
1582 DRM_ERROR("failed to allocate for drm bridge\n");
1583 return -ENOMEM;
1584 }
1585
1586 dp->bridge = bridge;
1587
1588 bridge->driver_private = dp;
1589 bridge->funcs = &analogix_dp_bridge_funcs;
1590
1591 ret = drm_bridge_attach(dp->encoder, bridge, NULL);
1592 if (ret) {
1593 DRM_ERROR("failed to attach drm bridge\n");
1594 return -EINVAL;
1595 }
1596
1597 return 0;
1598}
1599
1600static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1601{
1602 struct device_node *dp_node = dp->dev->of_node;
1603 struct video_info *video_info = &dp->video_info;
1604
1605 switch (dp->plat_data->dev_type) {
1606 case RK3288_DP:
1607 case RK3399_EDP:
1608
1609
1610
1611
1612 video_info->max_link_rate = 0x0A;
1613 video_info->max_lane_count = 0x04;
1614 break;
1615 case EXYNOS_DP:
1616
1617
1618
1619
1620 of_property_read_u32(dp_node, "samsung,link-rate",
1621 &video_info->max_link_rate);
1622 of_property_read_u32(dp_node, "samsung,lane-count",
1623 &video_info->max_lane_count);
1624 break;
1625 }
1626
1627 return 0;
1628}
1629
1630static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1631 struct drm_dp_aux_msg *msg)
1632{
1633 struct analogix_dp_device *dp = to_dp(aux);
1634
1635 return analogix_dp_transfer(dp, msg);
1636}
1637
1638struct analogix_dp_device *
1639analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1640 struct analogix_dp_plat_data *plat_data)
1641{
1642 struct platform_device *pdev = to_platform_device(dev);
1643 struct analogix_dp_device *dp;
1644 struct resource *res;
1645 unsigned int irq_flags;
1646 int ret;
1647
1648 if (!plat_data) {
1649 dev_err(dev, "Invalided input plat_data\n");
1650 return ERR_PTR(-EINVAL);
1651 }
1652
1653 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1654 if (!dp)
1655 return ERR_PTR(-ENOMEM);
1656
1657 dp->dev = &pdev->dev;
1658 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1659
1660 mutex_init(&dp->panel_lock);
1661 dp->panel_is_modeset = false;
1662
1663
1664
1665
1666
1667
1668 dp->plat_data = plat_data;
1669
1670 ret = analogix_dp_dt_parse_pdata(dp);
1671 if (ret)
1672 return ERR_PTR(ret);
1673
1674 dp->phy = devm_phy_get(dp->dev, "dp");
1675 if (IS_ERR(dp->phy)) {
1676 dev_err(dp->dev, "no DP phy configured\n");
1677 ret = PTR_ERR(dp->phy);
1678 if (ret) {
1679
1680
1681
1682
1683 if (ret == -ENOSYS || ret == -ENODEV)
1684 dp->phy = NULL;
1685 else
1686 return ERR_PTR(ret);
1687 }
1688 }
1689
1690 dp->clock = devm_clk_get(&pdev->dev, "dp");
1691 if (IS_ERR(dp->clock)) {
1692 dev_err(&pdev->dev, "failed to get clock\n");
1693 return ERR_CAST(dp->clock);
1694 }
1695
1696 clk_prepare_enable(dp->clock);
1697
1698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1699
1700 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1701 if (IS_ERR(dp->reg_base))
1702 return ERR_CAST(dp->reg_base);
1703
1704 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1705
1706
1707 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1708 if (!dp->hpd_gpiod)
1709 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1710 GPIOD_IN);
1711 if (IS_ERR(dp->hpd_gpiod)) {
1712 dev_err(dev, "error getting HDP GPIO: %ld\n",
1713 PTR_ERR(dp->hpd_gpiod));
1714 return ERR_CAST(dp->hpd_gpiod);
1715 }
1716
1717 if (dp->hpd_gpiod) {
1718
1719
1720
1721
1722
1723
1724
1725 dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1726 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1727 } else {
1728 dp->irq = platform_get_irq(pdev, 0);
1729 irq_flags = 0;
1730 }
1731
1732 if (dp->irq == -ENXIO) {
1733 dev_err(&pdev->dev, "failed to get irq\n");
1734 return ERR_PTR(-ENODEV);
1735 }
1736
1737 ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1738 analogix_dp_hardirq,
1739 analogix_dp_irq_thread,
1740 irq_flags, "analogix-dp", dp);
1741 if (ret) {
1742 dev_err(&pdev->dev, "failed to request irq\n");
1743 goto err_disable_pm_runtime;
1744 }
1745 disable_irq(dp->irq);
1746
1747 dp->drm_dev = drm_dev;
1748 dp->encoder = dp->plat_data->encoder;
1749
1750 dp->aux.name = "DP-AUX";
1751 dp->aux.transfer = analogix_dpaux_transfer;
1752 dp->aux.dev = &pdev->dev;
1753
1754 ret = drm_dp_aux_register(&dp->aux);
1755 if (ret)
1756 return ERR_PTR(ret);
1757
1758 pm_runtime_enable(dev);
1759
1760 ret = analogix_dp_create_bridge(drm_dev, dp);
1761 if (ret) {
1762 DRM_ERROR("failed to create bridge (%d)\n", ret);
1763 goto err_disable_pm_runtime;
1764 }
1765
1766 return dp;
1767
1768err_disable_pm_runtime:
1769
1770 pm_runtime_disable(dev);
1771
1772 return ERR_PTR(ret);
1773}
1774EXPORT_SYMBOL_GPL(analogix_dp_bind);
1775
1776void analogix_dp_unbind(struct analogix_dp_device *dp)
1777{
1778 analogix_dp_bridge_disable(dp->bridge);
1779 dp->connector.funcs->destroy(&dp->connector);
1780
1781 if (dp->plat_data->panel) {
1782 if (drm_panel_unprepare(dp->plat_data->panel))
1783 DRM_ERROR("failed to turnoff the panel\n");
1784 drm_panel_detach(dp->plat_data->panel);
1785 }
1786
1787 drm_dp_aux_unregister(&dp->aux);
1788 pm_runtime_disable(dp->dev);
1789 clk_disable_unprepare(dp->clock);
1790}
1791EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1792
1793#ifdef CONFIG_PM
1794int analogix_dp_suspend(struct analogix_dp_device *dp)
1795{
1796 clk_disable_unprepare(dp->clock);
1797
1798 if (dp->plat_data->panel) {
1799 if (drm_panel_unprepare(dp->plat_data->panel))
1800 DRM_ERROR("failed to turnoff the panel\n");
1801 }
1802
1803 return 0;
1804}
1805EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1806
1807int analogix_dp_resume(struct analogix_dp_device *dp)
1808{
1809 int ret;
1810
1811 ret = clk_prepare_enable(dp->clock);
1812 if (ret < 0) {
1813 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1814 return ret;
1815 }
1816
1817 if (dp->plat_data->panel) {
1818 if (drm_panel_prepare(dp->plat_data->panel)) {
1819 DRM_ERROR("failed to setup the panel\n");
1820 return -EBUSY;
1821 }
1822 }
1823
1824 return 0;
1825}
1826EXPORT_SYMBOL_GPL(analogix_dp_resume);
1827#endif
1828
1829int analogix_dp_start_crc(struct drm_connector *connector)
1830{
1831 struct analogix_dp_device *dp = to_dp(connector);
1832
1833 if (!connector->state->crtc) {
1834 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1835 connector->name);
1836 return -EINVAL;
1837 }
1838
1839 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1840}
1841EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1842
1843int analogix_dp_stop_crc(struct drm_connector *connector)
1844{
1845 struct analogix_dp_device *dp = to_dp(connector);
1846
1847 return drm_dp_stop_crc(&dp->aux);
1848}
1849EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1850
1851MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1852MODULE_DESCRIPTION("Analogix DP Core Driver");
1853MODULE_LICENSE("GPL v2");
1854
