1/* SPDX-License-Identifier: MIT */ 2#ifndef __NVIF_CL0080_H__ 3#define __NVIF_CL0080_H__ 4 5struct nv_device_v0 { 6 __u8 version; 7 __u8 pad01[7]; 8 __u64 device; /* device identifier, ~0 for client default */ 9}; 10 11#define NV_DEVICE_V0_INFO 0x00 12#define NV_DEVICE_V0_TIME 0x01 13 14struct nv_device_info_v0 { 15 __u8 version; 16#define NV_DEVICE_INFO_V0_IGP 0x00 17#define NV_DEVICE_INFO_V0_PCI 0x01 18#define NV_DEVICE_INFO_V0_AGP 0x02 19#define NV_DEVICE_INFO_V0_PCIE 0x03 20#define NV_DEVICE_INFO_V0_SOC 0x04 21 __u8 platform; 22 __u16 chipset; /* from NV_PMC_BOOT_0 */ 23 __u8 revision; /* from NV_PMC_BOOT_0 */ 24#define NV_DEVICE_INFO_V0_TNT 0x01 25#define NV_DEVICE_INFO_V0_CELSIUS 0x02 26#define NV_DEVICE_INFO_V0_KELVIN 0x03 27#define NV_DEVICE_INFO_V0_RANKINE 0x04 28#define NV_DEVICE_INFO_V0_CURIE 0x05 29#define NV_DEVICE_INFO_V0_TESLA 0x06 30#define NV_DEVICE_INFO_V0_FERMI 0x07 31#define NV_DEVICE_INFO_V0_KEPLER 0x08 32#define NV_DEVICE_INFO_V0_MAXWELL 0x09 33#define NV_DEVICE_INFO_V0_PASCAL 0x0a 34#define NV_DEVICE_INFO_V0_VOLTA 0x0b 35#define NV_DEVICE_INFO_V0_TURING 0x0c 36 __u8 family; 37 __u8 pad06[2]; 38 __u64 ram_size; 39 __u64 ram_user; 40 char chip[16]; 41 char name[64]; 42}; 43 44struct nv_device_info_v1 { 45 __u8 version; 46 __u8 count; 47 __u8 pad02[6]; 48 struct nv_device_info_v1_data { 49 __u64 mthd; /* NV_DEVICE_INFO_* (see below). */ 50 __u64 data; 51 } data[]; 52}; 53 54struct nv_device_time_v0 { 55 __u8 version; 56 __u8 pad01[7]; 57 __u64 time; 58}; 59 60#define NV_DEVICE_INFO_UNIT (0xffffffffULL << 32) 61#define NV_DEVICE_INFO(n) ((n) | (0x00000000ULL << 32)) 62#define NV_DEVICE_FIFO(n) ((n) | (0x00000001ULL << 32)) 63 64/* This will be returned for unsupported queries. */ 65#define NV_DEVICE_INFO_INVALID ~0ULL 66 67/* These return a mask of available engines of particular type. */ 68#define NV_DEVICE_INFO_ENGINE_SW NV_DEVICE_INFO(0x00000000) 69#define NV_DEVICE_INFO_ENGINE_GR NV_DEVICE_INFO(0x00000001) 70#define NV_DEVICE_INFO_ENGINE_MPEG NV_DEVICE_INFO(0x00000002) 71#define NV_DEVICE_INFO_ENGINE_ME NV_DEVICE_INFO(0x00000003) 72#define NV_DEVICE_INFO_ENGINE_CIPHER NV_DEVICE_INFO(0x00000004) 73#define NV_DEVICE_INFO_ENGINE_BSP NV_DEVICE_INFO(0x00000005) 74#define NV_DEVICE_INFO_ENGINE_VP NV_DEVICE_INFO(0x00000006) 75#define NV_DEVICE_INFO_ENGINE_CE NV_DEVICE_INFO(0x00000007) 76#define NV_DEVICE_INFO_ENGINE_SEC NV_DEVICE_INFO(0x00000008) 77#define NV_DEVICE_INFO_ENGINE_MSVLD NV_DEVICE_INFO(0x00000009) 78#define NV_DEVICE_INFO_ENGINE_MSPDEC NV_DEVICE_INFO(0x0000000a) 79#define NV_DEVICE_INFO_ENGINE_MSPPP NV_DEVICE_INFO(0x0000000b) 80#define NV_DEVICE_INFO_ENGINE_MSENC NV_DEVICE_INFO(0x0000000c) 81#define NV_DEVICE_INFO_ENGINE_VIC NV_DEVICE_INFO(0x0000000d) 82#define NV_DEVICE_INFO_ENGINE_SEC2 NV_DEVICE_INFO(0x0000000e) 83#define NV_DEVICE_INFO_ENGINE_NVDEC NV_DEVICE_INFO(0x0000000f) 84#define NV_DEVICE_INFO_ENGINE_NVENC NV_DEVICE_INFO(0x00000010) 85 86/* Returns the number of available channels. */ 87#define NV_DEVICE_FIFO_CHANNELS NV_DEVICE_FIFO(0x00000000) 88 89/* Returns a mask of available runlists. */ 90#define NV_DEVICE_FIFO_RUNLISTS NV_DEVICE_FIFO(0x00000001) 91 92/* These return a mask of engines available on a particular runlist. */ 93#define NV_DEVICE_FIFO_RUNLIST_ENGINES(n) ((n) + NV_DEVICE_FIFO(0x00000010)) 94#define NV_DEVICE_FIFO_RUNLIST_ENGINES__SIZE 64 95#endif 96