LXR linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#include "nv04.h"
  25#include "channv04.h"
  26#include "regsnv04.h"
  27
  28#include <core/ramht.h>
  29#include <subdev/instmem.h>
  30
  31static const struct nv04_fifo_ramfc
  32nv17_fifo_ramfc[] = {
  33        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  34        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  35        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  36        { 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  37        { 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  38        { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  39        { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  40        { 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
  41        { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
  42        { 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  43        { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  44        { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  45        { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  46        { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  47        {}
  48};
  49
  50static void
  51nv17_fifo_init(struct nvkm_fifo *base)
  52{
  53        struct nv04_fifo *fifo = nv04_fifo(base);
  54        struct nvkm_device *device = fifo->base.engine.subdev.device;
  55        struct nvkm_instmem *imem = device->imem;
  56        struct nvkm_ramht *ramht = imem->ramht;
  57        struct nvkm_memory *ramro = imem->ramro;
  58        struct nvkm_memory *ramfc = imem->ramfc;
  59
  60        nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
  61        nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
  62
  63        nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
  64                                            ((ramht->bits - 9) << 16) |
  65                                            (ramht->gpuobj->addr >> 8));
  66        nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
  67        nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 |
  68                                            0x00010000);
  69
  70        nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);
  71
  72        nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
  73        nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
  74
  75        nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
  76        nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
  77        nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
  78}
  79
  80static const struct nvkm_fifo_func
  81nv17_fifo = {
  82        .init = nv17_fifo_init,
  83        .intr = nv04_fifo_intr,
  84        .pause = nv04_fifo_pause,
  85        .start = nv04_fifo_start,
  86        .chan = {
  87                &nv17_fifo_dma_oclass,
  88                NULL
  89        },
  90};
  91
  92int
  93nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
  94{
  95        return nv04_fifo_new_(&nv17_fifo, device, index, 32,
  96                              nv17_fifo_ramfc, pfifo);
  97}
  98