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7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/device.h>
13#include <linux/sysfs.h>
14#include <linux/pci.h>
15
16#include "intel_th.h"
17
18#define DRIVER_NAME "intel_th_pci"
19
20enum {
21 TH_PCI_CONFIG_BAR = 0,
22 TH_PCI_STH_SW_BAR = 2,
23 TH_PCI_RTIT_BAR = 4,
24};
25
26#define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR))
27
28#define PCI_REG_NPKDSC 0x80
29#define NPKDSC_TSACT BIT(5)
30
31static int intel_th_pci_activate(struct intel_th *th)
32{
33 struct pci_dev *pdev = to_pci_dev(th->dev);
34 u32 npkdsc;
35 int err;
36
37 if (!INTEL_TH_CAP(th, tscu_enable))
38 return 0;
39
40 err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
41 if (!err) {
42 npkdsc |= NPKDSC_TSACT;
43 err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
44 }
45
46 if (err)
47 dev_err(&pdev->dev, "failed to read NPKDSC register\n");
48
49 return err;
50}
51
52static void intel_th_pci_deactivate(struct intel_th *th)
53{
54 struct pci_dev *pdev = to_pci_dev(th->dev);
55 u32 npkdsc;
56 int err;
57
58 if (!INTEL_TH_CAP(th, tscu_enable))
59 return;
60
61 err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
62 if (!err) {
63 npkdsc |= NPKDSC_TSACT;
64 err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
65 }
66
67 if (err)
68 dev_err(&pdev->dev, "failed to read NPKDSC register\n");
69}
70
71static int intel_th_pci_probe(struct pci_dev *pdev,
72 const struct pci_device_id *id)
73{
74 struct intel_th_drvdata *drvdata = (void *)id->driver_data;
75 struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
76 [TH_MMIO_CONFIG] = pdev->resource[TH_PCI_CONFIG_BAR],
77 [TH_MMIO_SW] = pdev->resource[TH_PCI_STH_SW_BAR],
78 };
79 int err, r = TH_MMIO_SW + 1, i;
80 struct intel_th *th;
81
82 err = pcim_enable_device(pdev);
83 if (err)
84 return err;
85
86 err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
87 if (err)
88 return err;
89
90 if (pdev->resource[TH_PCI_RTIT_BAR].start) {
91 resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
92 r++;
93 }
94
95 err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES);
96 if (err > 0)
97 for (i = 0; i < err; i++, r++) {
98 resource[r].flags = IORESOURCE_IRQ;
99 resource[r].start = pci_irq_vector(pdev, i);
100 }
101
102 th = intel_th_alloc(&pdev->dev, drvdata, resource, r);
103 if (IS_ERR(th))
104 return PTR_ERR(th);
105
106 th->activate = intel_th_pci_activate;
107 th->deactivate = intel_th_pci_deactivate;
108
109 pci_set_master(pdev);
110
111 return 0;
112}
113
114static void intel_th_pci_remove(struct pci_dev *pdev)
115{
116 struct intel_th *th = pci_get_drvdata(pdev);
117
118 intel_th_free(th);
119
120 pci_free_irq_vectors(pdev);
121}
122
123static const struct intel_th_drvdata intel_th_2x = {
124 .tscu_enable = 1,
125 .has_mintctl = 1,
126};
127
128static const struct pci_device_id intel_th_pci_id_table[] = {
129 {
130 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9d26),
131 .driver_data = (kernel_ulong_t)0,
132 },
133 {
134 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa126),
135 .driver_data = (kernel_ulong_t)0,
136 },
137 {
138
139 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x5a8e),
140 .driver_data = (kernel_ulong_t)0,
141 },
142 {
143
144 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0a80),
145 .driver_data = (kernel_ulong_t)0,
146 },
147 {
148
149 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1a8e),
150 .driver_data = (kernel_ulong_t)0,
151 },
152 {
153
154 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
155 .driver_data = (kernel_ulong_t)0,
156 },
157 {
158
159 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
160 .driver_data = (kernel_ulong_t)0,
161 },
162 {
163
164 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
165 .driver_data = (kernel_ulong_t)0,
166 },
167 {
168
169 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa226),
170 .driver_data = (kernel_ulong_t)0,
171 },
172 {
173
174 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
175 .driver_data = (kernel_ulong_t)&intel_th_2x,
176 },
177 {
178
179 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa326),
180 .driver_data = (kernel_ulong_t)&intel_th_2x,
181 },
182 {
183
184 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
185 .driver_data = (kernel_ulong_t)&intel_th_2x,
186 },
187 {
188
189 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
190 .driver_data = (kernel_ulong_t)&intel_th_2x,
191 },
192 {
193
194 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x34a6),
195 .driver_data = (kernel_ulong_t)&intel_th_2x,
196 },
197 {
198
199 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x02a6),
200 .driver_data = (kernel_ulong_t)&intel_th_2x,
201 },
202 {
203
204 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x06a6),
205 .driver_data = (kernel_ulong_t)&intel_th_2x,
206 },
207 {
208
209 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa3a6),
210 .driver_data = (kernel_ulong_t)&intel_th_2x,
211 },
212 {
213
214 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x45c5),
215 .driver_data = (kernel_ulong_t)&intel_th_2x,
216 },
217 {
218
219 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8a29),
220 .driver_data = (kernel_ulong_t)&intel_th_2x,
221 },
222 {
223
224 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9a33),
225 .driver_data = (kernel_ulong_t)&intel_th_2x,
226 },
227 {
228
229 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
230 .driver_data = (kernel_ulong_t)&intel_th_2x,
231 },
232 {
233
234 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
235 .driver_data = (kernel_ulong_t)&intel_th_2x,
236 },
237 {
238
239 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
240 .driver_data = (kernel_ulong_t)&intel_th_2x,
241 },
242 {
243
244 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),
245 .driver_data = (kernel_ulong_t)&intel_th_2x,
246 },
247 { 0 },
248};
249
250MODULE_DEVICE_TABLE(pci, intel_th_pci_id_table);
251
252static struct pci_driver intel_th_pci_driver = {
253 .name = DRIVER_NAME,
254 .id_table = intel_th_pci_id_table,
255 .probe = intel_th_pci_probe,
256 .remove = intel_th_pci_remove,
257};
258
259module_pci_driver(intel_th_pci_driver);
260
261MODULE_LICENSE("GPL v2");
262MODULE_DESCRIPTION("Intel(R) Trace Hub PCI controller driver");
263MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@intel.com>");
264
