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8#include <linux/clk.h>
9#include <linux/bitfield.h>
10#include <linux/of_irq.h>
11#include <linux/interrupt.h>
12#include <linux/delay.h>
13#include <linux/mutex.h>
14#include <linux/device.h>
15#include <linux/kernel.h>
16#include <linux/spi/spi.h>
17#include <linux/slab.h>
18#include <linux/sysfs.h>
19#include <linux/module.h>
20
21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
24#include <linux/iio/imu/adis.h>
25
26#include <linux/debugfs.h>
27
28#define ADIS16480_PAGE_SIZE 0x80
29
30#define ADIS16480_REG(page, reg) ((page) * ADIS16480_PAGE_SIZE + (reg))
31
32#define ADIS16480_REG_PAGE_ID 0x00
33#define ADIS16480_REG_SEQ_CNT ADIS16480_REG(0x00, 0x06)
34#define ADIS16480_REG_SYS_E_FLA ADIS16480_REG(0x00, 0x08)
35#define ADIS16480_REG_DIAG_STS ADIS16480_REG(0x00, 0x0A)
36#define ADIS16480_REG_ALM_STS ADIS16480_REG(0x00, 0x0C)
37#define ADIS16480_REG_TEMP_OUT ADIS16480_REG(0x00, 0x0E)
38#define ADIS16480_REG_X_GYRO_OUT ADIS16480_REG(0x00, 0x10)
39#define ADIS16480_REG_Y_GYRO_OUT ADIS16480_REG(0x00, 0x14)
40#define ADIS16480_REG_Z_GYRO_OUT ADIS16480_REG(0x00, 0x18)
41#define ADIS16480_REG_X_ACCEL_OUT ADIS16480_REG(0x00, 0x1C)
42#define ADIS16480_REG_Y_ACCEL_OUT ADIS16480_REG(0x00, 0x20)
43#define ADIS16480_REG_Z_ACCEL_OUT ADIS16480_REG(0x00, 0x24)
44#define ADIS16480_REG_X_MAGN_OUT ADIS16480_REG(0x00, 0x28)
45#define ADIS16480_REG_Y_MAGN_OUT ADIS16480_REG(0x00, 0x2A)
46#define ADIS16480_REG_Z_MAGN_OUT ADIS16480_REG(0x00, 0x2C)
47#define ADIS16480_REG_BAROM_OUT ADIS16480_REG(0x00, 0x2E)
48#define ADIS16480_REG_X_DELTAANG_OUT ADIS16480_REG(0x00, 0x40)
49#define ADIS16480_REG_Y_DELTAANG_OUT ADIS16480_REG(0x00, 0x44)
50#define ADIS16480_REG_Z_DELTAANG_OUT ADIS16480_REG(0x00, 0x48)
51#define ADIS16480_REG_X_DELTAVEL_OUT ADIS16480_REG(0x00, 0x4C)
52#define ADIS16480_REG_Y_DELTAVEL_OUT ADIS16480_REG(0x00, 0x50)
53#define ADIS16480_REG_Z_DELTAVEL_OUT ADIS16480_REG(0x00, 0x54)
54#define ADIS16480_REG_PROD_ID ADIS16480_REG(0x00, 0x7E)
55
56#define ADIS16480_REG_X_GYRO_SCALE ADIS16480_REG(0x02, 0x04)
57#define ADIS16480_REG_Y_GYRO_SCALE ADIS16480_REG(0x02, 0x06)
58#define ADIS16480_REG_Z_GYRO_SCALE ADIS16480_REG(0x02, 0x08)
59#define ADIS16480_REG_X_ACCEL_SCALE ADIS16480_REG(0x02, 0x0A)
60#define ADIS16480_REG_Y_ACCEL_SCALE ADIS16480_REG(0x02, 0x0C)
61#define ADIS16480_REG_Z_ACCEL_SCALE ADIS16480_REG(0x02, 0x0E)
62#define ADIS16480_REG_X_GYRO_BIAS ADIS16480_REG(0x02, 0x10)
63#define ADIS16480_REG_Y_GYRO_BIAS ADIS16480_REG(0x02, 0x14)
64#define ADIS16480_REG_Z_GYRO_BIAS ADIS16480_REG(0x02, 0x18)
65#define ADIS16480_REG_X_ACCEL_BIAS ADIS16480_REG(0x02, 0x1C)
66#define ADIS16480_REG_Y_ACCEL_BIAS ADIS16480_REG(0x02, 0x20)
67#define ADIS16480_REG_Z_ACCEL_BIAS ADIS16480_REG(0x02, 0x24)
68#define ADIS16480_REG_X_HARD_IRON ADIS16480_REG(0x02, 0x28)
69#define ADIS16480_REG_Y_HARD_IRON ADIS16480_REG(0x02, 0x2A)
70#define ADIS16480_REG_Z_HARD_IRON ADIS16480_REG(0x02, 0x2C)
71#define ADIS16480_REG_BAROM_BIAS ADIS16480_REG(0x02, 0x40)
72#define ADIS16480_REG_FLASH_CNT ADIS16480_REG(0x02, 0x7C)
73
74#define ADIS16480_REG_GLOB_CMD ADIS16480_REG(0x03, 0x02)
75#define ADIS16480_REG_FNCTIO_CTRL ADIS16480_REG(0x03, 0x06)
76#define ADIS16480_REG_GPIO_CTRL ADIS16480_REG(0x03, 0x08)
77#define ADIS16480_REG_CONFIG ADIS16480_REG(0x03, 0x0A)
78#define ADIS16480_REG_DEC_RATE ADIS16480_REG(0x03, 0x0C)
79#define ADIS16480_REG_SLP_CNT ADIS16480_REG(0x03, 0x10)
80#define ADIS16480_REG_FILTER_BNK0 ADIS16480_REG(0x03, 0x16)
81#define ADIS16480_REG_FILTER_BNK1 ADIS16480_REG(0x03, 0x18)
82#define ADIS16480_REG_ALM_CNFG0 ADIS16480_REG(0x03, 0x20)
83#define ADIS16480_REG_ALM_CNFG1 ADIS16480_REG(0x03, 0x22)
84#define ADIS16480_REG_ALM_CNFG2 ADIS16480_REG(0x03, 0x24)
85#define ADIS16480_REG_XG_ALM_MAGN ADIS16480_REG(0x03, 0x28)
86#define ADIS16480_REG_YG_ALM_MAGN ADIS16480_REG(0x03, 0x2A)
87#define ADIS16480_REG_ZG_ALM_MAGN ADIS16480_REG(0x03, 0x2C)
88#define ADIS16480_REG_XA_ALM_MAGN ADIS16480_REG(0x03, 0x2E)
89#define ADIS16480_REG_YA_ALM_MAGN ADIS16480_REG(0x03, 0x30)
90#define ADIS16480_REG_ZA_ALM_MAGN ADIS16480_REG(0x03, 0x32)
91#define ADIS16480_REG_XM_ALM_MAGN ADIS16480_REG(0x03, 0x34)
92#define ADIS16480_REG_YM_ALM_MAGN ADIS16480_REG(0x03, 0x36)
93#define ADIS16480_REG_ZM_ALM_MAGN ADIS16480_REG(0x03, 0x38)
94#define ADIS16480_REG_BR_ALM_MAGN ADIS16480_REG(0x03, 0x3A)
95#define ADIS16480_REG_FIRM_REV ADIS16480_REG(0x03, 0x78)
96#define ADIS16480_REG_FIRM_DM ADIS16480_REG(0x03, 0x7A)
97#define ADIS16480_REG_FIRM_Y ADIS16480_REG(0x03, 0x7C)
98
99
100
101
102
103#define ADIS16495_REG_SYNC_SCALE ADIS16480_REG(0x03, 0x10)
104
105#define ADIS16480_REG_SERIAL_NUM ADIS16480_REG(0x04, 0x20)
106
107
108#define ADIS16480_FIR_COEF(page) (x < 60 ? ADIS16480_REG(page, (x) + 8) : \
109 ADIS16480_REG((page) + 1, (x) - 60 + 8))
110#define ADIS16480_FIR_COEF_A(x) ADIS16480_FIR_COEF(0x05, (x))
111#define ADIS16480_FIR_COEF_B(x) ADIS16480_FIR_COEF(0x07, (x))
112#define ADIS16480_FIR_COEF_C(x) ADIS16480_FIR_COEF(0x09, (x))
113#define ADIS16480_FIR_COEF_D(x) ADIS16480_FIR_COEF(0x0B, (x))
114
115
116#define ADIS16480_DRDY_SEL_MSK GENMASK(1, 0)
117#define ADIS16480_DRDY_SEL(x) FIELD_PREP(ADIS16480_DRDY_SEL_MSK, x)
118#define ADIS16480_DRDY_POL_MSK BIT(2)
119#define ADIS16480_DRDY_POL(x) FIELD_PREP(ADIS16480_DRDY_POL_MSK, x)
120#define ADIS16480_DRDY_EN_MSK BIT(3)
121#define ADIS16480_DRDY_EN(x) FIELD_PREP(ADIS16480_DRDY_EN_MSK, x)
122#define ADIS16480_SYNC_SEL_MSK GENMASK(5, 4)
123#define ADIS16480_SYNC_SEL(x) FIELD_PREP(ADIS16480_SYNC_SEL_MSK, x)
124#define ADIS16480_SYNC_EN_MSK BIT(7)
125#define ADIS16480_SYNC_EN(x) FIELD_PREP(ADIS16480_SYNC_EN_MSK, x)
126#define ADIS16480_SYNC_MODE_MSK BIT(8)
127#define ADIS16480_SYNC_MODE(x) FIELD_PREP(ADIS16480_SYNC_MODE_MSK, x)
128
129struct adis16480_chip_info {
130 unsigned int num_channels;
131 const struct iio_chan_spec *channels;
132 unsigned int gyro_max_val;
133 unsigned int gyro_max_scale;
134 unsigned int accel_max_val;
135 unsigned int accel_max_scale;
136 unsigned int temp_scale;
137 unsigned int int_clk;
138 unsigned int max_dec_rate;
139 const unsigned int *filter_freqs;
140 bool has_pps_clk_mode;
141 const struct adis_timeout *timeouts;
142};
143
144enum adis16480_int_pin {
145 ADIS16480_PIN_DIO1,
146 ADIS16480_PIN_DIO2,
147 ADIS16480_PIN_DIO3,
148 ADIS16480_PIN_DIO4
149};
150
151enum adis16480_clock_mode {
152 ADIS16480_CLK_SYNC,
153 ADIS16480_CLK_PPS,
154 ADIS16480_CLK_INT
155};
156
157struct adis16480 {
158 const struct adis16480_chip_info *chip_info;
159
160 struct adis adis;
161 struct clk *ext_clk;
162 enum adis16480_clock_mode clk_mode;
163 unsigned int clk_freq;
164};
165
166static const char * const adis16480_int_pin_names[4] = {
167 [ADIS16480_PIN_DIO1] = "DIO1",
168 [ADIS16480_PIN_DIO2] = "DIO2",
169 [ADIS16480_PIN_DIO3] = "DIO3",
170 [ADIS16480_PIN_DIO4] = "DIO4",
171};
172
173#ifdef CONFIG_DEBUG_FS
174
175static ssize_t adis16480_show_firmware_revision(struct file *file,
176 char __user *userbuf, size_t count, loff_t *ppos)
177{
178 struct adis16480 *adis16480 = file->private_data;
179 char buf[7];
180 size_t len;
181 u16 rev;
182 int ret;
183
184 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev);
185 if (ret)
186 return ret;
187
188 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
189
190 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
191}
192
193static const struct file_operations adis16480_firmware_revision_fops = {
194 .open = simple_open,
195 .read = adis16480_show_firmware_revision,
196 .llseek = default_llseek,
197 .owner = THIS_MODULE,
198};
199
200static ssize_t adis16480_show_firmware_date(struct file *file,
201 char __user *userbuf, size_t count, loff_t *ppos)
202{
203 struct adis16480 *adis16480 = file->private_data;
204 u16 md, year;
205 char buf[12];
206 size_t len;
207 int ret;
208
209 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year);
210 if (ret)
211 return ret;
212
213 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md);
214 if (ret)
215 return ret;
216
217 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n",
218 md >> 8, md & 0xff, year);
219
220 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
221}
222
223static const struct file_operations adis16480_firmware_date_fops = {
224 .open = simple_open,
225 .read = adis16480_show_firmware_date,
226 .llseek = default_llseek,
227 .owner = THIS_MODULE,
228};
229
230static int adis16480_show_serial_number(void *arg, u64 *val)
231{
232 struct adis16480 *adis16480 = arg;
233 u16 serial;
234 int ret;
235
236 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_SERIAL_NUM,
237 &serial);
238 if (ret)
239 return ret;
240
241 *val = serial;
242
243 return 0;
244}
245DEFINE_DEBUGFS_ATTRIBUTE(adis16480_serial_number_fops,
246 adis16480_show_serial_number, NULL, "0x%.4llx\n");
247
248static int adis16480_show_product_id(void *arg, u64 *val)
249{
250 struct adis16480 *adis16480 = arg;
251 u16 prod_id;
252 int ret;
253
254 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_PROD_ID,
255 &prod_id);
256 if (ret)
257 return ret;
258
259 *val = prod_id;
260
261 return 0;
262}
263DEFINE_DEBUGFS_ATTRIBUTE(adis16480_product_id_fops,
264 adis16480_show_product_id, NULL, "%llu\n");
265
266static int adis16480_show_flash_count(void *arg, u64 *val)
267{
268 struct adis16480 *adis16480 = arg;
269 u32 flash_count;
270 int ret;
271
272 ret = adis_read_reg_32(&adis16480->adis, ADIS16480_REG_FLASH_CNT,
273 &flash_count);
274 if (ret)
275 return ret;
276
277 *val = flash_count;
278
279 return 0;
280}
281DEFINE_DEBUGFS_ATTRIBUTE(adis16480_flash_count_fops,
282 adis16480_show_flash_count, NULL, "%lld\n");
283
284static int adis16480_debugfs_init(struct iio_dev *indio_dev)
285{
286 struct adis16480 *adis16480 = iio_priv(indio_dev);
287
288 debugfs_create_file_unsafe("firmware_revision", 0400,
289 indio_dev->debugfs_dentry, adis16480,
290 &adis16480_firmware_revision_fops);
291 debugfs_create_file_unsafe("firmware_date", 0400,
292 indio_dev->debugfs_dentry, adis16480,
293 &adis16480_firmware_date_fops);
294 debugfs_create_file_unsafe("serial_number", 0400,
295 indio_dev->debugfs_dentry, adis16480,
296 &adis16480_serial_number_fops);
297 debugfs_create_file_unsafe("product_id", 0400,
298 indio_dev->debugfs_dentry, adis16480,
299 &adis16480_product_id_fops);
300 debugfs_create_file_unsafe("flash_count", 0400,
301 indio_dev->debugfs_dentry, adis16480,
302 &adis16480_flash_count_fops);
303
304 return 0;
305}
306
307#else
308
309static int adis16480_debugfs_init(struct iio_dev *indio_dev)
310{
311 return 0;
312}
313
314#endif
315
316static int adis16480_set_freq(struct iio_dev *indio_dev, int val, int val2)
317{
318 struct adis16480 *st = iio_priv(indio_dev);
319 unsigned int t, reg;
320
321 if (val < 0 || val2 < 0)
322 return -EINVAL;
323
324 t = val * 1000 + val2 / 1000;
325 if (t == 0)
326 return -EINVAL;
327
328
329
330
331
332
333
334
335 if (st->clk_mode == ADIS16480_CLK_PPS) {
336 t = t / st->clk_freq;
337 reg = ADIS16495_REG_SYNC_SCALE;
338 } else {
339 t = st->clk_freq / t;
340 reg = ADIS16480_REG_DEC_RATE;
341 }
342
343 if (t > st->chip_info->max_dec_rate)
344 t = st->chip_info->max_dec_rate;
345
346 if ((t != 0) && (st->clk_mode != ADIS16480_CLK_PPS))
347 t--;
348
349 return adis_write_reg_16(&st->adis, reg, t);
350}
351
352static int adis16480_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
353{
354 struct adis16480 *st = iio_priv(indio_dev);
355 uint16_t t;
356 int ret;
357 unsigned int freq;
358 unsigned int reg;
359
360 if (st->clk_mode == ADIS16480_CLK_PPS)
361 reg = ADIS16495_REG_SYNC_SCALE;
362 else
363 reg = ADIS16480_REG_DEC_RATE;
364
365 ret = adis_read_reg_16(&st->adis, reg, &t);
366 if (ret)
367 return ret;
368
369
370
371
372
373
374
375
376 if (st->clk_mode == ADIS16480_CLK_PPS)
377 freq = st->clk_freq * t;
378 else
379 freq = st->clk_freq / (t + 1);
380
381 *val = freq / 1000;
382 *val2 = (freq % 1000) * 1000;
383
384 return IIO_VAL_INT_PLUS_MICRO;
385}
386
387enum {
388 ADIS16480_SCAN_GYRO_X,
389 ADIS16480_SCAN_GYRO_Y,
390 ADIS16480_SCAN_GYRO_Z,
391 ADIS16480_SCAN_ACCEL_X,
392 ADIS16480_SCAN_ACCEL_Y,
393 ADIS16480_SCAN_ACCEL_Z,
394 ADIS16480_SCAN_MAGN_X,
395 ADIS16480_SCAN_MAGN_Y,
396 ADIS16480_SCAN_MAGN_Z,
397 ADIS16480_SCAN_BARO,
398 ADIS16480_SCAN_TEMP,
399};
400
401static const unsigned int adis16480_calibbias_regs[] = {
402 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_BIAS,
403 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_BIAS,
404 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_BIAS,
405 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_BIAS,
406 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_BIAS,
407 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_BIAS,
408 [ADIS16480_SCAN_MAGN_X] = ADIS16480_REG_X_HARD_IRON,
409 [ADIS16480_SCAN_MAGN_Y] = ADIS16480_REG_Y_HARD_IRON,
410 [ADIS16480_SCAN_MAGN_Z] = ADIS16480_REG_Z_HARD_IRON,
411 [ADIS16480_SCAN_BARO] = ADIS16480_REG_BAROM_BIAS,
412};
413
414static const unsigned int adis16480_calibscale_regs[] = {
415 [ADIS16480_SCAN_GYRO_X] = ADIS16480_REG_X_GYRO_SCALE,
416 [ADIS16480_SCAN_GYRO_Y] = ADIS16480_REG_Y_GYRO_SCALE,
417 [ADIS16480_SCAN_GYRO_Z] = ADIS16480_REG_Z_GYRO_SCALE,
418 [ADIS16480_SCAN_ACCEL_X] = ADIS16480_REG_X_ACCEL_SCALE,
419 [ADIS16480_SCAN_ACCEL_Y] = ADIS16480_REG_Y_ACCEL_SCALE,
420 [ADIS16480_SCAN_ACCEL_Z] = ADIS16480_REG_Z_ACCEL_SCALE,
421};
422
423static int adis16480_set_calibbias(struct iio_dev *indio_dev,
424 const struct iio_chan_spec *chan, int bias)
425{
426 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
427 struct adis16480 *st = iio_priv(indio_dev);
428
429 switch (chan->type) {
430 case IIO_MAGN:
431 case IIO_PRESSURE:
432 if (bias < -0x8000 || bias >= 0x8000)
433 return -EINVAL;
434 return adis_write_reg_16(&st->adis, reg, bias);
435 case IIO_ANGL_VEL:
436 case IIO_ACCEL:
437 return adis_write_reg_32(&st->adis, reg, bias);
438 default:
439 break;
440 }
441
442 return -EINVAL;
443}
444
445static int adis16480_get_calibbias(struct iio_dev *indio_dev,
446 const struct iio_chan_spec *chan, int *bias)
447{
448 unsigned int reg = adis16480_calibbias_regs[chan->scan_index];
449 struct adis16480 *st = iio_priv(indio_dev);
450 uint16_t val16;
451 uint32_t val32;
452 int ret;
453
454 switch (chan->type) {
455 case IIO_MAGN:
456 case IIO_PRESSURE:
457 ret = adis_read_reg_16(&st->adis, reg, &val16);
458 if (ret == 0)
459 *bias = sign_extend32(val16, 15);
460 break;
461 case IIO_ANGL_VEL:
462 case IIO_ACCEL:
463 ret = adis_read_reg_32(&st->adis, reg, &val32);
464 if (ret == 0)
465 *bias = sign_extend32(val32, 31);
466 break;
467 default:
468 ret = -EINVAL;
469 }
470
471 if (ret)
472 return ret;
473
474 return IIO_VAL_INT;
475}
476
477static int adis16480_set_calibscale(struct iio_dev *indio_dev,
478 const struct iio_chan_spec *chan, int scale)
479{
480 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
481 struct adis16480 *st = iio_priv(indio_dev);
482
483 if (scale < -0x8000 || scale >= 0x8000)
484 return -EINVAL;
485
486 return adis_write_reg_16(&st->adis, reg, scale);
487}
488
489static int adis16480_get_calibscale(struct iio_dev *indio_dev,
490 const struct iio_chan_spec *chan, int *scale)
491{
492 unsigned int reg = adis16480_calibscale_regs[chan->scan_index];
493 struct adis16480 *st = iio_priv(indio_dev);
494 uint16_t val16;
495 int ret;
496
497 ret = adis_read_reg_16(&st->adis, reg, &val16);
498 if (ret)
499 return ret;
500
501 *scale = sign_extend32(val16, 15);
502 return IIO_VAL_INT;
503}
504
505static const unsigned int adis16480_def_filter_freqs[] = {
506 310,
507 55,
508 275,
509 63,
510};
511
512static const unsigned int adis16495_def_filter_freqs[] = {
513 300,
514 100,
515 300,
516 100,
517};
518
519static const unsigned int ad16480_filter_data[][2] = {
520 [ADIS16480_SCAN_GYRO_X] = { ADIS16480_REG_FILTER_BNK0, 0 },
521 [ADIS16480_SCAN_GYRO_Y] = { ADIS16480_REG_FILTER_BNK0, 3 },
522 [ADIS16480_SCAN_GYRO_Z] = { ADIS16480_REG_FILTER_BNK0, 6 },
523 [ADIS16480_SCAN_ACCEL_X] = { ADIS16480_REG_FILTER_BNK0, 9 },
524 [ADIS16480_SCAN_ACCEL_Y] = { ADIS16480_REG_FILTER_BNK0, 12 },
525 [ADIS16480_SCAN_ACCEL_Z] = { ADIS16480_REG_FILTER_BNK1, 0 },
526 [ADIS16480_SCAN_MAGN_X] = { ADIS16480_REG_FILTER_BNK1, 3 },
527 [ADIS16480_SCAN_MAGN_Y] = { ADIS16480_REG_FILTER_BNK1, 6 },
528 [ADIS16480_SCAN_MAGN_Z] = { ADIS16480_REG_FILTER_BNK1, 9 },
529};
530
531static int adis16480_get_filter_freq(struct iio_dev *indio_dev,
532 const struct iio_chan_spec *chan, int *freq)
533{
534 struct adis16480 *st = iio_priv(indio_dev);
535 unsigned int enable_mask, offset, reg;
536 uint16_t val;
537 int ret;
538
539 reg = ad16480_filter_data[chan->scan_index][0];
540 offset = ad16480_filter_data[chan->scan_index][1];
541 enable_mask = BIT(offset + 2);
542
543 ret = adis_read_reg_16(&st->adis, reg, &val);
544 if (ret)
545 return ret;
546
547 if (!(val & enable_mask))
548 *freq = 0;
549 else
550 *freq = st->chip_info->filter_freqs[(val >> offset) & 0x3];
551
552 return IIO_VAL_INT;
553}
554
555static int adis16480_set_filter_freq(struct iio_dev *indio_dev,
556 const struct iio_chan_spec *chan, unsigned int freq)
557{
558 struct adis16480 *st = iio_priv(indio_dev);
559 struct mutex *slock = &st->adis.state_lock;
560 unsigned int enable_mask, offset, reg;
561 unsigned int diff, best_diff;
562 unsigned int i, best_freq;
563 uint16_t val;
564 int ret;
565
566 reg = ad16480_filter_data[chan->scan_index][0];
567 offset = ad16480_filter_data[chan->scan_index][1];
568 enable_mask = BIT(offset + 2);
569
570 mutex_lock(slock);
571
572 ret = __adis_read_reg_16(&st->adis, reg, &val);
573 if (ret)
574 goto out_unlock;
575
576 if (freq == 0) {
577 val &= ~enable_mask;
578 } else {
579 best_freq = 0;
580 best_diff = st->chip_info->filter_freqs[0];
581 for (i = 0; i < ARRAY_SIZE(adis16480_def_filter_freqs); i++) {
582 if (st->chip_info->filter_freqs[i] >= freq) {
583 diff = st->chip_info->filter_freqs[i] - freq;
584 if (diff < best_diff) {
585 best_diff = diff;
586 best_freq = i;
587 }
588 }
589 }
590
591 val &= ~(0x3 << offset);
592 val |= best_freq << offset;
593 val |= enable_mask;
594 }
595
596 ret = __adis_write_reg_16(&st->adis, reg, val);
597out_unlock:
598 mutex_unlock(slock);
599
600 return ret;
601}
602
603static int adis16480_read_raw(struct iio_dev *indio_dev,
604 const struct iio_chan_spec *chan, int *val, int *val2, long info)
605{
606 struct adis16480 *st = iio_priv(indio_dev);
607 unsigned int temp;
608
609 switch (info) {
610 case IIO_CHAN_INFO_RAW:
611 return adis_single_conversion(indio_dev, chan, 0, val);
612 case IIO_CHAN_INFO_SCALE:
613 switch (chan->type) {
614 case IIO_ANGL_VEL:
615 *val = st->chip_info->gyro_max_scale;
616 *val2 = st->chip_info->gyro_max_val;
617 return IIO_VAL_FRACTIONAL;
618 case IIO_ACCEL:
619 *val = st->chip_info->accel_max_scale;
620 *val2 = st->chip_info->accel_max_val;
621 return IIO_VAL_FRACTIONAL;
622 case IIO_MAGN:
623 *val = 0;
624 *val2 = 100;
625 return IIO_VAL_INT_PLUS_MICRO;
626 case IIO_TEMP:
627
628
629
630
631
632 *val = st->chip_info->temp_scale / 1000;
633 *val2 = (st->chip_info->temp_scale % 1000) * 1000;
634 return IIO_VAL_INT_PLUS_MICRO;
635 case IIO_PRESSURE:
636
637
638
639
640 *val = 131;
641 *val2 = 32767 << 16;
642 return IIO_VAL_FRACTIONAL;
643 default:
644 return -EINVAL;
645 }
646 case IIO_CHAN_INFO_OFFSET:
647
648 temp = 25 * 1000000LL;
649 *val = DIV_ROUND_CLOSEST_ULL(temp, st->chip_info->temp_scale);
650 return IIO_VAL_INT;
651 case IIO_CHAN_INFO_CALIBBIAS:
652 return adis16480_get_calibbias(indio_dev, chan, val);
653 case IIO_CHAN_INFO_CALIBSCALE:
654 return adis16480_get_calibscale(indio_dev, chan, val);
655 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
656 return adis16480_get_filter_freq(indio_dev, chan, val);
657 case IIO_CHAN_INFO_SAMP_FREQ:
658 return adis16480_get_freq(indio_dev, val, val2);
659 default:
660 return -EINVAL;
661 }
662}
663
664static int adis16480_write_raw(struct iio_dev *indio_dev,
665 const struct iio_chan_spec *chan, int val, int val2, long info)
666{
667 switch (info) {
668 case IIO_CHAN_INFO_CALIBBIAS:
669 return adis16480_set_calibbias(indio_dev, chan, val);
670 case IIO_CHAN_INFO_CALIBSCALE:
671 return adis16480_set_calibscale(indio_dev, chan, val);
672 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
673 return adis16480_set_filter_freq(indio_dev, chan, val);
674 case IIO_CHAN_INFO_SAMP_FREQ:
675 return adis16480_set_freq(indio_dev, val, val2);
676
677 default:
678 return -EINVAL;
679 }
680}
681
682#define ADIS16480_MOD_CHANNEL(_type, _mod, _address, _si, _info_sep, _bits) \
683 { \
684 .type = (_type), \
685 .modified = 1, \
686 .channel2 = (_mod), \
687 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
688 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
689 _info_sep, \
690 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
691 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
692 .address = (_address), \
693 .scan_index = (_si), \
694 .scan_type = { \
695 .sign = 's', \
696 .realbits = (_bits), \
697 .storagebits = (_bits), \
698 .endianness = IIO_BE, \
699 }, \
700 }
701
702#define ADIS16480_GYRO_CHANNEL(_mod) \
703 ADIS16480_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
704 ADIS16480_REG_ ## _mod ## _GYRO_OUT, ADIS16480_SCAN_GYRO_ ## _mod, \
705 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
706 BIT(IIO_CHAN_INFO_CALIBSCALE), \
707 32)
708
709#define ADIS16480_ACCEL_CHANNEL(_mod) \
710 ADIS16480_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
711 ADIS16480_REG_ ## _mod ## _ACCEL_OUT, ADIS16480_SCAN_ACCEL_ ## _mod, \
712 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
713 BIT(IIO_CHAN_INFO_CALIBSCALE), \
714 32)
715
716#define ADIS16480_MAGN_CHANNEL(_mod) \
717 ADIS16480_MOD_CHANNEL(IIO_MAGN, IIO_MOD_ ## _mod, \
718 ADIS16480_REG_ ## _mod ## _MAGN_OUT, ADIS16480_SCAN_MAGN_ ## _mod, \
719 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
720 16)
721
722#define ADIS16480_PRESSURE_CHANNEL() \
723 { \
724 .type = IIO_PRESSURE, \
725 .indexed = 1, \
726 .channel = 0, \
727 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
728 BIT(IIO_CHAN_INFO_CALIBBIAS) | \
729 BIT(IIO_CHAN_INFO_SCALE), \
730 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
731 .address = ADIS16480_REG_BAROM_OUT, \
732 .scan_index = ADIS16480_SCAN_BARO, \
733 .scan_type = { \
734 .sign = 's', \
735 .realbits = 32, \
736 .storagebits = 32, \
737 .endianness = IIO_BE, \
738 }, \
739 }
740
741#define ADIS16480_TEMP_CHANNEL() { \
742 .type = IIO_TEMP, \
743 .indexed = 1, \
744 .channel = 0, \
745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
746 BIT(IIO_CHAN_INFO_SCALE) | \
747 BIT(IIO_CHAN_INFO_OFFSET), \
748 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
749 .address = ADIS16480_REG_TEMP_OUT, \
750 .scan_index = ADIS16480_SCAN_TEMP, \
751 .scan_type = { \
752 .sign = 's', \
753 .realbits = 16, \
754 .storagebits = 16, \
755 .endianness = IIO_BE, \
756 }, \
757 }
758
759static const struct iio_chan_spec adis16480_channels[] = {
760 ADIS16480_GYRO_CHANNEL(X),
761 ADIS16480_GYRO_CHANNEL(Y),
762 ADIS16480_GYRO_CHANNEL(Z),
763 ADIS16480_ACCEL_CHANNEL(X),
764 ADIS16480_ACCEL_CHANNEL(Y),
765 ADIS16480_ACCEL_CHANNEL(Z),
766 ADIS16480_MAGN_CHANNEL(X),
767 ADIS16480_MAGN_CHANNEL(Y),
768 ADIS16480_MAGN_CHANNEL(Z),
769 ADIS16480_PRESSURE_CHANNEL(),
770 ADIS16480_TEMP_CHANNEL(),
771 IIO_CHAN_SOFT_TIMESTAMP(11)
772};
773
774static const struct iio_chan_spec adis16485_channels[] = {
775 ADIS16480_GYRO_CHANNEL(X),
776 ADIS16480_GYRO_CHANNEL(Y),
777 ADIS16480_GYRO_CHANNEL(Z),
778 ADIS16480_ACCEL_CHANNEL(X),
779 ADIS16480_ACCEL_CHANNEL(Y),
780 ADIS16480_ACCEL_CHANNEL(Z),
781 ADIS16480_TEMP_CHANNEL(),
782 IIO_CHAN_SOFT_TIMESTAMP(7)
783};
784
785enum adis16480_variant {
786 ADIS16375,
787 ADIS16480,
788 ADIS16485,
789 ADIS16488,
790 ADIS16490,
791 ADIS16495_1,
792 ADIS16495_2,
793 ADIS16495_3,
794 ADIS16497_1,
795 ADIS16497_2,
796 ADIS16497_3,
797};
798
799static const struct adis_timeout adis16485_timeouts = {
800 .reset_ms = 560,
801 .sw_reset_ms = 120,
802 .self_test_ms = 12,
803};
804
805static const struct adis_timeout adis16480_timeouts = {
806 .reset_ms = 560,
807 .sw_reset_ms = 560,
808 .self_test_ms = 12,
809};
810
811static const struct adis_timeout adis16495_timeouts = {
812 .reset_ms = 170,
813 .sw_reset_ms = 130,
814 .self_test_ms = 40,
815};
816
817static const struct adis_timeout adis16495_1_timeouts = {
818 .reset_ms = 250,
819 .sw_reset_ms = 210,
820 .self_test_ms = 20,
821};
822
823static const struct adis16480_chip_info adis16480_chip_info[] = {
824 [ADIS16375] = {
825 .channels = adis16485_channels,
826 .num_channels = ARRAY_SIZE(adis16485_channels),
827
828
829
830
831
832
833 .gyro_max_val = 22887 << 16,
834 .gyro_max_scale = IIO_DEGREE_TO_RAD(300),
835 .accel_max_val = IIO_M_S_2_TO_G(21973 << 16),
836 .accel_max_scale = 18,
837 .temp_scale = 5650,
838 .int_clk = 2460000,
839 .max_dec_rate = 2048,
840 .filter_freqs = adis16480_def_filter_freqs,
841 .timeouts = &adis16485_timeouts,
842 },
843 [ADIS16480] = {
844 .channels = adis16480_channels,
845 .num_channels = ARRAY_SIZE(adis16480_channels),
846 .gyro_max_val = 22500 << 16,
847 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
848 .accel_max_val = IIO_M_S_2_TO_G(12500 << 16),
849 .accel_max_scale = 10,
850 .temp_scale = 5650,
851 .int_clk = 2460000,
852 .max_dec_rate = 2048,
853 .filter_freqs = adis16480_def_filter_freqs,
854 .timeouts = &adis16480_timeouts,
855 },
856 [ADIS16485] = {
857 .channels = adis16485_channels,
858 .num_channels = ARRAY_SIZE(adis16485_channels),
859 .gyro_max_val = 22500 << 16,
860 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
861 .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
862 .accel_max_scale = 5,
863 .temp_scale = 5650,
864 .int_clk = 2460000,
865 .max_dec_rate = 2048,
866 .filter_freqs = adis16480_def_filter_freqs,
867 .timeouts = &adis16485_timeouts,
868 },
869 [ADIS16488] = {
870 .channels = adis16480_channels,
871 .num_channels = ARRAY_SIZE(adis16480_channels),
872 .gyro_max_val = 22500 << 16,
873 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
874 .accel_max_val = IIO_M_S_2_TO_G(22500 << 16),
875 .accel_max_scale = 18,
876 .temp_scale = 5650,
877 .int_clk = 2460000,
878 .max_dec_rate = 2048,
879 .filter_freqs = adis16480_def_filter_freqs,
880 .timeouts = &adis16485_timeouts,
881 },
882 [ADIS16490] = {
883 .channels = adis16485_channels,
884 .num_channels = ARRAY_SIZE(adis16485_channels),
885 .gyro_max_val = 20000 << 16,
886 .gyro_max_scale = IIO_DEGREE_TO_RAD(100),
887 .accel_max_val = IIO_M_S_2_TO_G(16000 << 16),
888 .accel_max_scale = 8,
889 .temp_scale = 14285,
890 .int_clk = 4250000,
891 .max_dec_rate = 4250,
892 .filter_freqs = adis16495_def_filter_freqs,
893 .has_pps_clk_mode = true,
894 .timeouts = &adis16495_timeouts,
895 },
896 [ADIS16495_1] = {
897 .channels = adis16485_channels,
898 .num_channels = ARRAY_SIZE(adis16485_channels),
899 .gyro_max_val = 20000 << 16,
900 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
901 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
902 .accel_max_scale = 8,
903 .temp_scale = 12500,
904 .int_clk = 4250000,
905 .max_dec_rate = 4250,
906 .filter_freqs = adis16495_def_filter_freqs,
907 .has_pps_clk_mode = true,
908 .timeouts = &adis16495_1_timeouts,
909 },
910 [ADIS16495_2] = {
911 .channels = adis16485_channels,
912 .num_channels = ARRAY_SIZE(adis16485_channels),
913 .gyro_max_val = 18000 << 16,
914 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
915 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
916 .accel_max_scale = 8,
917 .temp_scale = 12500,
918 .int_clk = 4250000,
919 .max_dec_rate = 4250,
920 .filter_freqs = adis16495_def_filter_freqs,
921 .has_pps_clk_mode = true,
922 .timeouts = &adis16495_1_timeouts,
923 },
924 [ADIS16495_3] = {
925 .channels = adis16485_channels,
926 .num_channels = ARRAY_SIZE(adis16485_channels),
927 .gyro_max_val = 20000 << 16,
928 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
929 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
930 .accel_max_scale = 8,
931 .temp_scale = 12500,
932 .int_clk = 4250000,
933 .max_dec_rate = 4250,
934 .filter_freqs = adis16495_def_filter_freqs,
935 .has_pps_clk_mode = true,
936 .timeouts = &adis16495_1_timeouts,
937 },
938 [ADIS16497_1] = {
939 .channels = adis16485_channels,
940 .num_channels = ARRAY_SIZE(adis16485_channels),
941 .gyro_max_val = 20000 << 16,
942 .gyro_max_scale = IIO_DEGREE_TO_RAD(125),
943 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
944 .accel_max_scale = 40,
945 .temp_scale = 12500,
946 .int_clk = 4250000,
947 .max_dec_rate = 4250,
948 .filter_freqs = adis16495_def_filter_freqs,
949 .has_pps_clk_mode = true,
950 .timeouts = &adis16495_1_timeouts,
951 },
952 [ADIS16497_2] = {
953 .channels = adis16485_channels,
954 .num_channels = ARRAY_SIZE(adis16485_channels),
955 .gyro_max_val = 18000 << 16,
956 .gyro_max_scale = IIO_DEGREE_TO_RAD(450),
957 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
958 .accel_max_scale = 40,
959 .temp_scale = 12500,
960 .int_clk = 4250000,
961 .max_dec_rate = 4250,
962 .filter_freqs = adis16495_def_filter_freqs,
963 .has_pps_clk_mode = true,
964 .timeouts = &adis16495_1_timeouts,
965 },
966 [ADIS16497_3] = {
967 .channels = adis16485_channels,
968 .num_channels = ARRAY_SIZE(adis16485_channels),
969 .gyro_max_val = 20000 << 16,
970 .gyro_max_scale = IIO_DEGREE_TO_RAD(2000),
971 .accel_max_val = IIO_M_S_2_TO_G(32000 << 16),
972 .accel_max_scale = 40,
973 .temp_scale = 12500,
974 .int_clk = 4250000,
975 .max_dec_rate = 4250,
976 .filter_freqs = adis16495_def_filter_freqs,
977 .has_pps_clk_mode = true,
978 .timeouts = &adis16495_1_timeouts,
979 },
980};
981
982static const struct iio_info adis16480_info = {
983 .read_raw = &adis16480_read_raw,
984 .write_raw = &adis16480_write_raw,
985 .update_scan_mode = adis_update_scan_mode,
986 .debugfs_reg_access = adis_debugfs_reg_access,
987};
988
989static int adis16480_stop_device(struct iio_dev *indio_dev)
990{
991 struct adis16480 *st = iio_priv(indio_dev);
992 int ret;
993
994 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_SLP_CNT, BIT(9));
995 if (ret)
996 dev_err(&indio_dev->dev,
997 "Could not power down device: %d\n", ret);
998
999 return ret;
1000}
1001
1002static int adis16480_enable_irq(struct adis *adis, bool enable)
1003{
1004 uint16_t val;
1005 int ret;
1006
1007 ret = __adis_read_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1008 if (ret)
1009 return ret;
1010
1011 val &= ~ADIS16480_DRDY_EN_MSK;
1012 val |= ADIS16480_DRDY_EN(enable);
1013
1014 return __adis_write_reg_16(adis, ADIS16480_REG_FNCTIO_CTRL, val);
1015}
1016
1017static int adis16480_initial_setup(struct iio_dev *indio_dev)
1018{
1019 struct adis16480 *st = iio_priv(indio_dev);
1020 uint16_t prod_id;
1021 unsigned int device_id;
1022 int ret;
1023
1024 adis_reset(&st->adis);
1025 msleep(70);
1026
1027 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_GLOB_CMD, BIT(1));
1028 if (ret)
1029 return ret;
1030 msleep(30);
1031
1032 ret = adis_check_status(&st->adis);
1033 if (ret)
1034 return ret;
1035
1036 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_PROD_ID, &prod_id);
1037 if (ret)
1038 return ret;
1039
1040 ret = sscanf(indio_dev->name, "adis%u\n", &device_id);
1041 if (ret != 1)
1042 return -EINVAL;
1043
1044 if (prod_id != device_id)
1045 dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.",
1046 device_id, prod_id);
1047
1048 return 0;
1049}
1050
1051#define ADIS16480_DIAG_STAT_XGYRO_FAIL 0
1052#define ADIS16480_DIAG_STAT_YGYRO_FAIL 1
1053#define ADIS16480_DIAG_STAT_ZGYRO_FAIL 2
1054#define ADIS16480_DIAG_STAT_XACCL_FAIL 3
1055#define ADIS16480_DIAG_STAT_YACCL_FAIL 4
1056#define ADIS16480_DIAG_STAT_ZACCL_FAIL 5
1057#define ADIS16480_DIAG_STAT_XMAGN_FAIL 8
1058#define ADIS16480_DIAG_STAT_YMAGN_FAIL 9
1059#define ADIS16480_DIAG_STAT_ZMAGN_FAIL 10
1060#define ADIS16480_DIAG_STAT_BARO_FAIL 11
1061
1062static const char * const adis16480_status_error_msgs[] = {
1063 [ADIS16480_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
1064 [ADIS16480_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
1065 [ADIS16480_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
1066 [ADIS16480_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
1067 [ADIS16480_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
1068 [ADIS16480_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
1069 [ADIS16480_DIAG_STAT_XMAGN_FAIL] = "X-axis magnetometer self-test failure",
1070 [ADIS16480_DIAG_STAT_YMAGN_FAIL] = "Y-axis magnetometer self-test failure",
1071 [ADIS16480_DIAG_STAT_ZMAGN_FAIL] = "Z-axis magnetometer self-test failure",
1072 [ADIS16480_DIAG_STAT_BARO_FAIL] = "Barometer self-test failure",
1073};
1074
1075static const struct adis_data adis16480_data = {
1076 .diag_stat_reg = ADIS16480_REG_DIAG_STS,
1077 .glob_cmd_reg = ADIS16480_REG_GLOB_CMD,
1078 .has_paging = true,
1079
1080 .read_delay = 5,
1081 .write_delay = 5,
1082
1083 .status_error_msgs = adis16480_status_error_msgs,
1084 .status_error_mask = BIT(ADIS16480_DIAG_STAT_XGYRO_FAIL) |
1085 BIT(ADIS16480_DIAG_STAT_YGYRO_FAIL) |
1086 BIT(ADIS16480_DIAG_STAT_ZGYRO_FAIL) |
1087 BIT(ADIS16480_DIAG_STAT_XACCL_FAIL) |
1088 BIT(ADIS16480_DIAG_STAT_YACCL_FAIL) |
1089 BIT(ADIS16480_DIAG_STAT_ZACCL_FAIL) |
1090 BIT(ADIS16480_DIAG_STAT_XMAGN_FAIL) |
1091 BIT(ADIS16480_DIAG_STAT_YMAGN_FAIL) |
1092 BIT(ADIS16480_DIAG_STAT_ZMAGN_FAIL) |
1093 BIT(ADIS16480_DIAG_STAT_BARO_FAIL),
1094
1095 .enable_irq = adis16480_enable_irq,
1096};
1097
1098static int adis16480_config_irq_pin(struct device_node *of_node,
1099 struct adis16480 *st)
1100{
1101 struct irq_data *desc;
1102 enum adis16480_int_pin pin;
1103 unsigned int irq_type;
1104 uint16_t val;
1105 int i, irq = 0;
1106
1107 desc = irq_get_irq_data(st->adis.spi->irq);
1108 if (!desc) {
1109 dev_err(&st->adis.spi->dev, "Could not find IRQ %d\n", irq);
1110 return -EINVAL;
1111 }
1112
1113
1114 val = ADIS16480_DRDY_EN(0);
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124 pin = ADIS16480_PIN_DIO1;
1125 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1126 irq = of_irq_get_byname(of_node, adis16480_int_pin_names[i]);
1127 if (irq > 0) {
1128 pin = i;
1129 break;
1130 }
1131 }
1132
1133 val |= ADIS16480_DRDY_SEL(pin);
1134
1135
1136
1137
1138
1139
1140 irq_type = irqd_get_trigger_type(desc);
1141 if (irq_type == IRQF_TRIGGER_RISING) {
1142 val |= ADIS16480_DRDY_POL(1);
1143 } else if (irq_type == IRQF_TRIGGER_FALLING) {
1144 val |= ADIS16480_DRDY_POL(0);
1145 } else {
1146 dev_err(&st->adis.spi->dev,
1147 "Invalid interrupt type 0x%x specified\n", irq_type);
1148 return -EINVAL;
1149 }
1150
1151 return adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1152}
1153
1154static int adis16480_of_get_ext_clk_pin(struct adis16480 *st,
1155 struct device_node *of_node)
1156{
1157 const char *ext_clk_pin;
1158 enum adis16480_int_pin pin;
1159 int i;
1160
1161 pin = ADIS16480_PIN_DIO2;
1162 if (of_property_read_string(of_node, "adi,ext-clk-pin", &ext_clk_pin))
1163 goto clk_input_not_found;
1164
1165 for (i = 0; i < ARRAY_SIZE(adis16480_int_pin_names); i++) {
1166 if (strcasecmp(ext_clk_pin, adis16480_int_pin_names[i]) == 0)
1167 return i;
1168 }
1169
1170clk_input_not_found:
1171 dev_info(&st->adis.spi->dev,
1172 "clk input line not specified, using DIO2\n");
1173 return pin;
1174}
1175
1176static int adis16480_ext_clk_config(struct adis16480 *st,
1177 struct device_node *of_node,
1178 bool enable)
1179{
1180 unsigned int mode, mask;
1181 enum adis16480_int_pin pin;
1182 uint16_t val;
1183 int ret;
1184
1185 ret = adis_read_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, &val);
1186 if (ret)
1187 return ret;
1188
1189 pin = adis16480_of_get_ext_clk_pin(st, of_node);
1190
1191
1192
1193
1194
1195 if (pin == ADIS16480_DRDY_SEL(val))
1196 dev_warn(&st->adis.spi->dev,
1197 "DIO%x pin supports only one function at a time\n",
1198 pin + 1);
1199
1200 mode = ADIS16480_SYNC_EN(enable) | ADIS16480_SYNC_SEL(pin);
1201 mask = ADIS16480_SYNC_EN_MSK | ADIS16480_SYNC_SEL_MSK;
1202
1203 if (st->chip_info->has_pps_clk_mode) {
1204 mode |= ADIS16480_SYNC_MODE(st->clk_mode);
1205 mask |= ADIS16480_SYNC_MODE_MSK;
1206 }
1207
1208 val &= ~mask;
1209 val |= mode;
1210
1211 ret = adis_write_reg_16(&st->adis, ADIS16480_REG_FNCTIO_CTRL, val);
1212 if (ret)
1213 return ret;
1214
1215 return clk_prepare_enable(st->ext_clk);
1216}
1217
1218static int adis16480_get_ext_clocks(struct adis16480 *st)
1219{
1220 st->clk_mode = ADIS16480_CLK_INT;
1221 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "sync");
1222 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1223 st->clk_mode = ADIS16480_CLK_SYNC;
1224 return 0;
1225 }
1226
1227 if (PTR_ERR(st->ext_clk) != -ENOENT) {
1228 dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
1229 return PTR_ERR(st->ext_clk);
1230 }
1231
1232 if (st->chip_info->has_pps_clk_mode) {
1233 st->ext_clk = devm_clk_get(&st->adis.spi->dev, "pps");
1234 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1235 st->clk_mode = ADIS16480_CLK_PPS;
1236 return 0;
1237 }
1238
1239 if (PTR_ERR(st->ext_clk) != -ENOENT) {
1240 dev_err(&st->adis.spi->dev, "failed to get ext clk\n");
1241 return PTR_ERR(st->ext_clk);
1242 }
1243 }
1244
1245 return 0;
1246}
1247
1248static struct adis_data *adis16480_adis_data_alloc(struct adis16480 *st,
1249 struct device *dev)
1250{
1251 struct adis_data *data;
1252
1253 data = devm_kmalloc(dev, sizeof(struct adis_data), GFP_KERNEL);
1254 if (!data)
1255 return ERR_PTR(-ENOMEM);
1256
1257 memcpy(data, &adis16480_data, sizeof(*data));
1258
1259 data->timeouts = st->chip_info->timeouts;
1260
1261 return data;
1262}
1263
1264static int adis16480_probe(struct spi_device *spi)
1265{
1266 const struct spi_device_id *id = spi_get_device_id(spi);
1267 const struct adis_data *adis16480_data;
1268 struct iio_dev *indio_dev;
1269 struct adis16480 *st;
1270 int ret;
1271
1272 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1273 if (indio_dev == NULL)
1274 return -ENOMEM;
1275
1276 spi_set_drvdata(spi, indio_dev);
1277
1278 st = iio_priv(indio_dev);
1279
1280 st->chip_info = &adis16480_chip_info[id->driver_data];
1281 indio_dev->dev.parent = &spi->dev;
1282 indio_dev->name = spi_get_device_id(spi)->name;
1283 indio_dev->channels = st->chip_info->channels;
1284 indio_dev->num_channels = st->chip_info->num_channels;
1285 indio_dev->info = &adis16480_info;
1286 indio_dev->modes = INDIO_DIRECT_MODE;
1287
1288 adis16480_data = adis16480_adis_data_alloc(st, &spi->dev);
1289 if (IS_ERR(adis16480_data))
1290 return PTR_ERR(adis16480_data);
1291
1292 ret = adis_init(&st->adis, indio_dev, spi, adis16480_data);
1293 if (ret)
1294 return ret;
1295
1296 ret = adis16480_config_irq_pin(spi->dev.of_node, st);
1297 if (ret)
1298 return ret;
1299
1300 ret = adis16480_get_ext_clocks(st);
1301 if (ret)
1302 return ret;
1303
1304 if (!IS_ERR_OR_NULL(st->ext_clk)) {
1305 ret = adis16480_ext_clk_config(st, spi->dev.of_node, true);
1306 if (ret)
1307 return ret;
1308
1309 st->clk_freq = clk_get_rate(st->ext_clk);
1310 st->clk_freq *= 1000;
1311 } else {
1312 st->clk_freq = st->chip_info->int_clk;
1313 }
1314
1315 ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
1316 if (ret)
1317 goto error_clk_disable_unprepare;
1318
1319 ret = adis16480_initial_setup(indio_dev);
1320 if (ret)
1321 goto error_cleanup_buffer;
1322
1323 ret = iio_device_register(indio_dev);
1324 if (ret)
1325 goto error_stop_device;
1326
1327 adis16480_debugfs_init(indio_dev);
1328
1329 return 0;
1330
1331error_stop_device:
1332 adis16480_stop_device(indio_dev);
1333error_cleanup_buffer:
1334 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
1335error_clk_disable_unprepare:
1336 clk_disable_unprepare(st->ext_clk);
1337 return ret;
1338}
1339
1340static int adis16480_remove(struct spi_device *spi)
1341{
1342 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1343 struct adis16480 *st = iio_priv(indio_dev);
1344
1345 iio_device_unregister(indio_dev);
1346 adis16480_stop_device(indio_dev);
1347
1348 adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
1349 clk_disable_unprepare(st->ext_clk);
1350
1351 return 0;
1352}
1353
1354static const struct spi_device_id adis16480_ids[] = {
1355 { "adis16375", ADIS16375 },
1356 { "adis16480", ADIS16480 },
1357 { "adis16485", ADIS16485 },
1358 { "adis16488", ADIS16488 },
1359 { "adis16490", ADIS16490 },
1360 { "adis16495-1", ADIS16495_1 },
1361 { "adis16495-2", ADIS16495_2 },
1362 { "adis16495-3", ADIS16495_3 },
1363 { "adis16497-1", ADIS16497_1 },
1364 { "adis16497-2", ADIS16497_2 },
1365 { "adis16497-3", ADIS16497_3 },
1366 { }
1367};
1368MODULE_DEVICE_TABLE(spi, adis16480_ids);
1369
1370static const struct of_device_id adis16480_of_match[] = {
1371 { .compatible = "adi,adis16375" },
1372 { .compatible = "adi,adis16480" },
1373 { .compatible = "adi,adis16485" },
1374 { .compatible = "adi,adis16488" },
1375 { .compatible = "adi,adis16490" },
1376 { .compatible = "adi,adis16495-1" },
1377 { .compatible = "adi,adis16495-2" },
1378 { .compatible = "adi,adis16495-3" },
1379 { .compatible = "adi,adis16497-1" },
1380 { .compatible = "adi,adis16497-2" },
1381 { .compatible = "adi,adis16497-3" },
1382 { },
1383};
1384MODULE_DEVICE_TABLE(of, adis16480_of_match);
1385
1386static struct spi_driver adis16480_driver = {
1387 .driver = {
1388 .name = "adis16480",
1389 .of_match_table = adis16480_of_match,
1390 },
1391 .id_table = adis16480_ids,
1392 .probe = adis16480_probe,
1393 .remove = adis16480_remove,
1394};
1395module_spi_driver(adis16480_driver);
1396
1397MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1398MODULE_DESCRIPTION("Analog Devices ADIS16480 IMU driver");
1399MODULE_LICENSE("GPL v2");
1400
