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47#include <linux/clk.h>
48#include <linux/interrupt.h>
49#include <linux/irq.h>
50#include <linux/irqchip/chained_irq.h>
51#include <linux/irqdomain.h>
52#include <linux/kernel.h>
53#include <linux/of_irq.h>
54#include <linux/of_platform.h>
55#include <linux/spinlock.h>
56
57#define CHANIER(n) (0x10 + (0x40 * n))
58#define CHANIPR(n) (0x20 + (0x40 * n))
59
60#define CHAN_MAX_NUM 0x8
61
62struct intmux_irqchip_data {
63 int chanidx;
64 int irq;
65 struct irq_domain *domain;
66};
67
68struct intmux_data {
69 raw_spinlock_t lock;
70 void __iomem *regs;
71 struct clk *ipg_clk;
72 int channum;
73 struct intmux_irqchip_data irqchip_data[];
74};
75
76static void imx_intmux_irq_mask(struct irq_data *d)
77{
78 struct intmux_irqchip_data *irqchip_data = d->chip_data;
79 int idx = irqchip_data->chanidx;
80 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
81 irqchip_data[idx]);
82 unsigned long flags;
83 void __iomem *reg;
84 u32 val;
85
86 raw_spin_lock_irqsave(&data->lock, flags);
87 reg = data->regs + CHANIER(idx);
88 val = readl_relaxed(reg);
89
90 val &= ~BIT(d->hwirq);
91 writel_relaxed(val, reg);
92 raw_spin_unlock_irqrestore(&data->lock, flags);
93}
94
95static void imx_intmux_irq_unmask(struct irq_data *d)
96{
97 struct intmux_irqchip_data *irqchip_data = d->chip_data;
98 int idx = irqchip_data->chanidx;
99 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
100 irqchip_data[idx]);
101 unsigned long flags;
102 void __iomem *reg;
103 u32 val;
104
105 raw_spin_lock_irqsave(&data->lock, flags);
106 reg = data->regs + CHANIER(idx);
107 val = readl_relaxed(reg);
108
109 val |= BIT(d->hwirq);
110 writel_relaxed(val, reg);
111 raw_spin_unlock_irqrestore(&data->lock, flags);
112}
113
114static struct irq_chip imx_intmux_irq_chip = {
115 .name = "intmux",
116 .irq_mask = imx_intmux_irq_mask,
117 .irq_unmask = imx_intmux_irq_unmask,
118};
119
120static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq,
121 irq_hw_number_t hwirq)
122{
123 irq_set_chip_data(irq, h->host_data);
124 irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq);
125
126 return 0;
127}
128
129static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node,
130 const u32 *intspec, unsigned int intsize,
131 unsigned long *out_hwirq, unsigned int *out_type)
132{
133 struct intmux_irqchip_data *irqchip_data = d->host_data;
134 int idx = irqchip_data->chanidx;
135 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
136 irqchip_data[idx]);
137
138
139
140
141
142
143 if (WARN_ON(intsize != 2))
144 return -EINVAL;
145
146 if (WARN_ON(intspec[1] >= data->channum))
147 return -EINVAL;
148
149 *out_hwirq = intspec[0];
150 *out_type = IRQ_TYPE_LEVEL_HIGH;
151
152 return 0;
153}
154
155static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec,
156 enum irq_domain_bus_token bus_token)
157{
158 struct intmux_irqchip_data *irqchip_data = d->host_data;
159
160
161 if (fwspec->fwnode != d->fwnode)
162 return false;
163
164 return irqchip_data->chanidx == fwspec->param[1];
165}
166
167static const struct irq_domain_ops imx_intmux_domain_ops = {
168 .map = imx_intmux_irq_map,
169 .xlate = imx_intmux_irq_xlate,
170 .select = imx_intmux_irq_select,
171};
172
173static void imx_intmux_irq_handler(struct irq_desc *desc)
174{
175 struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc);
176 int idx = irqchip_data->chanidx;
177 struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
178 irqchip_data[idx]);
179 unsigned long irqstat;
180 int pos, virq;
181
182 chained_irq_enter(irq_desc_get_chip(desc), desc);
183
184
185 irqstat = readl_relaxed(data->regs + CHANIPR(idx));
186
187 for_each_set_bit(pos, &irqstat, 32) {
188 virq = irq_find_mapping(irqchip_data->domain, pos);
189 if (virq)
190 generic_handle_irq(virq);
191 }
192
193 chained_irq_exit(irq_desc_get_chip(desc), desc);
194}
195
196static int imx_intmux_probe(struct platform_device *pdev)
197{
198 struct device_node *np = pdev->dev.of_node;
199 struct irq_domain *domain;
200 struct intmux_data *data;
201 int channum;
202 int i, ret;
203
204 channum = platform_irq_count(pdev);
205 if (channum == -EPROBE_DEFER) {
206 return -EPROBE_DEFER;
207 } else if (channum > CHAN_MAX_NUM) {
208 dev_err(&pdev->dev, "supports up to %d multiplex channels\n",
209 CHAN_MAX_NUM);
210 return -EINVAL;
211 }
212
213 data = devm_kzalloc(&pdev->dev, sizeof(*data) +
214 channum * sizeof(data->irqchip_data[0]), GFP_KERNEL);
215 if (!data)
216 return -ENOMEM;
217
218 data->regs = devm_platform_ioremap_resource(pdev, 0);
219 if (IS_ERR(data->regs)) {
220 dev_err(&pdev->dev, "failed to initialize reg\n");
221 return PTR_ERR(data->regs);
222 }
223
224 data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
225 if (IS_ERR(data->ipg_clk)) {
226 ret = PTR_ERR(data->ipg_clk);
227 if (ret != -EPROBE_DEFER)
228 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
229 return ret;
230 }
231
232 data->channum = channum;
233 raw_spin_lock_init(&data->lock);
234
235 ret = clk_prepare_enable(data->ipg_clk);
236 if (ret) {
237 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
238 return ret;
239 }
240
241 for (i = 0; i < channum; i++) {
242 data->irqchip_data[i].chanidx = i;
243
244 data->irqchip_data[i].irq = irq_of_parse_and_map(np, i);
245 if (data->irqchip_data[i].irq <= 0) {
246 ret = -EINVAL;
247 dev_err(&pdev->dev, "failed to get irq\n");
248 goto out;
249 }
250
251 domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops,
252 &data->irqchip_data[i]);
253 if (!domain) {
254 ret = -ENOMEM;
255 dev_err(&pdev->dev, "failed to create IRQ domain\n");
256 goto out;
257 }
258 data->irqchip_data[i].domain = domain;
259
260
261 writel_relaxed(0, data->regs + CHANIER(i));
262
263 irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
264 imx_intmux_irq_handler,
265 &data->irqchip_data[i]);
266 }
267
268 platform_set_drvdata(pdev, data);
269
270 return 0;
271out:
272 clk_disable_unprepare(data->ipg_clk);
273 return ret;
274}
275
276static int imx_intmux_remove(struct platform_device *pdev)
277{
278 struct intmux_data *data = platform_get_drvdata(pdev);
279 int i;
280
281 for (i = 0; i < data->channum; i++) {
282
283 writel_relaxed(0, data->regs + CHANIER(i));
284
285 irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
286 NULL, NULL);
287
288 irq_domain_remove(data->irqchip_data[i].domain);
289 }
290
291 clk_disable_unprepare(data->ipg_clk);
292
293 return 0;
294}
295
296static const struct of_device_id imx_intmux_id[] = {
297 { .compatible = "fsl,imx-intmux", },
298 { },
299};
300
301static struct platform_driver imx_intmux_driver = {
302 .driver = {
303 .name = "imx-intmux",
304 .of_match_table = imx_intmux_id,
305 },
306 .probe = imx_intmux_probe,
307 .remove = imx_intmux_remove,
308};
309builtin_platform_driver(imx_intmux_driver);
310
